Title:
RESONANT CLOCK DISTRIBUTION NETWORK ARCHITECTURE WITH PROGRAMMABLE DRIVERS
Document Type and Number:
WIPO Patent Application WO/2011/046974
Kind Code:
A3
Abstract:
A resonant clock distribution network architecture is proposed that uses clock drivers of programmable size and reference clocks of programmable duty cycle to achieve a target clock rise time and clock amplitude with low energy consumption when operating in any one of multiple clock frequencies in resonant or non-resonant mode. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.
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Inventors:
PAPAEFTHYMIOU MARIOS C (US)
ISHII ALEXANDER (US)
ISHII ALEXANDER (US)
Application Number:
PCT/US2010/052390
Publication Date:
October 13, 2011
Filing Date:
October 12, 2010
Export Citation:
Assignee:
CYCLOS SEMICONDUCTOR INC (US)
PAPAEFTHYMIOU MARIOS C (US)
ISHII ALEXANDER (US)
PAPAEFTHYMIOU MARIOS C (US)
ISHII ALEXANDER (US)
International Classes:
G06F1/04; G06F1/06
Foreign References:
| US20080150605A1 | 2008-06-26 | |||
| US5559463A | 1996-09-24 | |||
| US5122679A | 1992-06-16 |
Other References:
VISVESH S. ET AL.: "RESONANT CLOCK LATCH BASED DESIGN", IEEE, April 2008 (2008-04-01)
Attorney, Agent or Firm:
KLOKE, Daniel, C. et al. (Mullin Richter & Hampton LLP,390 Lytton Avenu, Palo Alto CA, US)
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