for Wide Input and Output Voltage Ranges

Field

This invention relates to power converters for power delivery to electronic devices and electric vehicles. More specifically, the invention relates to circuits and control methods for delivering a wide range of output voltages from a single power converter.

Background

Currently, the USB Power Delivery Standard (USB-PD) is proposed to solve the problem of incompatible output voltage levels of power adapters for cell phones, tablets, and notebook computers. The PD compatible power adapters are able to convert a universal AC voltage (such as 120V and 220V) to DC voltage and provide an output voltage adjustable from 5V to 20V for portable devices, such as cell phones, tablets, and notebook computers. The power adapter will communicate with the device it is charging, and then produce the required output voltage level that matches the need of the device. Therefore, the same power adapter can be used for multiple devices which are compatible to USB-PD. The output power of a PD adapter may be as high as 100W (20V, 5A).

A resonant converter is a good choice for a USB-PD charger because of features such as zero-voltage switching (ZVS) and high switching frequency operation, which reduces the overall size of the power adapter. However, in order to achieve 5 V to 20V output variation range, the switching frequency of the resonant converter must be changed over wide range (such as more than 3:1 ratio). When the voltage gain variation range is designed to be very wide, performance (such as efficiency) and power density are degraded.

Other applications also require very wide voltage gain variation range. One example is the DC-DC converter of an electric vehicle (EV) power system, which may have to provide 9V to 16V output voltage with 240V to 430V input voltage. This represents a voltage gain from 0.021 to 0.067, or a variation range of about 3.2 times, which is also a very challenging requirement for resonant converters. To maintain such a large voltage gain variation range, the design of the resonant converter is compromised and efficiency cannot be optimized. Summary

According to one aspect of the invention there is provided a resonant converter, comprising: first and second primary side input terminals; a primary side resonant circuit including two or more switches; a transformer having primary and secondary windings; a secondary side rectifier circuit; output points of the secondary side rectifier circuit connected to first and second secondary side output terminals; a control switch; an output capacitor connected across the first and second output terminals; and at least one controller that controls a control switch according to a selected mode; wherein a voltage at the first and second output terminals is variable according to the selected mode.

In one embodiment, the resonant converter further comprises a secondary side blocking capacitor; wherein the control switch is a secondary side control switch; wherein a first terminal of the blocking capacitor is connected to the transformer secondary winding and a second terminal of the blocking capacitor is connected to a second input terminal of the rectifier circuit; wherein a first terminal of the secondary side control switch is connected to the second terminal of the blocking capacitor and a second terminal of the secondary side control switch is connected to the second output point of the rectifier circuit; wherein the at least one controller controls the secondary side control switch according to a first selected mode so that when the secondary side control switch is off, the output voltage of the resonant converter is Vo, and according to a second selected mode so that when the secondary side control switch is on, the output voltage of the resonant converter is 2 Vo.

In one embodiment, the at least one controller controls a switching frequency of the resonant converter according to a lower switching frequency when the secondary side control switch is off, and according to a higher switching frequency when the secondary side control switch is on.

In one embodiment, the at least one controller controls a duty cycle of the secondary side control switch during a transition from off to on, wherein the duty cycle gradually increases from 0 to 1 during switching cycles over a first selected duration; and wherein the at least one controller controls the duty cycle of the secondary side control switch during a transition from on to off, wherein the duty cycle gradually decreases from 1 to 0 during switching cycles over a second selected duration. In one embodiment, the first selected duration corresponds to a duration in which a switching frequency of the resonant converter is increasing; and wherein the second selected duration corresponds to a duration in which the switching frequency of the resonant converter is decreasing.

In one embodiment, the at least one controller controls a duty cycle of the secondary side control switch within each switching cycle; wherein the output voltage of the resonant converter is determined by the duty cycle of the secondary side control switch within each switching cycle; wherein the output voltage of the resonant converter is variable from Vo to 2Vo.

In one embodiment, the at least one controller controls the secondary side control switch by: turning on the secondary side control switch during alternating negative halves of the transformer secondary current cycle; and otherwise turning off the secondary side control switch; wherein the output voltage of the resonant converter is between Vo and 2Vo.

In one embodiment, the at least one controller controls the secondary side control switch by: turning on the secondary side control switch during a selected number of consecutive negative halves of the transformer secondary current cycle; turning off the secondary side control switch during a selected number of consecutive negative halves of the transformer secondary current cycle; and otherwise turning off the secondary side control switch; wherein the output voltage of the resonant converter is between Vo and 2Vo.

In another embodiment, the resonant converter comprises a secondary side blocking capacitor; wherein the secondary side control switch is implemented with synchronous rectifiers arranged in a full bridge configuration; wherein a first terminal of the transformer secondary winding is connected to a first common point of first and third synchronous rectifiers of the full bridge; wherein a second terminal of the transformer secondary winding is connected to a first terminal of the blocking capacitor, and a second terminal of the blocking capacitor is connected to a second common point of second and fourth synchronous rectifiers of the full bridge; wherein the at least one controller controls the synchronous rectifiers according to a first selected mode so that the output voltage of the resonant converter is Vo, and according to a second selected mode so that the second synchronous rectifier is off and the fourth synchronous rectifier is on, and the output voltage of the resonant converter is 2Vo.

According to another embodiment, a reactive element of the primary side resonant circuit comprises first and second reactive elements; and the control switch is a primary side control switch; wherein the primary side control switch is connected to the first and second reactive elements; wherein the at least one controller controls the primary side control switch according to a selected mode; wherein the selected mode changes a total reactance of the first and second reactive elements; wherein a voltage at the first and second output terminals is variable according to the selected mode.

In one embodiment, the first and second reactive elements are first and second capacitors; wherein the selected mode changes a total capacitance of the first and second capacitors.

In one embodiment, the first and second reactive elements are first and second inductors; wherein the selected mode changes a total inductance of the first and second inductors.

In one embodiment, the at least one controller controls the primary side control switch according to a first mode in which the primary side control switch is off, and a second mode in which the primary side control switch is on.

In one embodiment, the at least one controller controls the primary side control switch according to a mode wherein the control switch is alternately off and on during consecutive switching cycles; wherein the voltage at the first and second output terminals is between K*Vo and Vo, where K is a number between 0 and 1.

In one embodiment, the at least one controller controls the primary side control switch according to a mode wherein the primary side control switch is off during a selected number of consecutive switching cycles, and on during a selected number of consecutive switching cycles; wherein the voltage at the first and second output terminals is between K*Vo and Vo, where K is a number between 0 and 1.

According to another embodiment, the resonant converter comprises a primary side control switch and a secondary side control switch; wherein a reactive element of the primary side resonant circuit comprises first and second reactive elements; wherein the primary side control switch is connected to the first and second reactive elements; wherein the at least one controller controls the primary side control switch according to a third selected mode; wherein the third selected mode changes a total reactance of the first and second reactive elements;

wherein a voltage at the first and second output terminals is variable between K*Vo and 2Vo, where K is a number between 0 and 1, according to the first, second, and third selected modes.

According to further aspects of the invention, there are provided methods for controlling a resonant converter including a primary side control switch, or a secondary side control switch, or primary side and secondary side control switches, as described herein. In various embodiments, the methods may include controlling the primary side control switch, or the secondary side control switch, or the primary side and secondary side control switches, according to a selected mode, wherein a voltage at the first and second output terminals is variable according to the selected mode.

In one embodiment, the method comprises controlling the secondary side control switch according to a first selected mode so that when the secondary side control switch is off, the output voltage of the resonant converter is Vo, and according to a second selected mode so that when the secondary side control switch is on, the output voltage of the resonant converter is 2Vo.

In one embodiment, the method comprises controlling a switching frequency of the resonant converter according to a lower switching frequency when the secondary side control switch is off, and according to a higher switching frequency when the secondary side control switch is on.

In one embodiment, the method comprises controlling a duty cycle of the secondary side control switch during a transition from off to on, wherein the duty cycle gradually increases from 0 to 1 during switching cycles over a first selected duration; and controlling the duty cycle of the secondary side control switch during a transition from on to off, wherein the duty cycle gradually decreases from 1 to 0 during switching cycles over a second selected duration. In one

embodiment, the first selected duration corresponds to a duration in which a switching frequency of the resonant converter is increasing; and the second selected duration corresponds to a duration in which the switching frequency of the resonant converter is decreasing.

In one embodiment, the method comprises controlling a duty cycle of the secondary side control switch within each switching cycle; wherein the output voltage of the resonant converter is determined by the duty cycle of the secondary side control switch within each switching cycle; wherein the output voltage of the resonant converter is variable from Vo to 2Vo.

In one embodiment, the method comprises controlling the secondary side control switch by: turning on the secondary side control switch during alternating negative halves of the transformer secondary current cycle; and otherwise turning off the secondary side control switch; wherein the output voltage of the resonant converter is between Vo and 2Vo.

In one embodiment, the method comprises controlling the secondary side control switch by turning on the secondary side control switch during a selected number of consecutive negative halves of a resonant transformer secondary current cycle; turning off the secondary side control switch during a selected number of consecutive negative halves of the transformer secondary current cycle; and otherwise turning off the secondary side control switch; wherein the output voltage of the resonant converter is between Vo and 2Vo.

In one embodiment, the method comprises controlling synchronous rectifiers according to a first selected mode wherein the output voltage of the resonant converter is Vo, and according to a second selected mode so that wherein the output voltage of the resonant converter is 2Vo.

In one embodiment, the method comprises controlling the primary side control switch according to a selected mode; wherein the selected mode changes a total reactance of primary side reactive elements; wherein a voltage at the first and second output terminals is variable according to the selected mode.

In one embodiment, the method comprises controlling the primary side control switch according to a mode wherein the control switch is alternately off and on during consecutive switching cycles; wherein a voltage at the first and second output terminals is between K*Vo and Vo, where K is a number between 0 and 1.

In one embodiment, the method comprises controlling the primary side control switch according to a mode wherein the primary side control switch is off during a selected number of consecutive switching cycles, and on during a selected number of consecutive switching cycles; wherein the voltage at the first and second output terminals is between K*Vo and Vo, where K is a number between 0 and 1.

In one embodiment, the method comprises controlling the secondary side control switch according to first and second selected modes, and controlling the primary side control switch according to a third selected mode; wherein the third selected mode changes a total reactance of primary side reactive elements; wherein a voltage at the first and second output terminals is variable between K*Vo and 2Vo, where K is a number between 0 and 1, according to the first, second, and third selected modes.

Brief Description of the Drawings

For a greater understanding of the invention, and to show more clearly how it may be carried into effect, embodiments will be described, by way of example, with reference to the accompanying drawings, wherein: Fig. 1 is a schematic diagram of a resonant converter, according to one embodiment.

Figs. 2 A and 2B are schematic diagrams showing equivalent circuits of the secondary side of the embodiment of Fig. 1, during the positive and negative half cycles, respectively, of a non- voltage doubler mode of operation.

Figs. 3 A and 3B are schematic diagrams showing equivalent circuits of the secondary side of the embodiment of Fig. 1, during the positive and negative half cycles, respectively, of a voltage doubler mode of operation.

Fig. 4 is a schematic diagram of a resonant converter with secondary side implemented with synchronous rectifiers, according to one embodiment.

Figs. 5A and 5B show gate drive waveforms for synchronous rectifiers of the embodiment of Fig. 4, in non- voltage doubler and voltage doubler modes, respectively.

Fig. 6 is a schematic diagram of an implementation of a resonant converter and control circuitry, according to one embodiment.

Fig. 7 is a timing diagram showing a gating signal for a switch that controls non-voltage doubler and voltage doubler modes, according to one embodiment.

Fig. 8 is a timing diagram for a switch of a voltage doubler operating in duty cycle control mode, according to one embodiment.

Fig. 9 is a plot showing a relationship between duty cycle and output voltage.

Fig. 10 is a timing diagram for a switch of a voltage doubler operating in sub-frequency control mode, according to one embodiment.

Fig. 11 is a schematic diagram of a series resonant converter (SRC) with capacitor bypassing, according to one embodiment.

Fig. 12 is an SRC gain curve for different values of resonant inductor and capacitor within a range of switching frequency.

Fig. 13 is an SRC gain curve for different values of input AC voltage and resonant capacitor, within a range of switching frequency.

Fig. 14 is a schematic diagram of an equivalent circuit of a resonant capacitor and body diode.

Figs. 15, 16, and 17 are plots showing voltage stress on resonant capacitors of the embodiment of Fig. 11, under various conditions. Fig. 18 is a schematic diagram of a series resonant converter with capacitor bypassing, according to another embodiment.

Figs. 19 and 20 are schematic diagrams of a series resonant converter with inductor bypassing, according to further embodiments.

Figs. 21 and 22 are SRC gain curves for different values resonant capacitor and resonant inductor, respectively, within a range of switching frequency.

Fig. 23 is a plot showing the voltage waveform on a resonant capacitor of the embodiment of Fig. 11, according to an operating mode when the by-passing switch is off.

Fig. 24 is a timing diagram for the embodiment of Fig. 11, under a sub-frequency operating mode.

Figs. 25 A and 25B are plots show efficiency of the embodiment of Fig. 11, for different AC input voltages.

Fig. 26 is a schematic diagram of an LLC resonant converter with capacitor bypassing, according to one embodiment.

Fig. 27 is a schematic diagram of a series resonant converter with capacitor bypassing, according to another embodiment.

Fig. 28 is a schematic diagram of a series resonant converter with capacitor bypassing and a secondary side voltage doubler, according to one embodiment.

Fig. 29 is a schematic diagram showing controllers for the embodiment of Fig. 28, according to one embodiment.

Fig. 30 is a schematic diagram of a series resonant converter with capacitor bypassing, according to another embodiment.

Figs. 31 A and 31B are timing diagrams for the embodiment of Fig. 30, according to one embodiment.

Detailed Description of Embodiments

Aspects and embodiments described herein, and variations thereof, are suitable for applications requiring wide input voltage and output voltage ranges. For example, applications may include AC-DC power delivery for low- voltage personal electronic devices such as cell phones, tablets, and laptop computers. Since the embodiments can provide a range of output voltage ranges to accommodate such devices, a single power delivery device may be used for all such devices.

Embodiments are also well-suited to DC-DC applications, including high-voltage applications such as electric vehicle (EV) charging. Since the embodiments can provide a wide range of output voltages, a single embodiment can accommodate different voltages required for different types of EVs (e.g., cars may require lower voltages than large vehicles such as trucks and buses).

Further, embodiments can accommodate a wide range of input voltages as may be determined by location (due to, for example, different line voltages such as 110-120 VAC in North America and 220-240 VAC in Europe) while maintaining the wide output voltage range.

I. Secondary Side Control Switch

According to a first aspect of the invention, variable output of an AC -DC resonant converter is achieved by implementing control of the secondary side DC output voltage.

Fig. 1 shows a resonant converter according one embodiment. The primary side is an LLC topology with half bridge switches Ql and Q2, resonant inductor Lr, magnetizing inductor Lm, and resonant capacitor Cr. The secondary side includes a full bridge rectifier (D1-D4), a blocking capacitor Cb, and one switch S, which may be referred to herein as a“doubler” switch or a“control” switch. The switch S may be, for example, a MOSFET. In some embodiments, to save cost and/or to reduce complexity, D4 can be removed and the body diode of switch S can serve as D4.

The embodiment of Fig. 1 includes a conventional primary side topology. In other embodiments, other topologies with a current source as an output, such as an LLC resonant converter, including an PWM converter, such as an isolated boost converter, etc., may also be used.

Operation of the embodiment of Fig. 1 will be described with respect to the secondary side, since the primary side operates as a conventional converter. There are several operating modes. According to a first operating mode, the full bridge rectifier operates substantially normally (non-doubler), in which case the output voltage value is denoted as Vo. In a second operating mode, the full bridge rectifier operates as a voltage doubler. In this mode the output voltage is twice the voltage in the first (full bridge) mode, i.e. 2 Vo. In the following, a detailed description of the first and second operating two modes is provided. A simulation was conducted using PSIM (PowerSim, Rockville, MD, USA) based on the design parameters of Table 1, with output voltage Vo = 10V for non-doubler mode, and 2Vo = 20V for voltage doubler mode of operation.

Table 1. Design Parameters

Non-doubler operation mode

When the switch S in Fig. 1 is not turned on, effectively S does not have any impact on the circuit operation, and the rectifier operates as a full bridge rectifier. The equivalent circuits of the positive and negative halves of the switching cycle are shown in Figs. 2A and 2B, where the dashed lines show parts of the circuit that are not in operation.

In the positive half cycle, the current direction is from Tx to Dl, Co and RL, then D4 and Cb, as shown in solid line. If the body diode of the switch S has lower forward voltage drop than D4, then it will conduct and D4 will not conduct. However, for the most part, D4 will be selected such that it has lower forward voltage drop.

In the negative half cycle, the current direction is from Tx to Cb, D2, then Co and RL, and D3, as shown in solid line.

In steady state, the current in the positive (ID1) and negative half cycle (ID3) has same magnitude but opposite direction. The blocking capacitor will be charged and discharged, respectively, once in a full switching cycle. Thus, the blocking capacitor Cb will carry no DC voltage (VCb = 0 V) but some switching-frequency level voltage ripple. In practice, the DC voltage across Cb may be a very small value.

Doubler operation mode

When the control switch S in Fig. 1 is turned on all the time, the rectifier operates as a voltage doubler rectifier. The equivalent circuits of the positive and negative halves of the switching cycle are shown in Figs. 3A and 3B, where the dashed lines show parts of the circuit that are not in operation.

In the positive half cycle, shown in Fig. 3 A, the current ID1 is from Tx to Dl, Co and RL, then S and Cb, as shown in solid line. The voltage on the transformer winding is Vo, same as in the non-doubler mode. In steady state, the blocking capacitor Cb will carry a DC voltage of VCb, with a value of Vo. The capacitor is charged in the negative half cycle. Thus, the actual output voltage is the sum of the transformer voltage and VCb, i.e., N = 2 Vo.

In the negative half cycle, shown in Fig. 3B, the current ID3 conduction path is from Tx to Cb, S and D3, as shown in solid line. The transformer winding voltage is Vo. Thus, the capacitor is charged to Vo in steady state. The output power is provided by the output capacitor Co during the negative half cycle. Therefore, the load power is transferred only during the positive half cycle by ID1.

It is noted that the voltage on the blocking capacitor Cb is different in doubler and nondoubler operation. In doubler mode, Cb carries a DC voltage the same as the winding voltage (VCb = 10V), as well as high frequency voltage ripple. In non-doubler mode, Cb only has high frequency voltage ripple with its DC value close to zero.

In this embodiment, in voltage doubler operation mode, during half of the switching cycle, energy is provided to the output by both the resonant current and the DC blocking capacitor. Therefore, the output voltage is higher. During the other half of the switching cycle, the DC blocking capacitor is charged by the resonant current to keep its voltage at the output voltage level, Vo.

Comparing the current in the diodes for the non-doubler mode of operation and the doubler mode of operation, it can be observed that both ID1 and ID3 contribute to the load current in non-doubler mode of operation, while in the doubler mode of operation, only the current in the positive half cycle, i.e., ID1, is transferred to the load. As a result, in doubler mode, the diode current stress is doubled as compared to the non-doubler mode, provided the same load current.

Synchronous rectifier voltage doubler

In low output voltage applications, a synchronous rectifier may be used to reduce the conduction loss of the rectifier. Fig. 4 shows an embodiment implanted with synchronous rectifiers (SR). With SRs, the rectifier circuit still operates in the doubler and non-doubler mode. However, no additional component other than the blocking capacitor Cb is needed to achieve the two operation modes.

In non-doubler operation, SR1 and SR4 conduct during the positive half cycle, while SR2 and SR3 conduct during the negative half cycle. This operation is the same as a conventional full bridge rectifier with synchronous rectifiers. Cb has only high frequency voltage ripple and no DC voltage. The gate drive waveforms for SR1 to SR4 are shown in Fig. 5A.

In voltage doubler operation, SR2 is always turned off, and SR4 is always on. SR1 and SR3 will be on and off alternatively. In this case, Cb will have a DC voltage bias of the output voltage. The gate drive waveforms for SR1 to SR4 are shown in Fig. 5B.

Smooth transition between voltage doubler and non-voltage doubler modes of operation

In some embodiments, the designed output voltages of the doubler mode and the non- doubler mode overlap. This may result in a current surge and a voltage spike during the transition between the two modes of operation. For example, if the output voltage range is continuous from 5V to 20V, then the non-doubler operation should be used when the output voltage is between 5 V and 10V, and doubler mode operation should be used for the output voltage between 10V and 20V. Then, at 10V, the operation is switched from non-doubler mode to doubler mode. That is, the output voltage should be regulated at the same voltage (10V in this example) for both non- voltage doubler operation and voltage doubler operation. This change of operation mode may create an output voltage spike, caused by delay in the control loop. The following embodiments eliminate the voltage spike, or reduce it to an acceptable level.

As used herein, a smooth transition means that there is either no voltage (or current) spike, or only a very small voltage (or current) spike that may be considered negligible.

One embodiment is based on the circuit shown in Fig. 1 , with the design parameters shown in Table 2. In this embodiment switching frequency control is used to regulate the output voltage when the doubler rectifier mode or non-doubler rectifier mode is selected. As shown in the example of Table 2, for the non-doubler mode the switching frequency at steady state is about 600 kHz, and for the doubler mode is about 1 MHz to achieve output voltage of 10V. In other embodiments, such as PWM converters, variable duty cycle is used for control instead of switching frequency. In a battery charging application, the output voltage is increased as the battery being charged. Thus, the transition happens only from non-doubler to doubler operation. In other cases, the transition could happen both ways (either from non-doubler operation to doubler operation or from doubler operation to non-doubler operation).

Table 2. Design Parameters for a Smooth Transition between Modes of Operation

Fig. 6 is a schematic diagram of the power stage and control circuit. In the LLC sensor and controller, the output voltage is sensed by the controller, and a PI closed-loop control is implemented inside the controller. A half-bridge PWM generation circuit generates the gate drive signals for the primary side switches Ql and Q2. A doubler switch controller is used to generate the tum-on and turn-off signals for the doubler switch S. In an alternative embodiment, the controller generates a gradually increasing/decreasing duty cycle for the doubler switch S, as described below. In one embodiment this may be implemented by a gradually increasing or decreasing reference signal being compared with a triangular ramp signal operating dynamically at the switching frequency. The changing slope of the reference signal is controlled so that the transition period can be controlled.

Closed loop control

When the voltage doubler switch S is turned on, the circuit changes the operation mode from non- voltage doubler mode to voltage doubler mode. In the example, the switching frequency is changed from 600 kHz to 1 MHz by a feedback loop. The switching frequency cannot change immediately due to the delay of the feedback loop, and may require, e.g., 500 ps for the transition, which will cause the output voltage to increase. For example, the output voltage will increase towards 20V from an initial value of 10V. Then, through feedback control, the output voltage will recover to the original value. Because of the delay in the feedback loop, a voltage spike during the transition may be relatively large, such as 20% of the initial voltage level. For example, a simulation indicated that the output voltage will rise from 10V to as high as 12V and then recover to 10V again. A faster feedback loop will reduce the voltage spike.

Similarly, when the voltage doubler switch S is turned off, the circuit will change the operation mode from voltage doubler mode to non- voltage doubler mode. . In the example, the switching frequency is changed from 1 MHz to 600 kHz by feedback loop. The switching frequency cannot change immediately due to the delay of the feedback loop, and may require, e.g., 400 ps for the transition, which will cause the output voltage to decrease. For example, the output voltage will decrease towards 5V from an initial value of 10V. Then, through feedback control, the output voltage will recover to the original value. Because of the delay in the feedback loop, the voltage spike during the transition may be relatively large, such as 20% of the initial voltage level. For example, a simulation indicated that the output voltage will decrease from 10V to as low as 8.5V and then recover to 10V. Again, implementing a fast feedback loop will reduce the voltage spike.

Closed loop and switching frequency feedforward

In order to reduce the voltage spike, switching frequency feedforward may be used. It is observed that when the converter operates in non- voltage doubler mode, and the output voltage is at the high end of the output voltage range, such as 10V, the switching frequency is at lower end of the switching frequency range, such as at 600 kHz. When the converter is switched into voltage doubler mode, the feedback circuit will increase the switching frequency to the higher end of the switching frequency range, such as 1 MHz, to maintain same output voltage.

Therefore, switching frequency feedforward may be used to reduce the voltage spike. According to one embodiment, as soon as the converter is switched from non- voltage doubler operation to voltage doubler operation by turning on the voltage doubler switch S, the switching frequency is increased from the lower end of the switching frequency range to a pre-determined higher switching frequency, such as from 600 kHz to 1 MHz. This this way, the transition time is reduced and the voltage spike can be reduced.

In one simulation based on the above example, when switching frequency feedforward was used for the transition from non-doubler mode to doubler mode, the transition time was reduced to about 50 ps and the voltage spike was reduced to about 0.15V (for 10V output voltage). Similarly, when the converter is switched from voltage doubler operation to nonvoltage doubler operation, the switching frequency is reduced to a pre-determined value, such as from 1 MHz to 600 kHz. The simulation showed that the transition time was reduced to about 50 ps and the voltage spike was also limited to about 0.3 V.

Gradual transition of switch S

It is observed from the above description of the closed loop that during the transition, the output voltage will have overshoot or undershoot, which is not desirable. It is observed that when the rectifier operates in non-doubler mode, the control switch S is always off, or equivalently, its duty cycle is zero. When the rectifier operates in doubler mode, the switch S is always on, or equivalently, its duty cycle is one (or 100%). The voltage overshoot or undershoot during the transition results from the energy imbalance between non-doubler mode and doubler mode. According to another embodiment, the duty cycle of the doubler switch S is changed gradually during the transition, which reduces the impact of the energy imbalance and the voltage overshoot and undershoot.

Fig. 7 shows a gating signal for a gradual change in the duty cycle of switch S during the transition from non-voltage doubler operation to voltage doubler operation. It is assumed that at time tl, the circuit starts the transition. At the first switching period, Tsl, the duty cycle of S is very small, such as 2%. The duty cycle of the switch S increases slowly after each switching period, as shown in Fig. 7. Near the end of the transition, the duty cycle is close to 1 (i.e., 100%). When the duty cycle is 100%, the transition is finished and the converter operates in voltage doubler mode. As long as the duty cycle increases slowly enough, the output voltage spike may be controlled to be very small. A simulation result showed that with a gradual increase in the duty cycle of switch S, the output voltage spike during the transition is less than 0.05 V, which is very small for 10V steady state voltage.

According to this embodiment, the gradual change in duty cycle may be implemented over, e.g., a 1 ms to 10 ms time period, or 100 to 1,000 switching cycles, although other time periods or numbers of switching cycles may be used. For example, consider an embodiment such as that shown in Fig. 6 with switching frequencies of 600 kHz and 1 MHz, and both a closed- loop controller and PWM control of the doubler switch S. Before the switching cycle Tsl (Fig. 7), S remains off, thus the rectifier is operating in non-doubler mode and the duty cycle of S is zero. At the instant of Tsl, S is turned on for a short period in each switching cycle. The duty cycle is then increased to 100% gradually over a duration of n switching cycles Tsn, e.g., a duration of 200 ps. After that, S remains as on, and the rectifier operates in doubler mode.

During the period that the duty cycle is changing, the closed-loop controller changes the switching frequency from 600 kHz to 1 MHz to regulate the output voltage. With the two controllers in synergy, the voltage overshoot is reduced to very small value, such as less than 1 % of the DC output voltage value.

Similarly, during the transition from doubler to non-doubler mode, the duty cycle of S may be decreased gradually from 100% to 0 within a duration of, e.g., 200 ps to 10 ms. After that, switch S remains off, and the rectifier operates in non-doubler mode. During the period that the duty cycle is changing, the closed-loop controller changes the switching frequency from 1 MHz to 600 kHz to regulate the output voltage. Again, with the two controllers in synergy, the voltage overshoot is reduced.

Duty cycle control mode

In some embodiments, PWM control of the control switch S is used in steady state as well as in the transition between voltage doubler and non- voltage doubler modes. In such embodiments, the converter runs in a hybrid operation mode, also referred to as a duty cycle control mode. In this mode, within one switching period, the converter operates in voltage doubler mode for part of the switching period and operates in non- voltage doubler mode for the other part of the switching period. The switch S conducts for a period in each switching cycle, and the rectifier operates in partly non-doubler mode and partly doubler mode. In this way, the DC blocking capacitor voltage is neither zero nor Vo; rather, it is between. Then, the output voltage is between Vo and 2Vo, depending on the duty cycle of the doubler switch S.

Duty cycle control mode will be described with reference to an embodiment based on the circuit shown in Fig. 1, the parameters listed in Table 1, and a switching frequency fixed at 1 MHz. In this mode, the switching frequency remains fixed and the output voltage Vo is variable from V to 2 V. The positive half cycle is defined as the positive transformer secondary side current (ISEC > 0). The negative half cycle is defined as the negative transformer secondary side current (ISEC < 0). In steady state, the output voltage Vo = 10V in non-doubler mode, and Vo = 20V in doubler mode.

To achieve doubler mode operation, S is turned on only during the negative half cycle of the transformer secondary side current, ISEC, because S takes effect only during the negative half cycle, while operation in the positive half cycle is the same regardless of the state of S. In other words, the effective duty cycle is from 0 to 50% for the voltage doubler switch to have an impact on the output voltage. When the duty cycle is 0 (zero), the gate signal is always low for the voltage doubler switch S, or the rectifier operates in non-doubler mode, the voltage on the blocking capacitor is 0 and the output voltage Vo is equal to the transformer winding voltage, which is 10V in this example.

Fig. 8 is a timing diagram, showing that the switch S is turned on when the transformer secondary side, ISEC, becomes negative. The switch S is turned off after it conducts for a period of TSEC. The duty cycle is defined as the ratio of the conduction time of the doubler switch, TSEC, and the switching period, Ts.

D = TSEC / T _s (1)

Since the time period of the negative current is only half of the switching period, the duty cycle is varied from 0 (zero) to 0.5. When D = 0, the circuit operates in non- voltage doubler mode and the output voltage is Vo. When D = 0.5, the operation is voltage doubler mode and the output voltage will be 2Vo. When the duty cycle is between 0 and 0.5 (in an ideal case when the dead time is not considered), the output voltage is between Vo and 2Vo.

A simulation showed that when the switch S duty cycle is 20%, the capacitor voltage VCb is 7V with the S turned on for 200 ns (i.e., a duty cycle of 20%). The output voltage Vo is 17 V. It was also observed that the power/current transferred during the positive half cycle is increased while the power/current is reduced during the negative half cycle, as compared to the case when the duty cycle is 0.

When the switch S duty cycle is 40%, the output voltage is almost 20V. In this example this is the maximum effective duty cycle, considering the theoretical max of 50% and a dead time of 10%. In other words, this is equivalent to the voltage doubler mode.

The switch S is turned on during the entire negative half cycle of the transformer secondary side current, ISEC. The power during the entire negative half cycle is used to charge Cb. Thus, the capacitor voltage VCb is 10V in this case. The output voltage Vo is double VCb, i.e., 20V. Power is transferred to the load during the positive half cycle, while during the negative half cycle, no power is transferred to the load.

The relation between the duty cycle D of the switch S and the output voltage Vo is shown in Fig. 9, based on a simulation. As the D increases from 0 to 0.4 the output voltage increases from 10V to 20V. When the duty cycle is larger than 0.4, the output voltage is maintained at 20V. It is noted that the 0.4 duty cycle includes the impact of the dead time. In an extreme case, or in theory, the duty cycle should be 0.5 to achieve full voltage doubler operation. However, in a practical application, because of the dead time, the maximum duty cycle cannot achieve 0.5.

Therefore, by controlling the conduction time of the switch S within the switching period, the output voltage can be regulated at any value between Vo and 2 Vo, such as from 10V to 20V in the above example. In this case, the switch S is turned on and off within every switching period of the resonant converter.

Sub-frequency control mode

Fig. 10 is a timing diagram for switch S according to another embodiment, based on the circuit of Fig. 1. In this embodiment, the switch S is turned on for the complete negative current cycle in a first switching period, Tsl . Then the switch S is turned off for a next switching period, Ts2, and then S is turned on for a third switching period, Ts3. The operation continues this way. With this control mode, the circuit operates in voltage doubler mode for one switching period and in non- voltage doubler mode for the next switching period. Therefore, in steady state, the output voltage will be between Vo and 2 Vo for given circuit parameters. In another embodiment, the switch S may be controlled in the following way:

(1) S is turned on for the complete negative current cycle for N switching periods continuously;

(2) S is turned off for the following M switching cycles continuously;

(3) The output voltage Vo will be between V and 2V, and will depend on the values of N and M. The values of N and M may be the same or different.

(4) Since N and M are integers, the output voltage Vo cannot be regulated continuously. The voltage Vo will be regulated in discrete values according to N and M.

(5) The switching frequency Fs or switching period Ts may be changed to achieve continuous output voltage regulation.

Advantages of this embodiment include the following:

• The switching loss of S is reduced since the switching frequency of S is lower than the switching frequency of the resonant converter. In the example shown in Fig. 10, the switching frequency of S is half of the switching frequency of the resonant converter.

• The switching frequency variation range of the resonant converter is smaller in order to regulate the output voltage between Vo and 2 Vo.

Since the switching frequency of the doubler switch S is lower than the switching frequency of the resonant converter, this control mode is referred to as sub-frequency control mode.

II. Primary Side Control Switch

According to a second aspect of the invention, variable output of an AC-DC resonant converter is achieved by implementing control of the resonant converter primary side, using a primary side control switch.

This aspect is achieved by implementing a capacitor bypassing circuit in the primary side of a series resonant converter. Embodiments solve the wide voltage range problems discussed above, by accommodating wide AC input voltages (e.g., 110-240 VAC) and providing wide DC output voltage ranges (e.g., 5-20 VDC). For wide AC input voltage, embodiments may include two resonant capacitors used respectively for two AC line voltages - e.g., 110-120 VAC, and 220-240 VAC. For wide output voltage, embodiments may use the two capacitors respectively for different output voltages. Embodiments may require an additional capacitor and switch, which add only a small increase in circuit footprint and cost, and only a small resonant inductor.

An embodiment based on a series resonant converter (SRC) topology is shown in Fig. 11. The circuit includes a primary side rectifier stage, which may be a full bridge rectifier (Dl - D4) and a bulk capacitor Cin as shown in Fig. 11, half bridge (FIB) switches Ql and Q2, and a series resonant tank circuit including a resonant inductor Lr, two resonant capacitors Crl and Cr2, and a control switch Q3. The secondary side includes a rectifier stage, for which a non-limiting example is a center-tapped configuration with synchronous rectifiers, as shown in Fig. 11. Other secondary side configurations, such as full bridge rectifiers, voltage doubler rectifiers, etc., may also be used.

In a conventional SRC, it is challenging to design the converter to use both 110-120 VAC and 220-240 VAC input line voltages, since the resonant inductor Lr value must be very large to achieve reasonable regulation performance over the large input voltage range. Embodiments described herein overcome this problem by providing what are effectively two SRC resonant tank circuits, one for each of the AC input voltages. According to the embodiment shown in Fig. 11, the switch Q3 operates in on/off mode to select the proper resonant capacitor(s) (Crl and/or

Cr2) for the different AC voltages.

Table 3 shows design parameters of an embodiment for 100 - 240 VAC input, 10 VDC, 30 W output. With 47 pF capacitor as Cin and 30 W output power, the DC voltage (Vin) on Cin is 100 - 340 VDC for 100 - 240 VAC input. More specifically, Vin is 100 - 200 VDC for 120 VAC line voltage, and Vin is 250 - 340 VDC for 220 VAC line voltage.

Table 3. Design Parameters of SRC with Capacitor Bypassing

It is noted that in a conventional SRC converter with 30 W output power, to

accommodate Vin of 100-340 VDC, a resonant inductor Lr of 60 mH must be used, if the desired switching frequency range is 500-900 kHz. The gain curve is shown in Fig. 12. With a smaller Lr, it either cannot cover the entire input voltage range, or requires a substantial increase in the switching frequency range, which makes such a design difficult to achieve in a practical application.

However, according to embodiments with capacitor bypassing as described herein, a small resonant capacitor is used for 120 VAC line, and a large resonant capacitor is used for 220 VAC line. In the embodiment of Fig. 11 and the parameters in Table 3, at 120 VAC, the MOSFET Q; remains off, and the equivalent G value is C _ri * G2 / (G _/ + G2), which is about 3 nF in this example. This set of parameters covers the 120 VAC line with a DC range of 100-200 VDC.

When the input AC voltage is changed to 220 VAC, the MOSFET Qj is turned on. Thus, C _ri is a short circuit, and G2 individually serves as the resonant capacitor. As G2 is a larger value, 40 nF in this example, the resonant frequency is reduced as compared to the 120 VAC case. Therefore, the voltage gain is also reduced within the desired frequency range. The DC voltage range is 250-340 VDC.

Fig. 13 shows the gain curves for the SRC with capacitor bypassing for the two AC lines, for an embodiment based on the parameters from Table 1. The equivalent G value is 3 nF for 120 VAC and 40 nF for 220 VAC. The actual inductor value needed is 30 mH, which is only half of the 60 mH inductor in the conventional SRC converter. If the two inductors are designed with the same core and same winding, the flux in the 60 mH inductor will be 2 times the 30 mH counterpart, due to F LJ making the core loss more than 4 times higher. If the core loss is maintained the same for the two inductors, then the copper loss of the 60 mH inductor will be 4 times higher, because the winding needs to be twice the length with half section area. Change of circuit behavior due to body diode of the control switch

Referring to the embodiment of Fig. 11, when the converter is operating with 220 VAC line, the switch Qi is turned on. Thus, all the parasitic components of Qs are ineffective.

When the converter is operating at 120 VAC line, Qi is turned off, and the impact of the parasitic components should be considered. The parasitic capacitor is directly parallel to C _ri , thus, its effect is small and can be neglected. The body diode, however, influences the circuit behavior, because the body diode changes the charging and discharging characteristics of a capacitor that is in parallel with it.

Whether the body diode conducts or not, the resonant current is of an AC shape alternating at the switching frequency. Thus, a sinusoidal current may be used for the analysis. The voltage across C _ri and C _r 2 is also be sinusoidal, and for half bridge, the capacitor should bear a DC bias, Vbias, with a value equal to half of the input DC voltage. Thus, a simplified model of Cri and C _r 2 voltage stress at 120 VAC is shown in Fig. 14. In this model, the AC voltage source vc _r-pk is defined by the peak value of the AC component on the two resonant capacitors. ¾ is the body diode of the control switch Qs.

Depending on whether ¾ conducts, two conditions should be considered. The boundary of the two conditions is Vbias = vcr _pk-

Condition A: Vhh·, vc, nk

If the resonant current is low, then the AC component will always be lower than the DC bias, i.e. V _bias > = c _r-pk - The total voltage stress on the two resonant capacitors is always positive. Thus, the diode D _M is always reverse biased. Equivalently, D _M could be removed. The voltage stress of Cri and C _r 2 is reversely proportional to the capacitor value.

Fig. 15 shows the PSIM simulation result of an example of condition^, in which the total bias voltage V _bias = 100 V, and the AC component vc _r _p _k = 50 V for G/ = 4 nF and C _r 2 = 36 nF. As the capacitance ratio of C _ri and C _r 2 is 1 :9, the impedance will be 9:1. Based on the voltage divider theory, C _ri should assume 90% of the total voltage stress - both the DC and AC components, and C _r 2 should assume 10%. Thus, for C _ri , the bias voltage Vbia _{s i} = 90 V, and the AC component vc _ri-pk = 45 V. For C _r 2, the bias voltage Vu _as 2 = 10 V, and the AC component VCr2 _pk = 5 V. Condition B: V _bi;iS < vc _{r »k}

In the condition that V _bias < vc _rjk , the minimum voltage stress on the two capacitors C _ri and C _r2 is negative. If no body diode is presented, the voltage distribution on the two capacitors will still be determined by the capacitor value in a reversely-proportional manner, despite the direction. Fig. 16 shows the voltage waveforms of the two resonant capacitors without the body diode, for Vbias < vcr _pk.

When the body diode is added in parallel with C _ri , C _ri , the voltage is always clamped as positive. As can be observed in Fig. 17, at t = 0, the two capacitors store no energy. Thus, in the first cycle when the total voltage is above zero, the two capacitors voltage stress is reverse- proportionally distributed, despite being charged or discharged.

As the total voltage decreases to negative, D _b s will conduct. Thus, the voltage across C _ri is clamped to zero. As the voltage is decreasing, the capacitors are discharging, and C _r2 bears all the negative voltage. Until the total voltage stress reaches the minimum, the two capacitors start to charge again. During the charging process, D _bi remains reverse biased, and the charging current must go through the series connected C _ri and C _r2 simultaneously. Thus, the voltage variation on CV _/ and C _r2 is maintained reversely-proportional to the capacitor value. As the starting point is zero for C _ri voltage, after a symmetrical cycle of charging and discharging, the voltage at the ending point is still zero for C _ri . Once the steady state is reached, the body diode D _b 3 does not conduct again. Thus, with the body diode, the AC voltage stress for C _ri and C _r2 is still reversely proportional to the capacitor value, while the DC bias is changed to maintain minimum voltage on C _ri as zero. As the currents in the two resonant capacitors are the same in steady state, it is concluded that the body diode only changes the DC bias.

In summary, the body diode has no impact on the circuit behavior when the resonant current/load current is low, i.e., the AC voltage stress is lower than the DC bias (Vbias > = vcr_pk ). Otherwise, the body diode will conduct for a short period during the transient and clamp the voltage on C _ri always as critical positive. The DC bias on the two resonant capacitors will then be re-distributed, and the AC component remain unchanged. This does not have an impact on the resonant current/load current.

Alternative Embodiments

The following alternative topologies have the same operating principle as that of the SRC with resonant capacitor bypassing described above.

Two Capacitors in Parallel

As shown in Fig. 18, C _ri and C _r2 may be connected in parallel instead of in series as in the embodiment of Fig. 1. Q3 is connected in series with CV2 and used as an AC line selector for selecting between 120 VAC and 240 VAC lines.

For 120 VAC, Q ₃ is turned off, and only C _ri serves as the resonant capacitor, which is a small value. For a 240 VAC line, Q ₃ is turned on, so that C _ri and C _r2 are connected in parallel, and the total resonant capacitor value is C _ri + C _r2 The body diode will also change the DC bias of C _ri and C _r2 during the transient. In steady state, the impact is small and may be neglected.

As compared to the series connected embodiment of Fig. 1, for the same effective resonant capacitor design, the peak voltage stress on Q3 is slightly higher at 120 VAC when it is turned off. This is because, for the parallel structure, Q ₃ withstands the total voltage stress, whereas for the two capacitors connected in series, Q ₃ withstands a part of the total stress.

SRC with Inductor Bypassing

Fig. 19 shows an embodiment based on an SRC, with two resonant inductors connected in series and the control switch implemented with switches Q3 and Q ₄ in back-to-back configuration such that they operate together with one control signal, i.e., they are turned on and off simultaneously and may be considered to operate as a single switch. For 120 VAC, L _ri is used as the resonant inductor. For 240 VAC, L _ri and L _r2 are connected in series and serve as the resonant inductor, with a value of L _ri + L _r2 . The control switch Q3 and Q4 is used to switch between the two AC lines. Otherwise, the inductor will have DC bias current, which is not acceptable. In practice, L _ri may be the leakage inductor from the transformer, while L _r2 is a discrete inductor.

In another embodiment, the two inductors may be connected in parallel, as shown in Fig. 20, wherein the AC line selector control switch (Q ₃ and Q ₄ in back-to-back configuration) is in series with L _r2 - At 120 VAC, Q ₃ and Q ₄ are turned off. The total inductor value is L _ri * L _ri / (Lri + L _r i). For 240 VAC, Q ₃ and Q ₄ are turned on. Thus, L _r2 is a short circuit and L _ri alone serves as the resonant inductor. In this embodiment, the two inductors discrete. Although two inductors in parallel may not be a practical solution, it is technically viable. Comparison of capacitor bypassing and inductor bypassing

According to the capacitor bypassing and inductor bypassing embodiments described herein, a different resonant tank circuit is used for each of the 120 VAC and 220 VAC line voltages. The embodiments use a small resonant capacitor/inductor value for 120 VAC, and a larger value for 220 VAC, such that the resonant frequency for 220 VAC is lower than the 120 VAC case. Then, the voltage gain may be reduced for 220 VAC. In further embodiments, capacitor bypassing and inductor bypassing may be combined to provide wider voltage variation ranges.

In terms of effectiveness, inductor bypassing is more effective than capacitor bypassing, in that only a small add-on value is needed to achieve enough gain dip for 220 VAC. Gain curves of an SRC converter with different values of capacitors and inductors are shown in Figs. 21 and 22, respectively. The values of L _r = 30 pH and C _r = 3 nF are used as the reference. In Fig. 21, the capacitors are increased to 4 nF and 5 nF. At 900 kHz, the minimum voltage gain with 4 nF is 0.43, and that of 5 nF is 0.41. As a comparison, in Fig. 22, by changing the inductors to 40 pH and 50 pH, the voltage gain is lower in the desired frequency range. At 900 kHz, the minimum voltage gain with 40 pH is 0.34, and that of 50 pH is 0.25.

The reason that inductors have more significant impact than capacitors in reducing the voltage gain is that the SRC converter is operated in the inductive region, i.e., higher than resonant frequency. If operating in the capacitive region, i.e., lower than resonant frequency, it would be observed that changing the capacitor value would have more impact on the gain.

From the point view of size, cost reduction, and simplicity, the capacitor bypassing method is a better choice. For example:

(1) Only one switch is needed for capacitor bypassing, while two switches are used for

inductor bypassing (with only one control signal), although both may be of low voltage rating.

(2) The switch used in capacitor bypassing is ground referenced, thus the driver design is much simpler than that in inductor bypassing.

(3) In practice, the resonant capacitors used in the converters are much smaller in physical size than the resonant inductors. Thus, for a compact size, capacitor bypassing should be selected. Sub-frequency control mode

In the above capacitor bypassing embodiments, the control switch Q3 is operated either on or off for a long period of time, or under steady state operation. When Q3 is on in steady state, the voltage across Crl is zero. When Q3 is off in steady state, the voltage across Crl is shown in Fig. 23. It is noted that the voltage VC _RI is the same as the drain to source voltage of Q3.

Fig. 24 shows the control signal of Q3 under sub-frequency control mode. According to this embodiment, for a first switching period, Tsl, Q3 is off. For a second switching period, Ts2, Q3 is turned on. For a third switching period, Q3 is turned off again. The sequence repeats this way. Thus, Q3 is turned on for a complete switching period in alternative switching periods. Therefore, under this control mode, the output voltage will be a value between K*Vo and Vo, where K is a number between 0 and 1. The value of K depends on the parameters of the power circuit.

A more general control case is that Q3 will be off for X switching periods and will be turned on for Y switching periods, where X and Y may be the same or different. In this condition, the output voltage will be between K*Vo and Vo, where K is between 0 and 1.

Working example

A 100 - 240 VAC input, 10 V, 30 W output prototype was built to demonstrate the effectiveness of an SRC with capacitor bypassing. The prototype was built according to Fig. 11 using the design parameters given in Table 3.

With 120 VAC, 60 Hz input the voltage on the input capacitor Cm varies from 140 V to 170 V. For this input voltage the control switch Qs was turned off, and the effective resonant capacitor value was 3 nF. The resonant inductor current had a peak value of 1 A, and the measured RMS value was 0.7 A. The output voltage was well regulated at 10 VDC.

The switching frequency for the rectified DC input voltage within 140 V and 170 V, were 650 kHz and 725 kHz, respectively, which was also the switching frequency range for 120 VAC operation. As the switching frequency increased, the resonant current had similar magnitude because of the same load current. In addition, the capacitor bypass circuit did not impact the zero voltage switching (ZVS) feature of the series resonant converter. Over the entire input voltage range, ZVS operation of the primary switches was maintained.

With 220 VAC, 50 Hz input, Qs was turned on, and the effective resonant capacitor was 40 nF. The rectified DC input voltage was within 290 V to 315 V. Again, the output voltage was well regulated at 10 VDC. The resonant inductor current had a peak value of 1.1 A, and the measured RMS value was 0.8 A throughout the input voltage range.

The switching frequency for 290 V was 740 kHz, and for 315 V was 815 kHz. As the resonant capacitor was significantly larger, the resonant period was also much longer. Thus, the resonant current was more triangular in shape rather than sinusoidal. Similar to the 120 VAC case, the resonant current did not change significantly at different input voltages, as it is determined by the load. In addition, over the entire input voltage range, ZVS operation of the primary switches was maintained. The switching frequency variation range for the entire input voltage range (110V / 220V) was 650 - 815 kHz.

Fig. 25 A shows the efficiency for different AC voltages for a 120 VAC line. At lower voltage, the rectifier current is high, so the loss is higher. At higher voltage, the resonant tank current has higher current stress, so the conduction loss and core loss increases. The peak efficiency at 93.3% is achieved around the nominal 120 VAC and 130 VAC, which is desired.

Fig. 25B shows the efficiency for different AC voltages for a 220 VAC line. The measured efficiency decreases as the AC voltage increases. This can be attributed to the increasing switching frequency, which results in higher conduction loss and core loss in the magnetic components as well as higher switching loss in the switching devices.

Capacitor bypassing for LLC converter and wide output voltage regulation

Capacitor bypassing as described herein may also be used for an LLC converter, to regulate a wide output voltage range. The following example applies to an LLC converter in, e.g., a USB power delivery application. The circuit diagram is shown in Fig. 26, and circuit parameters are given in Table 4, according to one embodiment.

The DC output voltage Vo has two levels, 5 V and 10 V with same output current of 3 A. When Vo is 10 V, a small resonant capacitor Crl of 1 nF is used, and the converter operates in below the resonance region. For 5 V output, a larger capacitor Cr2 of 20 nF is used, and the converter operates above the resonance region. Table 4. Design Parameters for an LLC Converter with Capacitor Bypassing

When the input voltage is 200 V and the output is 10 V, 3 A, the series connection of resonant capacitors Crl and Cr2 is used (Q3 is off), resonant capacitance value is 1 nF, and the resonant frequency of the resonant tank is 1100 kHz. The actual operating frequency is 900 kHz.

Thus, the converter is operating in the below resonance region.

When input voltage is 200 V and the output is at 5 V/3 A, only the resonant capacitor Cr2 of 20 nF is used (Q3 is on), and the resonant frequency of the resonant tank becomes 250 kHz. The actual operating frequency is 850 kHz. Thus, the converter is operating above the resonance region. A reduced voltage gain is achieved, with similar switching frequency as the 10 V case.

Full bridge rectifier at transformer secondary side

Fig. 27 shows an alternative SRC embodiment with capacitor bypassing, implemented with a full bridge rectifier using one secondary winding and four diodes.

Combined circuit with primary side capacitor bypassing and secondary side voltage doubler In the above aspects and embodiments, resonant converters with primary side capacitor bypassing switch and resonant converters with secondary side voltage doubler switch were described. Since the operation of the two switches (primary and secondary sides) are

independent, the two approaches may be combined in the same resonant converter, as shown in Fig. 28. Table 5 shows combinations of control methods that may be used in this embodiment. It is assumed that for a given switching frequency Fs and given set of circuit parameters of the resonant circuit, the output voltage is Vo.

Table 5. Non-Switching Operation

When both Q3 and S are off, case 12, the circuit will operate with no capacitor bypassing and no voltage doubler. The output voltage will be Vo. When Q3 is on (capacitor bypassing is activated) and S is off (non- voltage doubler operation), case 11, the output voltage is Vo 11 = K*Vo. The value K is between 0 (zero) and 1 (one). The value of K depends on the parameters of the power circuit. When both Q3 and S are on (both capacitor by-passing active and voltage doubler active), case 13, the output voltage is Vol3 = 2K*Vo. When Q3 is off (no capacitor by passing) and S is on (voltage doubler active), the output voltage is Vo 14 = 2 Vo.

Under each operating condition (case 11 to case 14), the output voltage may be regulated using switching frequency control. For example, if K = 0.75, then by setting the two switches (Q3 and S), the output voltage may be set to 0.75 Vo, Vo, 1.5 Vo, and 2Vo under the same switching frequency. This means that for the same switching frequency, the output voltage can be adjusted from 0.75Vo to 2Vo, for a variation range of 3.

The above example shows how the output voltage can be changed with different combinations of the operating condition for Q3 and S. Table 6 shows the output voltage levels under different operating conditions for Q3 when S is off.

Table 6. Output Voltage under Different Operating Conditions of Q3

The following table shows the output voltage under different operating conditions of S, when Q3 is off.

Table 7. Output Voltage under Different Operating Conditions of S

It will be appreciated that the on and off operating conditions for Q3 and S may be combined so that different output voltages can be achieved at same switching frequency.

Fig. 29 shows controllers used to achieve the above mentioned control strategy for the embodiment of Fig. 28. The primary side controller generates the gate signals for the primary side switches, which include the half bridge switches, Ql and Q2, and the bypassing switch Q3. The input signals of the primary side controller may be input voltage Vin and output voltage Vo. The gate signals for Ql and Q2 are 50% duty cycle with a small dead time in between. Switching frequency is changed to regulate the output voltage. Based on the operating conditions, the gate signal for Q3 may be a constant high voltage (on operation), a constant low voltage (off operation), or a sub-frequency switching signal that keep Q3 on for N switching periods and keep Ql off for M switching periods.

The secondary side controller uses the output voltage as the input signal. Input voltage Vin may also be used as an input signal (not shown). Based on the operating conditions, the gate signal VgateS for the voltage doubler switch S may be a constant high voltage (S on all the time, voltage doubler operation), a constant low voltage (S off all the time, non-voltage doubler operation), or a duty cycle signal, or a sub-frequency signal.

In the above discussion, it is assumed that diodes are used as full bridge rectifier. It is understood that a synchronous rectifier may also be used as the full bridge rectifier, as shown in the embodiment of Fig. 30. In this case, SR4 serves also as voltage doubler switch S.

Fig. 5A shows the gate drive signals for SR1 to SR4 under non-voltage doubler operation. In this operating condition, the gate signal of SR4 is same as the gate signal of SR1, and the gate signals for SR2 and SR3 are the same.

Fig. 5B shows the gate drive signals for SR1 to SR4 under voltage doubler operation. In this case, SR2 is off all the time (low gate voltage) and SR4 is on all the time (high gate voltage).

Fig. 31 A shows the gate drive signals for SR1 to SR4 under duty cycle operating condition. In this case, SR4 will conduct longer (TSEC) when the transformer secondary current is negative. The gate signal for SR2 is complimentary to the gate of SR4.

Fig. 31B shows the gate drive signals for SR1 to SR4 under sub-frequency operating condition, wherein the SR4 serves as the voltage doubler switch S (i.e., the control switch) and the synchronous rectifier switch (SR4 in this case). SR4 is on for the first half of the first switching period (Tsl A, when ISEC is positive) operating as synchronous rectifier. SR4 is on for the second half of the first switching period (TslB, when ISEC is negative) to operate as voltage doubler switch. In the second switching cycle, S is on for the first half (Ts2A, when ISEC is positive) as synchronous rectifier. It is turned off for the second half (Ts2B, when ISEC is negative) to operate as non-voltage doubler switch. The gate signals for SR1 and SR3 are same as in Fig. 31 A. The gate signal of SR4 is high for the first switching period (Tsl), operating at voltage doubler mode. In the second switching period, the gate signal of SR4 is high when ISEC is positive and is low when ISEC is negative value. SR2 is complimentary of SR4. SR2 is off during first switching period. In second switching period, SR2 is on when ISEC is negative.

In the above analysis it is assumed that the transformer secondary current is a sinusoidal waveform. The gate signals will be similar under a non-sinusoidal waveform.

The above embodiment may also be implemented using a full bridge primary

configuration.

Equivalents

While the invention has been described with respect to illustrative embodiments thereof, it will be understood that various changes may be made to the embodiments without departing from the scope of the invention. Accordingly, the described embodiments are to be considered merely exemplary and the invention is not to be limited thereby.