RETIMING CIRCUITS USING A CUT-BASED APPROACH

Title:

RETIMING CIRCUITS USING A CUT-BASED APPROACH

Document Type and Number:

WIPO Patent Application WO2004084277

Kind Code:

A3

Abstract:

Methods and apparatus for retiming an integrated circuit are described. According to certain embodiments, the retiming comprises performing a timing analysis (Fig. 12: 202) for one or more paths in the integrated circuit to obtain slack values (Fig. 12: 204), selecting one of the paths based on the slack values obtained (Fig. 12: 206), and determining a retimeable cut along the path selected (Fig. 12: 208). The retimeable cut in these exemplary embodiments comprises a set of input pins for one or more logic instances in the integrated circuit to which one or more retimed sequential elements can be coupled in order to improve the slack value of the path selected (Fig. 12: 210). In particular embodiments, the retimeable cut is automatically selected from multiple possible cuts along the path selected. Other embodiments for retiming integrated circuits are disclosed, as well as integrated circuits and circuit design databases retimed by the disclosed methods (Fig. 12: 216). Computer-executable media storing instructions for performing the disclosed methods are also disclosed (Fig. 12).

Inventors:

SUARIS PETER (US)
WANG DONGSHENG (US)

Application Number:

PCT/US2004/008690

Publication Date:

November 16, 2006

Filing Date:

March 18, 2004

Export Citation:

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Assignee:

MENTOR GRAPHICS CORP (US)
SUARIS PETER (US)
WANG DONGSHENG (US)

International Classes:

G06F17/50; G06F9/45; G06F9/455; H01L

Foreign References:

US6367056B1

2002-04-02

Other References: