BACKGROUND

Field

[0001] Embodiments of the present disclosure generally relate to methods and systems of controlling plasma in a process chamber.

Description of the Related Art

[0002] Processing chambers are conventionally used to perform plasma processing of substrates, such as etch or deposition processes. During etch or deposition processes, particles may be deposited on a showerhead within the processing chamber. The material deposited on the showerhead can fall on to the substrate or substrate support below and contaminate the substrate and processing volume within the chamber.

[0003] Therefore, there is a need for controlling and reducing particle generation in a processing chamber.

SUMMARY

[0004] The present disclosure generally describes a method, system, and apparatus for reducing particle generation from a showerhead. in one example, a substrate processing method is provided. The method includes supplying a first RF (radio frequency) signal having a first frequency, a first amplitude, and a first phase. The first RF signal is supplied from an RF generator to an electrode embedded in a substrate support disposed in a process chamber. A second RF signal having a second frequency, a second amplitude, and a second phase is supplied from the RF generator to the electrode. The method further includes adjusting the second RF signal relative to the first RF signal to generate ions. The adjusting the second RF signal is performed in response to a measurement of the first amplitude, the first phase, the second amplitude, and the second phase. [0005] In another example, a system for processing a substrate is disclosed. The system includes a process chamber having a substrate support disposed in a processing volume of a process chamber. A shovverhead is disposed above the substrate support in the processing volume of the process chamber. An electrode is embedded in a substrate support surface of the substrate support. An RF generator is coupled to the first electrode to supply a first RF signal having a first frequency, a first amplitude, and a first phase and a second RF signal having a second frequency, second amplitude, and a second phase to the first electrode. A controller is connected to the RF generator to adjust the second RF signal relative to the first RF signals in response to a measurement of the first and second amplitudes and phases to generate ions for etching a substrate.

[0006] In another example, an apparatus for processing a substrate is disclosed. The apparatus includes a process chamber having a substrate support disposed in a processing volume of a process chamber. A showerhead is disposed above the substrate support in the processing volume of the process chamber. An electrode is embedded in a substrate support surface of the substrate support. An RF generator is coupled to the first electrode to supply a first RF signal having a first frequency, first amplitude, and a first phase and a second RF signal having a second frequency, a second amplitude, and a second phase to the first electrode. A controller is connected to the RF generator to adjust the second RF signal relative to the first RF signal in response to a measurement of the first and second amplitudes and phases to generate ions which are maximized adjacent to the substrate support surface and minimized adjacent to the showerhead.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only exemplary embodiments and are therefore not to be considered limiting of scope, as the disclosure may admit to other equally effective embodiments.

[0008] Figure 1 depicts a schematic view of a processing system according to one embodiment of the disclosure.

[0009] Figure 2 illustrates calculated RF voltage forms according to one embodiment of the disclosure.

[0010] Figure 3 illustrates calculated RF voltage forms according to one embodiment the disclosure.

[0011] Figure 4A illustrates a calculated DC self-bias voltage form according to one embodiment of the disclosure.

[0012] Figure 4B illustrates a calculated bulk plasma potential voltage form according to one embodiment of the disclosure.

[0013] Figure 5 depicts a schematic view of a processing system according to one embodiment of the disclosure.

[0014] Figure 6 depicts a flow chart of an algorithm to identify an RF tailored voltage by attaining target RF voltage parameters according to one embodiment of the disclosure.

[0015] Figure 7 depicts a block diagram of a frequency generator according to one embodiment of the disclosure.

[0016] Figure 8 depicts a block diagram of an amplitude and phase generator according to one embodiment of the disclosure.

[0017] Figure 9 depicts a block diagram of an RF voltage monitor according to one embodiment of the disclosure. [0018] Figure 10 depicts a block diagram of an IQ detector according to one embodiment of the disclosure.

[0019] Figure 1 1 depicts a method of controlling ion bombardment in a process chamber according to one embodiment of the disclosure.

[0020] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

DETAILED DESCRIPTION

[0021] The present disclosure generally relates to plasma processing of substrates, such as etching and deposition of substrates. During etch and deposition processes, a capacitively-coupled plasma is generated between two electrodes, for example, a first electrode disposed within a substrate support and a second electrode in a sbowerhead. The substrate support electrode is connected to an RF generator and the showerhead electrode is connected to an electric ground or RF return. The plasma generated within the process chamber facilitates etching of material from, or deposition of material onto, a substrate.

[0022] Aspects of the present disclosure relate to controlling the phase and voltage of the RF signal to simultaneously control deposition or etching with respect to the substrate, while reducing particle generation {e.g., flaking) from the showerhead or other upper electrode. Moreover, aspects herein relate to identification of phase differences between frequencies to facilitate an increase in deposition or etching with respect to the substrate, while reducing the particle generation (e.g., flaking) from the showerhead or other upper electrode.

[0023] Methods and systems for reducing particle generation from a showerhead during an ion bombarding process in a process chamber are provided. A first RF signal and a second RF signal are supplied from an RF generator to a first electrode embedded in a substrate support disposed in a process chamber. The second RF signal is adjusted relative to the first RF signal in response to measured characteristics of the first and second RF signals, for example, a first amplitude and a first phase of the first RF signal and a second amplitude and a second phase of the second RF signal in some embodiments, which can be combined with one or more embodiments described above, ion bombardment on a substrate is increased and the quantity of particles generated from the showerhead is reduced. Methods and systems herein enable etching through the utilization of ion bombardment, while reducing the amount of debris particles generated from the showerhead. In addition, a method of increasing accuracy of the RF voitage/current monitor by combining information from an RF match is discussed.

[0024] Figure 1 depicts a schematic view of a processing system 100 for performing a multi-frequency bias operation in a process chamber 101. The processing system 100 includes the process chamber 101 connected to multiple RF generators 108 through an n-frequency RF match 102. The process chamber 101 includes a showerhead 103 disposed therein and connected to an electric ground 107 (or an RF return). A substrate support 104 is disposed in the process chamber 101 opposite the showerhead 103. A substrate 137 is supported by the substrate support 104. Embedded within substrate support 104 is an electrode 105. The electrode 105 is connected to the n-frequency RF match 102. The n-frequency RF match 102 applies power to the electrode 105 at a respective voltage (17) and phase ( _έ ) for each respective frequency (/)). The electrode 105 and the showerhead 103 facilitate generation of a capadtively-coupied plasma 106.

[002S] According to one embodiment, which can be combined with one or more embodiments described above, a multi-frequency bias operation is performed in the process chamber 101. During processing, the electrode 105 is biased by multiple frequencies (for example, two different frequencies), via the n-frequency RF match 102, while the showerhead 103 ( e.g ., second electrode) is connected to the electric ground 107 to facilitate RF return. In one example, frequencies applied by the n-frequency RF match 102 may be integer multiples of one another, for example, RF energy may be applied at both a first frequency of 13.56 MHz and a second frequency of 27.12 MHz. In some embodiments, which can be combined with one or more embodiments described above, the first frequency and the second frequency are harmonic frequencies. In some embodiments, which can be combined with one or more embodiments described above, the first frequency and the second frequency are adjacent harmonic frequencies.

[0026] Additionally, a surface area of the showerhead 103 is larger than a surface area of the substrate support 104.

[0027] When operating the process chamber 101 with multi-harmonic frequencies, the plasma 106, with a time averaged bulk plasma potential of V _pia , is generated with a time averaged self-bias DC voltage of V _DC formed on the substrate support 104. When using dual-frequency plasma generation, it is believed that at a certain phase value (f), ion bombardment on the substrate 137, defined by \v _pla - V _DC \, becomes nearly maximum. Simultaneously, ion bombardment on the ground side of the plasma 106 (e.g., the showerhead 103), defined by \v _pla \, becomes nearly minimum. Operating the process chamber accordingly enables maximizing etching on the substrate 137 while simultaneously minimizing particle generation from the showerhead 103. Adjusting | V _{Pia ~} V _DC \ *° nearly a maximum value while adjusting \ V _pia \ to nearly a minimum value, will be referred to hereinafter as RF tailored voltage.

[0028] The electrode 105 is connected to RF generators 1 G8i, 108 ₂ , 108 _h at frequencies of f _l f ₂ , . f _n , respectively, via the n~frequency RF match 102. In general, an RF voltage at the substrate support 104 is represented by Equation 1 :

V(t) = å ₌₁ V _t sin^- + F (1 ) where Vi and f _ί are a voltage and a phase, respectively, at f _: = and where w,- is angular frequency. To keep commensurate RF periods, the frequency [, is the /-t h harmonic frequency of a fundamental frequency f _v fi = i f ^' i where £ = 1 , 2 n (2)

Equation (2) facilitates implementation of a timing clock in hardware.

[0029] In the process chamber 101 , the plasma 106 is generated with a time averaged bulk plasm potential of V _pia A time-averaged self-bias DC voltage of V _DC forms on the surface of a substrate 137 as a result of plasma generation within the process chamber 101.

[0030] For modeling illustration, Equation (1 ) is further assumed in the form of: fί)

(3)

[0031] Furthermore, when Equation (3) is limited at n =2:

[0032] In Equation 3, an amplitude of the harmonic is normalized by that of the fundamental harmonic. As the harmonic order increases, the amplitude decreases, e.g. , the amplitude of the n-th harmonic is 1/n of the fundamental harmonic. It is believed to be advantageous to predominantly operate the fundamental harmonic for processing and other harmonics as adjusted terms to satisfy the RF tailored voltage condition where \v _pla - V _DC \ is near a maximum value and \ V _pia \ is near a minimum value.

[0033] In the dual frequency system, for example when /i= 13.56 MHz and f ₂ = 27.12 MHz, the phase difference between the two frequencies is defined by: f º f ₂ - f, (5)

[0034] Figures 2 and 3 illustrate calculated RF voltage forms according to an example. When applying a self-consistent plasma modelling to the geometry of Figure 1 with V ₁ - 200 V and f _i = 0, the voltage wave form results are obtained for f = 0°, 90°, 180°, 270° as functions of normalized time in the Figures 2 and 3. [0035] Figure 4A illustrates a calculated DC self-bias voltage form according to the example. Calcu lated V _DC formed on the substrate support 104 illustrated in Figure 1 is shown as a function of f in Figure 4A. Calculated V _pia is shown as a function of f in Figure 4B. As illustrated in Figures 4A and 4B, the minimum of \v _pla \ is about 60 V and the maximum of \v _pia - V _DC \ is about 360 V at about f = 100°.

[0036] Since the ion bombardment voltages to the electrode 106 and the showerhead 103 are given by and j V _pia - V _DC \ and \ V _pia \, respectively, plasma processing at f = 100° provides near the minimum ion bombardment on the showerhead 103, thus reducing particle generation from the showerhead 103, and near the maximum bombardment to the substrate 137 on the substrate support 104, enhancing ion etching on the substrate 137. In other words, operating at f = 100° maximizes etching rates on the substrate 137 while simultaneously minimizing particle generation from the showerhead 103. Thus, particle generation from the showerhead 103 is minimized by varying the phase difference f during a dual frequency plasma processing operation.

[0037] It is contemplated that plasma processing may occur with an n-frequency RF match 102 which uses more than two different frequencies, or with a second frequency which is an integer multiple of the first frequency, where the integer multiple is greater than 1. For example, a higher order harmonic, / ₂ , may be replaced with the third harmonic of / _j , which is 13.56 MHz, in Equation 4 (j.e., f ₂ = 40.68 MHz).

[0038] Figure 6 depicts a schematic view of a processing system 500 according to an embodiment of the disclosure, which can be combined with one or more embodiments described above. The processing system 500 is similar to the processing system 100, but includes a single n-frequency generator 508, an n-frequency RF match 502 coupled to and downstream of the n-frequency RF generator 508, and a voltage monitor 509 coupled to and downstream of the n-frequency RF match 502. While a single RF generator 508 is shown, it is contemplated that multiple RF generators may be employed in the processing system 500. [0039] To facilitate more accurate control and adjustment of processing parameters, the voltage monitor 509 detects voltage downstream of the n-frequency RF match 502, which corresponds to the voltage applied to the electrode 105 by a linear relation determined by a geometrical structure of the process chamber 501 (described hereinafter). Detecting voltage downstream of the n-frequency RF match 502 provides a more accurate indication of conditions in the process chamber 501 , thus improving adjustments made to the processing parameters.

[0040] To facilitate process control, the n-frequency RF generator 508 receives a signal from the voltage monitor 509 via a connection 510. In response, the RF generator 508 generates RF power signals at each frequency to satisfy the RF tailored voltage condition operation at the electrodes 105 and 103. The n-frequency RF generator 508 may also receive a signal from the RF match 502 via a connection 512.

[0041] Determination of phase and ampiitude adjustment, as described above, utilizes the parameters V _t and f _i (i = 1 , 2, ... n), which are defined at the substrate support 104. However, in the processing system 500, RF voltages and phases should be post-match (i.e., downstream of the RF match 502) as V _im and f _ίpi (i = 1 , 2, ... n) Hence, the derived values ) and f _ί in Equation (1 ) are transformed to post RF match 502 values defined as V _im and f _ίpi , calculated by a transform matrix: where ail values are defined as complex numbers. Hence, the values in Equation (1 ) are converted to the form of:

[0042] is defined at the substrate support 104 and is calculated, for one example, based on the modeling illustrated in Figures 2, 3, 4A, and 4B. The ABCD matrix can be calculated from the geometry of the process chamber 501 , and more specifically, a series of transmission lines and some combination of capacitors and inductors. It is noted that f _± has arbitrariness. Thus, f ₁ can be defined as f = 0 without losing generality. During operation, the RF voltage parameters V) and f, _: post RF match 502 are measured by the n-frequency RF voltage monitor 509, denoting the measured values as V _ime and f _ίpib . Experimental determination of the RF voltage parameters enables determination of an RF tailored voltage.

[0043] Figure 6 depicts a flow chart of an algorithm to identify an RF tailored voltage by attaining target RF voltage parameters V _im and f _ίpi . In some embodiments, V _im and f _ίpi are user defined target parameters in other embodiments, V _im and f _ίpi are measured parameters of a second RF signal. During operation 620, experimental parameters V _ime and f _ίpΐ£ are measured by the n-frequency RF voltage monitor 509. During operation 621 , it is determined whether the measured experimental parameters Vi _me and F _ίhΐb satisfy the conditions of Equations (8) and (9):

Fίpib Fίihb ^¾ Fίhi Fΐpi (9)

[0044] If the measured parameters V _ime and f _ίpΐ£ satisfy Equations (8) and (9) within a user-defined tolerance, no adjustments are performed on the n-frequency RF generator 508. The user-defined tolerance is empirical, typically. The user-defined tolerance of the amplitude ratio (Equation 8) is about 5 percent, for example, between about 3 percent and about 7 percent, such as between about 4 percent and about 6 percent. The user-defined tolerance for the relative angle (Equation 9) is between about 3 degrees and about 8 degrees, for example, between about 4 degrees and about 6 degrees. However, if the algorithm of operation 621 is not satisfied by the measured values of V _ime and f _ί!hb , an amplitude A and a phase q of a seed RF voltage (see Figure 7) is generated inside the n-frequency RF generator 508 through a negative feedback control, e.g., a proportional integral derivative (RID) controller, performed inside of a micro control unit (MCU), as illustrated in operation 622. Stated otherwise, the RID and MCU facilitate adjustment of the n-frequency RF generator 508, in response to the measured values V _ime and f _ίthb , to effect a desired voltage and phase downstream of the RF match 502. The feedback control is performed for each frequency, f _l where i = 2, 3,...n while A and q are constant.

[0045] In one example, operation 620 is subsequently followed by operation 621 if operation 621 is satisfied, processing of the substrate proceeds without adjustment to voltage and phase. If operation 621 is not satisfied, operation 622 is performed and operations 620-622 are repeated until operation 621 is satisfied.

[0046] In some examples, the n-frequency RF voltage monitor 509 may be not sufficiently precise at frequencies over 40 MHz because both RF voltage and current downstream of the RF match 502 are relatively high, and the phase angle between these two is close to 90 degrees. At around a 90 degree phase angle, a small difference, for example, 1 degree, results in a large difference in power and can lead to erroneous readings of the RF voltage and/or current in such a case, the complex-

valued impedance Z _ime (shown in Figure 7) is determined by Z _ime =— , where Y _ime is

Y ime

the admittance at a frequency f _{i t} which is derived from the RF matching condition inside the n-frequency RF match 502 and can be used to calculate v _ime in Equation (10): where P _ime is a power delivered to the process chamber, such as the process chamber 501 depicted in Figure 5, at the frequency, f _t . The measurement of Z _tme is calibrated by a vector network analyzer (not shown) disposed in the RF match 502. Thus, Equation (10) is highly accurate.

[0047] It is noted that the n-frequency RF voltage monitor 509 is used to measure phase angles, <p _irne , which include systematic errors when measuring the absolute value of the phase angles. However, the systematic error is cancelled by the subtraction in Equation (9). Additionally, the statistical error of the derived values is reduced by using time-average variables, thus improving accuracy of the derived results. Consequently, the effect of error in Equation (9) can be alleviated. [0048] Figure 7 is a block diagram of the n-frequency RF generator 508 illustrated in Figure 5. The n-frequency RF generator 508 includes a phase-locked loop (PLL) circuit 720, a frequency divider 722, an MCU 724, a user interface 726, one or more generators 728a-728c (three are shown), and one or more power amplifiers 71 1 (three are shown) each connected to a respective generator 728a-728c. The PLL circuit 720 receives a signal from a crystal oscillator or an external clock generator 710 to generate a clock signal of CLK = N f _n , where N is an arbitrary integer, e.g., 2 ² - 2 ^ώ . The CLK signal is transmitted to the frequency divider 722 to generate a set of CLK signals CLK i (where i = 1 ,....n), each of which is transmitted to a respective generator 728a-72Sc configured to generate an amplitude and phase at a frequency of /).

[0049] The CLK signal is also transmitted to an n-frequency RF-vo!tage monitor (such as n-frequency RF voltage monitor 509) that measures V _ime and 4> _ime at /). As shown in Equation (10), V _ime can be replaced with the measurement of the voltage at the n-frequency RF match 502. The values of V _ime and d> _ime are provided to the MCU 724, which calculates an amplitude A and a phase q for a seed RF voltage through a RID controller as shown in Figure 6 from the measured values V _ime , f _ίihb and the target values V _im , <p _im input by a user at the user interface 726 The amplitude A',· and the phase q represent the adjustment to the measured values of V _ime and <t> _ime . Once the measured values of V _ime and <p _ime match the target values of V _im and <p _im , respectively, the RF signal is applied to the electrode 105 illustrated in Figures 1 and 5.

[0950] Figure 8 depicts a block diagram of an amplitude and phase generator 728a, according to an embodiment of the disclosure, which can be combined with one or more embodiments described above. It is to be understood that generators 728b and 728c are similarly configured. Using information of A’.cose’i and A’isine’i received from the MCU 724 shown in Figure 7, an In-and-Quadrature phase (IQ) modulation operation at CLKf = N f synthesizes a digital seed signal of where p = 0, 1...N-

1 , eventually converting the digital seed signal to an analog seed of in the digital to analog converter (DAC) 830. As shown in Figure 7, the signal from the RF generator A'isinfait + Q/) is amplified by a power amplifier 71 1 to A _; s (&> J + 0 _< ). The amplified signal of A^ίh w^ + 0*) is transmitted to the n-frequeney RF match 502 which converts the amplified signal to V _iTne sm(a it + f _ίpib ) at the output of the RF match.

[0051] Figure 9 is a diagram of the n-frequency RF voltage monitor 509 receiving the basic dock signal of CLK = N f _n from the n-frequency RF generator 508. An analog voltage detector 902, e.g., a capacitive voltage divider, measures n-set of RF voltages in the form of V' _ime sinfoj _j t + p _ime ) at a frequency of f _t (i = 1 ,. ..n), where V _ime and V _ime are related by a scale factor. The frequency divider 722 generates n-set of CLK i {i = 1 ,....n) to operate respective IQ detectors 936a-936c (three are shown) at a frequency of /). The IQ detectors 936a-936c derive V _ime and <p _ime from the input RF voltage lustrates a block diagram of an IQ detector 936 at a frequency of f _t alog to digital converter (ADC) 1038 converts the analog input of from the analog voltage defector 902 to the digital value of The digital value is multiplied by cos ^{: ?} ~~- from the ROM 1039. The converted signal is transmitted to low pass filters (LPF) 1040. The low pass filters produce the output of ~ [V ^! _ime ] The output of the low Pass filters is transmitted to a digital signal processor (DSP) 1041. The DSP 1041 may include a coordinate rotation digital computer (CQRDIC). A CQRDIC algorithm and other digital signal processing are utilized to derive V _ime and f _ίpib .

[0053] Figure 1 1 depicts a method 1 100 of controlling ion bombardment in a process chamber according to an embodiment of the disclosure, which can be combined with one or more embodiments described above. During operation 1 1 10, a first RF signal having a first frequency, a first amplitude, and a first phase is transmitted from an RF generator to an electrode embedded in a substrate support in a process chamber.

[0054] During operation 1 120, a second RF signal having a second frequency, a second amplitude, and a second phase is transmitted from the RF generator to the electrode. In one embodiment, which can be combined with one or more embodiments described above, the second RF signal has a harmonic frequency of the frequency of the first RF signal. During operation 1 130, the second RF signal is adjusted relative to the first RF signal in response to a measurement of the first amplitude, the first phase, the second amplitude, and second phase. In one embodiment, which can be combined with one or more embodiments described above, an amplitude and a phase for a seed RF voltage as discussed above is determined based on the measurements of the first RF signal and the second RF signal. The amplitude and the phase of the seed RF voltage may be used to adjust the second RF signal. At operation 1 140, ion bombardment on a substrate is increased and particle generation on a showerhead disposed in the chamber is decreased as a result of the RF modulation.

[0055] Utilization of the method 1 100 for plasma processing reduces particles generated from the showerhead by identifying the phases f _int (i = 2,...n) at which the I V _p/ aj becomes nearly minimum, as shown above. At f _iih ( i = 2,. .n), it is also identified that | V _pia - VDC | becomes nearly maximum, thus maximizing deposition or etching on the substrate while simultaneously reducing particle generation from the showerhead. The | Vpia - VDC I corresponds to ionized particle impact on the substrate during etching or deposition, and the \ V _pia \ corresponds to ionized particle impact on the showerhead. Therefore, by identifying the phases where the voltage on the substrate support is maximized and the voltage on the showerhead is minimized, ionized particle impact at the showerhead is minimized (reducing particle flaking from the showerhead) while deposition and/or etching is increased and/ or maximized at or adjacent to the substrate.

[0056] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.