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Title:
RIPPLE SUPPRESSION CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2018/196654
Kind Code:
A1
Abstract:
A ripple suppression circuit comprising a first transistor, a second transistor and a third transistor; the first transistor being connected in series to the second transistor to form a Darlington transistor; and the third transistor being connected in parallel to the Darlington transistor formed by the first transistor and the second transistor to control on/off of the Darlington transistor.

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Inventors:
MAO, Egbert (3-4 Floor, Building A11Silicon Valley Power Qinghu Industry Zone, Long Hua, Baoan Distric, Shenzhen Guangdong 9, 518109, CN)
CHEN, Steven (3-4 Floor, Building A11Silicon Valley Power Qinghu Industry Zone, Long Hua, Baoan Distric, Shenzhen Guangdong 9, 518109, CN)
ZHONG, Scotty (3-4 Floor, Building A11Silicon Valley Power Qinghu Industry Zone, Long Hua, Baoan Distric, Shenzhen Guangdong 9, 518109, CN)
Application Number:
CN2018/083338
Publication Date:
November 01, 2018
Filing Date:
April 17, 2018
Export Citation:
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Assignee:
TRIDONIC GMBH & CO KG (Faerbergasse 15, Dornbirn, Dornbirn, AT)
MAO, Egbert (3-4 Floor, Building A11Silicon Valley Power Qinghu Industry Zone, Long Hua, Baoan Distric, Shenzhen Guangdong 9, 518109, CN)
International Classes:
H02M7/217; H02M1/14
Foreign References:
CN206850681U2018-01-05
GB201719319D02018-01-03
CN102412743A2012-04-11
CN104283418A2015-01-14
CN102570798A2012-07-11
US4920307A1990-04-24
Attorney, Agent or Firm:
BEIJING SANYOU INTELLECTUAL PROPERTY AGENCY LTD. (16th Fl, Block A Corporate Square,No.35 Jinrong Street, Beijing 3, 100033, CN)
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