Title:
RISING EDGE DETECTION CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2015/176572
Kind Code:
A1
Abstract:
Disclosed is a rising edge detection circuit composed of a bistable storage unit, an asymmetric delay circuit, an inverter and a plurality of NMOS transistors, so long as the asymmetric delay circuit meets the conditions that a sum of a rising edge delay and a falling edge delay is larger than a pulse period of an input signal and the falling edge delay is very small, an output signal with the maximum pulse width close to the pulse period of the input signal can be generated, so as to meet the use requirements of a follow-up device. The present invention not only is simple in structure, but also has a self-starting function, and the self-starting can be achieved when the initial low level length of the input signal is larger than the rising edge delay of the asymmetric delay circuit.
Inventors:
ZHANG JIANWEI (CN)
WU GUOQIANG (CN)
ZHANG XIUZHE (CN)
CHEN XIAOMING (CN)
TANG ZHENAN (CN)
ZHENG SHANXING (CN)
DING QIUHONG (CN)
TENG FEI (CN)
LI JIAQI (CN)
MA WANLI (CN)
WU GUOQIANG (CN)
ZHANG XIUZHE (CN)
CHEN XIAOMING (CN)
TANG ZHENAN (CN)
ZHENG SHANXING (CN)
DING QIUHONG (CN)
TENG FEI (CN)
LI JIAQI (CN)
MA WANLI (CN)
Application Number:
PCT/CN2015/073929
Publication Date:
November 26, 2015
Filing Date:
March 10, 2015
Export Citation:
Assignee:
UNIV DALIAN TECH (CN)
International Classes:
H03K5/1534
Foreign References:
| CN104038185A | 2014-09-10 | |||
| CN203933573U | 2014-11-05 | |||
| CN101398447A | 2009-04-01 | |||
| CN101546995A | 2009-09-30 | |||
| US20090189644A1 | 2009-07-30 | |||
| US7508242B2 | 2009-03-24 |
Attorney, Agent or Firm:
DALIAN FEIFAN PATENT AGENCY (CN)
大连非凡专利事务所 (CN)
大连非凡专利事务所 (CN)
Download PDF:
Previous Patent: HYBRID POWER VEHICLE
Next Patent: ELECTRONIC EYESIGHT EXAMINATION SYSTEM ADOPTING DOUBLE-BLIND DESIGN
Next Patent: ELECTRONIC EYESIGHT EXAMINATION SYSTEM ADOPTING DOUBLE-BLIND DESIGN