Title:
ROBUST ESD PROTECTION CIRCUIT, METHOD AND DESIGN STRUCTURE FOR TOLERANT AND FAILSAFE DESIGNS
Document Type and Number:
WIPO Patent Application WO/2010/120428
Kind Code:
A3
Abstract:
A robust ESD protection circuit, method and design structure for tolerant and failsafe designs are disclosed. A circuit (200) includes a middle junction control circuit (250) that turns off a top NFET (225) of a stacked NFET electrostatic discharge (ESD) protection circuit (pad 215, ground 220, top NFET 225, bottom NFET 230, top resistor 235, and bottom resistor 240) during an ESD event.
Inventors:
CAMPI JOHN B (US)
CHANG SHUNHUA T (US)
CHATTY KIRAN V (US)
GAUTHIER ROBERT J (US)
LI JUNJUN (US)
MUHAMAD MUJAHID (US)
CHANG SHUNHUA T (US)
CHATTY KIRAN V (US)
GAUTHIER ROBERT J (US)
LI JUNJUN (US)
MUHAMAD MUJAHID (US)
Application Number:
PCT/US2010/027774
Publication Date:
January 13, 2011
Filing Date:
March 18, 2010
Export Citation:
Assignee:
IBM (US)
CAMPI JOHN B (US)
CHANG SHUNHUA T (US)
CHATTY KIRAN V (US)
GAUTHIER ROBERT J (US)
LI JUNJUN (US)
MUHAMAD MUJAHID (US)
CAMPI JOHN B (US)
CHANG SHUNHUA T (US)
CHATTY KIRAN V (US)
GAUTHIER ROBERT J (US)
LI JUNJUN (US)
MUHAMAD MUJAHID (US)
International Classes:
H01L21/336; H01L23/60
Foreign References:
| US20050237681A1 | 2005-10-27 | |||
| US20030007298A1 | 2003-01-09 | |||
| US5930094A | 1999-07-27 |
Other References:
See also references of EP 2419931A4
Attorney, Agent or Firm:
CANALE, Anthony J. (Intellectual Property Law 972E1000 River Stree, Essex Junction Vermont, US)
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