FABRICATION

TECHNICAL FIELD

Embodiments of the invention are in the field of integrated circuit fabrication and, in particular, resistive random access memory (RRAM) devices having a bottom oxygen exchange layer and their methods of fabrication.

BACKGROUND

For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. It has become increasingly significant to rely heavily on innovative fabrication techniques to meet the exceedingly tight tolerance requirements imposed by scaling.

Non-volatile embedded memory with RRAM devices, e.g., on-chip embedded memory with non-volatility can enable energy and computational efficiency. However, the technical challenges of creating an appropriate stack for fabrication of RRAM devices that exhibit high device endurance, high retention and operability at low voltages and currents presents formidable roadblocks to commercialization of this technology today. Specifically, the objective of memory technology to control tail bit data in a large array of memory bits necessitates tighter control of the variations in metal oxide break down and switching events in individual bits. Furthermore, in filamentary RRAM systems, the latter is dictated by fine tuning oxygen vacancy concentration which is widely understood to drive filament formation and dissolution in metal oxide films. As such, significant improvements are still needed in the area of metal oxide stack engineering which rely on material advancements, deposition techniques or a combination of both. This area of process development is an integral part of the non-volatile memory roadmap.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1A illustrates a cross-sectional view of a resistive random access memory (RRAM) cell which includes an RRAM device with a top electrode and a top electrode contact layer formed in an opening in a dielectric hardmask above a metal oxide switching layer, in accordance with an embodiment of the present invention.

Figure IB illustrates a partial cross-sectional view of an array of RRAM cells of the type illustrated in Figure 1A, in accordance with an embodiment of the present invention.

Figure 2A illustrates a cross-sectional view of a resistive random access memory (RRAM) cell which includes an RRAM device with a scaled top electrode formed in an opening in a dielectric hardmask above a metal oxide switching layer, in accordance with an embodiment of the present invention.

Figure 2B illustrates a partial cross-sectional view of an array of RRAM cells of the type illustrated in Figure 2A, in accordance with an embodiment of the present invention.

Figures 3A-30 illustrate cross-sectional views representing various operations in a method of fabricating an RRAM device, in accordance with an embodiment of the present invention.

Figure 3A illustrates a conductive interconnect surrounded by a first dielectric layer.

Figure 3B illustrates the structure of Figure 3A following the formation of a material layer stack on the conductive interconnect and on the first dielectric layer.

Figure 3C illustrates a resist pattern formed on a dual dielectric hardmask layer composed of a first dielectric hardmask formed on a second dielectric hardmask formed on the material layer stack.

Figure 3D illustrates the structure of Figure 3C following an etch process used to transfer the resist pattern into the second dielectric hardmask layer to form a second dielectric hardmask partem, followed by removal of the resist partem.

Figure 3E illustrates the structure of Figure 3D following an etch process used to transfer the second dielectric hardmask pattern into the first dielectric hardmask and the material layer stack to form a dual hardmask layer and a patterned material layer stack.

Figure 3F illustrates the structure of Figure 3E following the formation of a dielectric spacer layer covering the dual hardmask layer, the patterned material layer stack and the first dielectric layer.

Figure 3G illustrates the structure of Figure 3F following an anisotropic plasma etch of the dielectric spacer layer to form a dielectric spacer.

Figure 3H illustrates the structure of Figure 3G following formation of a second dielectric layer covering the dual hardmask layer, the patterned material layer stack, the dielectric spacer, and the first dielectric layer.

Figure 31 illustrates the structure of Figure 3H following planarization to form coplanar surfaces of the first dielectric layer, the dielectric spacer, and the first dielectric hardmask.

Figure 3 J illustrates the structure of Figure 31 following formation of a third dielectric layer on the coplanar surfaces of the first dielectric layer, the dielectric spacer, and the first dielectric hardmask.

Figure 3K illustrates the structure of Figure 3 J following patterning of a photoresist material to form a mask to define a via location.

Figure 3L illustrates the structure of Figure 3K following an etch process to create an upper portion of a via in the third dielectric layer, followed by mask removal.

Figure 3M illustrates the structure of Figure 3L following an etch process to form a lower portion of the via in the first dielectric hardmask, the via exposing the metal oxide switching layer.

Figure 3N illustrates the structure of Figure 3M following formation of a top electrode layer and a top electrode fill layer in the via.

Figure 30 illustrates the structure of Figure 3N following planarization to form a top electrode.

Figures 4A-4K illustrate cross-sectional views representing various operations in another method of fabricating an RRAM device, in accordance with another embodiment of the present invention.

Figure 4A illustrates the structure of Figure 3H following planarization of the second dielectric layer.

Figure 4B illustrates the structure of Figure 4A following patterning of a photoresist material to form a mask to define a first via location.

Figure 4C illustrates the structure of Figure 4B following an etch process to create an upper portion of a first via in the second dielectric hardmask layer, followed by a mask removal.

Figure 4D illustrates the structure of Figure 4C following an etch process to form a lower portion of the first via in the first hardmask layer, the first via exposing the metal oxide switching layer.

Figure 4E illustrates the structure of Figure 4D following formation of a top electrode metal layer in the first via and on the metal oxide switching layer.

Figure 4F illustrates the structure of Figure 4E following a planarization process to form a top electrode.

Figure 4G illustrates the structure of Figure 4F following formation of a third dielectric layer on the coplanar surfaces of the second dielectric layer, the dielectric spacer, the first dielectric hardmask layer and the top electrode.

Figure 4H illustrates the structure of Figure 4G following patterning of a photoresist material to form a mask to define a second via location. Figure 41 illustrates the structure of Figure 4H following an etch process to create a second via in the third dielectric layer, followed by mask removal.

Figure 4J illustrates the structure of Figure 41 following formation of a top electrode contact in the second via.

Figure 4K illustrates the structure of Figure 4J following a planarization process to form a top electrode contact.

Figure 5A illustrates a cross-sectional view representing an RRAM device where the width of a bottom electrode is smaller than the width of a conducive interconnect, in accordance with an embodiment of the present invention.

Figure 5B illustrates a cross-sectional view representing an RRAM device where the width of a bottom electrode is smaller than the width of a conducive interconnect, and the interconnect includes a capping layer, in accordance with an embodiment of the present invention.

Figures 6A-6D illustrate cross-sectional views representing various operations in a method of fabricating a bottom electrode integrated on a conductive interconnect, in accordance with an embodiment of the present invention.

Figure 7A illustrates a cross-sectional view representing an RRAM device where the width of a bottom electrode and the width of the top electrode may each be independently controlled with respect the width of the oxygen exchange layer, in accordance with an embodiment of the present invention.

Figure 7B illustrates a cross-sectional view representing an RRAM device where the width of a bottom electrode and the width of the top electrode can be controlled independently of the size of the oxygen exchange layer, in an embodiment of the present invention.

Figure 8 illustrates a cross-sectional view of a conventional RRAM device.

Figure 9A illustrates an I-V plot, demonstrating concepts involved with filament formation and voltage cycling (reading and writing) in an RRAM device, in accordance with embodiments of the present invention.

Figure 9B illustrates illustrates a cross-sectional view of a resistive random access memory (RRAM) cell which includes an RRAM device having a bottom oxygen exchange layer and a filament formed in a metal oxide switching layer formed on the bottom oxygen exchange layer, in accordance with an embodiment of the present invention.

Figure 10 illustrates a cross-sectional view of an RRAM element coupled to a drain side of a select transistor, in accordance with an embodiment of the present invention.

Figures 11 A-l IE illustrate schematic views of several options for positioning an RRAM element in an integrated circuit, in accordance with embodiments of the present invention. Figure 12 illustrates a schematic of a memory bit cell which includes a metal-conductive oxide-metal RRAM device, in accordance with embodiments of the present invention.

Figure 13 illustrates a block diagram of an electronic system, in accordance with embodiments of the present invention.

Figure 14 illustrates a computing device in accordance with embodiments of the present invention.

Figure 15 illustrates an interposer in accordance with embodiments of the present invention. DESCRIPTION OF THE EMBODIMENTS

Resistive random access memory (RRAM) devices having a bottom oxygen exchange layer and their methods of fabrication are described. In the following description, numerous specific details are set forth, such as novel structural schemes and detailed fabrication methods in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known features, such as switching operations associated with embedded memory, are described in lesser detail in order to not unnecessarily obscure embodiments of the present invention. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as "upper", "lower", "above", and "below" refer to directions in the drawings to which reference is made. Terms such as "front", "back", "rear", and "side" describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

To provide context, integrating a memory array with low voltage logic circuitry, such as logic circuitry operational at a voltage less than or equal to 1 Volt, may be advantageous since it enables higher operation speeds compared to having physically separate logic and memory chips. Additionally, approaches for integrating an RRAM device onto a transistor to create embedded, one transistor-one resistor memory, or 1T-1R memory, presents material challenges that have become far more formidable with scaling. As transistor operating voltages are scaled down in an effort to become energy efficient, RRAM memory devices that are connected in series with such transistors are also required to function at lower voltages and currents.

Figure 8 illustrates a cross-sectional view of a conventional RRAM device 800. The RRAM device 800 includes a top electrode 812, an oxygen exchange layer 810, a metal oxide switching layer 808, and a bottom electrode 806. The RRAM device 800 is above an interconnect 804 formed in a dielectric layer 802 above a substrate 801.

In one embodiment, the RRAM device 800 exhibits limitations when operating with an NMOS transistor operating in one particular mode. Limitations arising from high switching current needs of an RRAM device 800 connected in series with one such NMOS transistor, may prevent an RRAM device 800 from switching between low and high resistance states. In an embodiment, an RRAM device with an oxygen exchange layer inserted directly above a bottom electrode layer but below a metal oxide switching layer (to form a bottom OEL) serves to lower the switching current demands on such an NMOS transistor operating in a given mode. In one such embodiment, device cycling between low and high resistance states can be repeatedly performed. Additional advantages of a bottom OEL may include potentially minimizing additional parasitic resistance otherwise arising from deposition of a metal oxide switching layer directly on a bottom electrode. However, when an oxygen exchange layer is formed between a metal oxide switching layer on one side and a bottom electrode on another, the top electrode formed on the metal oxide switching layer may be required to possess a higher work function than the bottom electrode. Additional restrictions may arise on the choice of top electrode materials. In one such embodiment, a top electrode includes a metal such as but not limited to Pt, Pd and W. Unfortunately, however, such metals often present formidable etch challenges which are even greater to overcome as device dimensions are scaled. Thus, in accordance with embodiments of the present invention, a damascene process is used to form a top electrode without the need for etching. Such a top electrode may be formed to provide an RRAM device having a metal oxide switching layer formed on a bottom oxygen exchange layer which is formed on a bottom electrode.

In accordance with embodiments of the present invention, various examples of RRAM devices including bottom oxygen exchange layer are described in association with Figures 1A- 1 B and Figures 2 A-2B .

Figure 1A illustrates a cross-sectional view of a resistive random access memory (RRAM) cell which includes an RRAM device 100 with a top electrode 122 and a top electrode contact layer 124 formed in an opening 130 in a dielectric layer 120 and a dielectric hardmask layer 112 above a metal oxide switching layer 110, in accordance with an embodiment of the present invention. The RRAM device 100 is disposed on a conductive interconnect 104 and a first dielectric layer 102. In an embodiment, the conductive interconnect 104 includes a barrier layer, such as tantalum nitride, and a fill material, such as copper, as is known in the art. The conductive interconnect 104 is disposed within a dielectric layer 102 disposed above a substrate 101.

The RRAM device 100 includes a bottom electrode 106 disposed above the conductive interconnect 104. An oxygen exchange layer 108 is disposed on the bottom electrode 106. A metal oxide switching layer 110 is disposed on the oxygen exchange layer 108. A first dielectric hardmask layer 112 is disposed on the metal oxide switching layer 110. A dielectric spacer 116 is disposed along sidewalls of the bottom electrode 106, the oxygen exchange layer 108, the metal oxide switching layer 110, the first dielectric hardmask layer 112 and on the first dielectric layer 102. The dielectric spacer 116 extends from the uppermost surface of the first dielectric layer 102 to an upper most surface of the first dielectric hardmask layer 112. A second dielectric layer 118 is disposed on the first dielectric layer 102 and laterally adjacent to the dielectric spacer 116. An uppermost surface of the second dielectric layer 118 is coplanar or substantially coplanar with an uppermost surface of the dielectric spacer 116 and the uppermost surface of the first dielectric hardmask layer 112. A third dielectric layer 120 is disposed on the second dielectric layer 118, on the dielectric spacer 116 and on the first dielectric hardmask layer 112. The top electrode 122 is disposed in the opening 130 disposed in the third dielectric layer 120 and first dielectric hardmask layer 112. The top electrode contact layer 124 is disposed on the top electrode 122. In an embodiment the top electrode contact layer 124 fills the opening 130.

In an embodiment, the bottom electrode 106 extends laterally onto a portion of the dielectric layer 102, as is depicted. In an embodiment, the bottom electrode 106 includes a material such as but not limited to titanium nitride, tantalum, tantalum nitride, tungsten or ruthenium. In an embodiment, the bottom electrode 106 has a thickness in the range of 40 to 100 nanometers (nm). In an embodiment, the bottom electrode 106 has a width, Wbe, approximately equal to a width, Wd, of the conductive interconnect 104. In an embodiment, the composition and thickness of the bottom electrode 106 are tuned to meet specific device attributes such as series resistance, programming voltage and current.

The oxygen exchange layer 108 is formed on the bottom electrode 106. In an embodiment the oxygen exchange layer 108 is composed of a metal such as but not limited to, hafnium, tantalum or titanium. In an embodiment, the oxygen exchange layer 108 has a thickness in the range of 5-20nm. In an embodiment, the oxygen exchange layer 108 acts as a source of oxygen vacancy or as a sink for O ^2" . In an embodiment, the metal oxide switching layer 1 10 is formed directly on the oxygen exchange layer 108. In an embodiment, the metal oxide switching layer 1 10 is composed of a metal (M), such as but not limited to, hafnium, tantalum or titanium. In the case of titanium or hafnium, or tantalum with an oxidation state +4, the metal oxide switching layer 110 has a chemical composition, MOx, where O is oxygen and X is or is substantially close to 2. In the case of tantalum with an oxidation state +5, the metal oxide switching layer 1 10 has a chemical composition, IVhOx, where O is oxygen and X is or is substantially close to 5. In an

embodiment, the metal oxide switching layer 110 has a thickness approximately in the range of 1 -5 nm.

In an embodiment, subsequent to formation of a metal oxide switching layer, the oxygen exchange layer 108, includes an upper most portion that is oxidized. That is, a partially oxidized portion of the oxygen exchange layer 108 ultimately becomes part of a switching layer for an RRAM cell. In one embodiment, the partially oxidized portion of the oxygen exchange layer is indistinguishable from the metal oxide switching layer 110. In another embodiment, a seam is present at an interface of the partially oxidized portion of the oxygen exchange layer and the metal oxide switching layer 110. In an embodiment, the thickness of the oxygen exchange layer 108 is at least twice the thickness of the metal oxide switching layer 1 10. In another embodiment, the thickness of the oxygen exchange layer 108 is at least twice the thickness of the metal oxide switching layer 108.

In an embodiment, the dielectric hardmask layer 112 is composed of a material such as but no limited to silicon nitride, carbon doped silicon nitride or silicon carbide. In an embodiment, the dielectric hardmask layer 112 has a thickness in the range of 10-50nm. In an embodiment, the dielectric hardmask is a material that can function as etch stop.

The dielectric spacer 116 is disposed adjacent and on sidewalls of the RRAM device 100 and on the first dielectric layer 102. The dielectric spacer 1 16 extends from the uppermost surface of the first dielectric layer 102 to an upper most surface of the first hardmask layer 112 and may be any suitable dielectric material such as but not limited to carbon doped silicon nitride or silicon nitride. In an embodiment, the dielectric material of the dielectric spacer 116 is a non- oxygen-containing material. In an embodiment, the dielectric spacer 116 has a thickness in the range of 20-5 Onm.

The second dielectric layer 1 18 is disposed on the first dielectric layer 102 and laterally adjacent to the dielectric spacer 116. An uppermost surface of the second dielectric layer 1 18 is coplanar or substantially coplanar with an uppermost surface of the dielectric spacer 1 16 and the uppermost surface of the top electrode 122. In an embodiment, the second dielectric layer may be any suitable dielectric material such as but not limited to carbon doped silicon nitride or silicon nitride, silicon oxide or carbon doped oxide.

In an embodiment, the third dielectric layer 120 is composed of the same material as the second dielectric layer. In an embodiment, the third dielectric layer 120 and the second dielectric layer 118 are composed of a carbon doped silicon material. In one such embodiment, the third dielectric layer 120 has a lower carbon concentration than the second dielectric layer 1 18. In an embodiment, the third dielectric layer 120 has a carbon concentration of

approximately 1-3% less carbon than the second dielectric layer 118. In an embodiment, the third dielectric layer 120 and the second dielectric layer 118 both have a carbon concentration approximately in the range of 5-15%, however, the third dielectric layer 120 has a lower carbon concentration than the second dielectric layer 118. In another embodiment, the third dielectric layer 120 and the second dielectric layer 118 both have a same carbon concentration.

The top electrode 122 is disposed in the opening 130 disposed in the second dielectric layer 1 18 and first dielectric hardmask layer 112. The opening has a sidewall angle in the range of 40-60 degrees. In an embodiment, the top electrode 122 has a portion that is directly in contact with the metal oxide switching layer 1 10 and portions that are in contact with sidewalls of the first dielectric hardmask layer 1 12 and the third dielectric layer 120. In an embodiment, the top electrode 122 is composed of a material such as, but not limited to, Pt, W, Pd and Ir. In an embodiment, the bottom electrode 106 and the top electrode 122 are composed of the same material. In an embodiment, the top electrode 122 has a thickness approximately in the range of 10 to 50 nm. In an embodiment, the top electrode 122 has a width ranging from 10-50nm. In another embodiment, the top electrode 122 extends laterally beyond the edge of the metal oxide switching layer 110. In an embodiment, the composition and thickness of the top electrode 122 are tuned to meet specific device attributes such as series resistance, programming switching voltage and current. In an embodiment, a requirement to subsequently polish top electrode 122 limits thickness to less than l OOnm.

In an embodiment, the top electrode contact layer 124 is composed of a material such as, but not limited to, Pt, W, Pd, Ir, TiN, W and TaN. In an embodiment, the top electrode completely fills the opening 130. In an embodiment the top electrode contact layer 124 and the top electrode 122 are the same metal.

Figure IB illustrates a plan view of an array of RRAM cells of the type illustrated in Figure 1A, in accordance with an embodiment of the present invention. In an embodiment, an RRAM array may include 10 ³ — 10 ^s RRAM cells. In an embodiment, electrical contact is made to the top electrode 122 and top electrode contact layer 124 of each RRAM device 100 through subsequent formation of conductive interconnects.

Figure 2A illustrates a cross-sectional view of a resistive random access memory (RRAM) cell which includes an RRAM device 200 with a scaled top electrode 222 formed in an opening 230 in a dielectric hardmask layer 212 above a metal oxide switching layer 210, in accordance with an embodiment of the present invention. The RRAM cell includes an RRAM device 200 disposed on a conductive interconnect 104, such as a conductive line or via, disposed in a first dielectric layer 102.

The top electrode 222 is disposed in the opening 230 in the first dielectric hardmask layer 212. In an embodiment, the opening 230 has sloped sidewalls to provide a conical opening, as is depicted. In another embodiment, the opening 230 has vertical sidewalls. In yet another embodiment, the opening 230 has curved sidewalls. The top electrode 222 completely or almost completely fills the opening 230 in the dielectric hardmask layer 212. In one embodiment, the top electrode 222 has a width at the base of the opening approximately in the range of 5-10 nm. As such, in an embodiment, the portion of the top electrode 222 in contact with the metal oxide switching layer has a width approximately in the range of 5-10 nm. In an embodiment, the top electrode 222 is centered between the dielectric spacer 116. In another embodiment, the top electrode 222 is off-centered between the dielectric spacer 116.

In an embodiment, the width of the portion of the top electrode 222 in contact with the metal oxide switching layer 210 is narrower than the width of the portion of the bottom electrode 106 in contact with the oxygen exchange layer 108. In one such embodiment, the width of the portion of the top electrode 222 in contact with the metal oxide switching layer 210 is approximately 5-50% of the width of the portion of the bottom electrode 106 in contact with the oxygen exchange layer 108. In a specific such embodiment, the width of the portion of the top electrode 222 in contact with the metal oxide switching layer 210 is approximately 10-20% of the width of the portion of the bottom electrode 106 in contact with the oxygen exchange layer 108.

The top electrode contact layer 224 is formed in an opening 240 in a dielectric layer 220. The top electrode contact layer 224 completely or almost completely fills the opening 240. In an embodiment, not shown, some portions of top electrode contact layer 224 extend into voids in the opening 230. In other embodiments, voids exist at the interface between the top electrode contact layer 224 and the top electrode 222. In one such embodiment, voids have dimension approximately in the range of 1 -3 nanometers.

In an embodiment, the opening 240 has sloped sidewalls, and the top electrode contact layer 224 is conformal with the sidewalls of the opening 240, as is depicted. In an embodiment the width, WTO, of the top of the opening 240 in the dielectric layer 220 is greater than the width, WBO, of the base of the opening 240. In an embodiment, the width, WBO, of the base of the opening 240 is wider than the width of the uppermost surface of the top electrode layer 222, as is depicted in Figure 2A. In an embodiment, the top electrode 222 is centered with the top electrode contact layer 224, as is depicted in Figure 2A. In another embodiment, the top electrode 222 is off-centered with the top electrode contact layer 224.

Figure 2B illustrates a partial cross-sectional view of the array of RRAM cells of the type illustrated in Figure 2A, in accordance with an embodiment of the present invention. In an embodiment, an array of RRAM cells includes 10 ³ — 10 ^s RRAM cells. In an embodiment, contact is made to the top electrode contact layer 224 of each RRAM device 200, subsequently through formation of interconnects. In contrast to the RRAM devices in the array illustrated in Figure IB, plurality of RRAM devices 200 depicted in the array in Figure 2B expose an uppermost surface of the top contact layer 224. Top electrode 122 and the top contact layer 124 are exposed in the array depicted in Figure IB.

Figures 3A-30 illustrate cross-sectional views representing various operations in a method of fabricating an RRAM device, in accordance with an embodiment of the present invention.

Figure 3A illustrates a cross-sectional view of a bottom electrode formed above a conductive interconnect, surrounded by a first dielectric layer 302 formed above a substrate 301. In an embodiment, one or more dielectric layers are included. Dielectric layer 302 may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (SiC ), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. The dielectric layer 302 may include pores or air gaps to further reduce their dielectric constant. In an embodiment, the total thickness of dielectric layer 302 may be in the range of 2000A - 3000A. The conductive interconnect 304 may be fabricated using dual damascene processing or subtractive etching. The dielectric layer 302 has an uppermost surface substantially co-planar with an uppermost surface of the conductive interconnect 304.

Figure 3B illustrates the structure of Figure 3A following the formation of a material layer stack 300 on the conductive interconnect and the first dielectric layer.

In an embodiment, the bottom electrode 306 is a material having a composition and a thickness such as described above in association with the bottom electrode 106. In an embodiment, the bottom electrode layer 306 is formed using a PVD or an ALD process. In an embodiment the bottom electrode layer 306 includes a material deposited by a physical vapor deposition (PVD) process. In one embodiment, the bottom electrode layer 306 is deposited by PVD and is composed of a material such as, but not limited to, TiN, TaN, W or Ru. In an embodiment, the bottom electrode layer 306 is deposited by PVD to a thickness approximately in the range of 30 nm to lOOnm. The process of depositing the bottom electrode layer 306 using PVD may include an in-situ sputter cleans to first remove any oxide residue from the uppermost surface of the conductive interconnect 304. For example, a gas containing Ar may be used to energetically bombard the surface of the conductive interconnect 304 to remove any native oxide. In an embodiment, the bottom electrode layer 306 is formed by a PVD process and is subsequently polished to achieve a surface roughness of 1 nm or less. Reducing surface roughness using a polishing process may offer advantages during cycling of an RRAM device as it may serve to reduce abrupt filament nucleation and hence lessen variation in cycling voltage in a large device array.

In another embodiment, the bottom electrode layer 306 is formed using an atomic layer deposition (ALD) process. The ALD process may offers advantages such as greater film thickness uniformity (~1 %) compared to a PVD process (-5%), but may have a slower deposition rate, e.g., a deposition rate of 0.5 nm - 2nm/min. In one embodiment, a planarization process is not needed subsequent to depositing using an ALD process. Reducing surface roughness using an ALD process may offer advantages during cycling of an RRAM device as it serves to reduce abrupt filament nucleation and hence lessen variation in cycling voltage in a large device array. In an embodiment, the bottom electrode layer 306 is deposited by ALD and is composed of a material such as, but not limited to, TiN, TaN, W and Ru.

Referring again to Figure 3B, an oxygen exchange layer 308 is formed on the uppermost surface of bottom electrode layer 306. In an embodiment, the oxygen exchange layer 308 includes a metal such as, but not limited to, hafnium, titanium or tantalum. In an embodiment, the oxygen exchange layer 308 has a thickness sufficiently thick to protect the underlying bottom electrode 306 during a subsequent metal oxide layer deposition process involving oxidation. In one embodiment, the oxygen exchange layer 308 is formed to a thickness approximately in the range of 5-20 nanometers. In one embodiment, the oxygen exchange layer 308 and the bottom electrode layer 306 are deposited sequentially in a same chamber or in a same tool without breaking vacuum. In one such embodiment, deposition of the oxygen exchange layer 308 involves the use of energetic ions that bombard the bottom electrode layer 306. In an embodiment, intermixing between the constituents of the bottom electrode layer 306 and the oxygen exchange layer 308 leads to formation of a conductive metal alloy interface (as illustrated by the dashed line 305 in Figure 3B). In one such embodiment, the alloy is composed of materials such as, but not limited to, titanium, nitrogen and hafnium. In an embodiment, the intermixing leads to an oxygen-free region.

Referring again to Figure 3B, in an embodiment, the metal oxide switching layer 310 is formed on an oxygen exchange layer 308. In an embodiment, the thickness of the metal oxide switching layer 310 has a thickness approximately in the range of 2-5nm. In an embodiment, the metal oxide switching layer 310 is formed using an ALD process. The ALD process may be characterized by a slow and a highly controlled metal oxide deposition rate. The ALD process may also be highly uniform (e.g., approximately O. lnm level variation). In another embodiment, the metal oxide switching layer 310 is formed using a PVD process. In contrast to the ALD process, in an embodiment an energetic PVD deposition process, may cause intermixing between the metal oxide switching layer 310 and the oxygen exchange layer 308. In an embodiment, intermixing leads to a thin transition region (indicated by the dashed line 309) between the metal oxide switching layer 310 and the oxygen exchange layer 308. In an embodiment, a switching layer for an RRAM device ultimately includes the thin transition region of the oxygen exchange layer 308 together with the metal oxide switching layer 310.

Figure 3C illustrates a resist pattern formed on a dual hardmask layer 313 composed of a first dielectric hardmask layer 312 formed on a second dielectric hardmask layer 314 formed on the material layer stack 300. In an embodiment, the first dielectric hardmask layer 312 is a material having a composition and a thickness such as described above in association with the dielectric hardmask layer 112. In an embodiment, the second dielectric hardmask layer 314 is a material having a composition similar to the dielectric hardmask layer 312.

In an embodiment, the first dielectric hardmask layer 312 and the second dielectric hardmask layer 314 are composed of a carbon doped silicon material. In one such embodiment, first dielectric hardmask layer 312 has a lower carbon concentration than the second dielectric hardmask layer 314. In an embodiment, the second dielectric hardmask layer 314 has a carbon concentration of approximately 1-2% more carbon than the first dielectric hardmask layer 312. In an embodiment, the first dielectric hardmask layer 312 and the second dielectric hardmask layer 314 both have a carbon concentration approximately in the range of 1-3%, however, the first dielectric hardmask layer 312 has a lower carbon concentration than the second dielectric hardmask layer 314. In another embodiment, the first dielectric hardmask layer 312 and the second dielectric hardmask layer 314 both have a same carbon concentration. In one embodiment, the first dielectric hardmask layer 312 has no carbon and the second dielectric hardmask layer 314 has 1 -3% carbon concentration. In an embodiment, the first dielectric hardmask layer 312 has a carbon concentration of 1 -3%, and the second dielectric hardmask layer 314 has no carbon.

In an embodiment, resist pattern 319 has a shape that ultimately defines a shape of an RRAM device fabricated from the material layer stack 300. In one embodiment, the resist partem 319 has rectangular shape or a circular shape. In one embodiment, the resist pattern 319 has a shortest width in the range of 20-100nm. Resist pattern 319 may include one or more materials such as an anti-reflective coating (ARC), gap-fill and planarizing material in addition to or in place of a photoresist material. In one embodiment, the resist pattern 319 is formed to a thickness sufficient to retain its profile during subsequent patterning of the dual hardmask layer 313 but not so thick as to prevent lithographic patterning into the smallest dimensions (e.g., critical dimensions) possible with photolithography processing.

Figure 3D illustrates the structure of Figure 3C following an etch process used to transfer the resist pattern 319 into the second dielectric hardmask layer 314 to form a second dielectric hardmask pattern, followed by removal of the resist partem. In an embodiment, an anisotropic plasma etch process is used to partem second dielectric hardmask layer 314 with selectivity to the resist pattern 319. In an embodiment, a selectivity of greater than 3 to 1 between photoresist material and second dielectric hardmask layer 314 is achieved. It is to be appreciated that chemical etchants utilized in the plasma etch process may depend on the dielectric material being etched, and may include one or more of CH _x F _y , C , Ar, N2 and CF4. Sidewall angles of the pattemed dual hardmask layer 313 may be tailored to vary from 85-90 degrees depending on the type of etch conditions employed. In an embodiment, the etch process will expose the underlying first dielectric hardmask layer 312. In an embodiment, the etch selectivity between the first dielectric hardmask layer 312 and the second dielectric hardmask layer 314 has a value approximately in the range of 0.5 to 0.8. In an embodiment, a portion of the second dielectric hardmask layer 314 is removed while etching the first dielectric hardmask layer 312.

Referring again to Figure 3D, in an embodiment, the resist pattern 319 is removed using an ash process. The ash process may include use of a gas containing O2, H2/N2, etc. It is to be appreciated that polymeric films, which may result from the interaction between a photoresist material and etch byproducts during memory device etch, may adhere to the sidewall portions of an etched RRAM material layer stack 300. If portions of such polymeric layers have metallic components, device performance may be significantly degraded. As such, in one embodiment, the resist pattern 319 is removed prior to etching the second dielectric hardmask layer 314.

Figure 3E illustrates the structure of Figure 3D following an etch process used to transfer the second dielectric hardmask pattern into the first dielectric hardmask layer 312 and the material layer stack 300 to form a dual hardmask layer 313 and a patterned material layer stack 300.

In one embodiment, etching of the second dielectric hardmask layer 314, metal oxide switching layer 310, oxygen exchange layer 308 and the bottom electrode layer 306 is performed in a single introduction in an etch tool to etch all layers of the material layer stack 300 in a single pass. However, different chemistries may be utilized in the etch recipes. In an embodiment, the dielectric hardmask layer 314 is etched using a reactive ion etch with chemistry including Ar, CF4. In an embodiment, a hafnium-based oxygen exchange layer 3 is etched using BC13, C12, and Ar. In an embodiment, where metal oxide switching layer 310 and the oxygen exchange layer 308 include a same metal, such as Hf, the etch may be carried out with BC13, C12, and Ar. In another embodiment, a Ta-based metal oxide switching layer 310 and a Ta-based oxygen exchange layer 308 is patterned using a mixture of CHF _X , Ar, Ch containing chemistry. In an embodiment, a TiN bottom electrode layer 306 is etched using a reactive ion etch with chemistry including Ar, CF4 and C12. In an embodiment, the metallic nature of the oxygen exchange layer and the bottom electrode leads to little to no notching in the oxygen exchange layer.

In an embodiment, as depicted in Figure 3E, the width of the bottom electrode 306 is larger than the width of the conductive interconnect 304. When the bottom electrode layer 306 is completely etched the underlying first dielectric layer 302 is exposed. Depending on the etch selectivity to the first dielectric layer, there may be a small but noticeable amount of recess 303 in the dielectric layer 302.

Figure 3F illustrates the structure of Figure 3E following the formation of a dielectric spacer layer 315 covering the dual hardmask layer 313, the patterned material layer stack 300 and the first dielectric layer 302. In an embodiment, deposition of the dielectric spacer layer 315 is performed immediately post RRAM device etch, prior to breaking vacuum in the same tool or chamber used for the etch process. Such a procedure, known in the art as in-situ deposition, may hermetically seal the device and potentially decrease oxidation of the perimeter of the sensitive metal oxide switching layer 310. In an embodiment, the dielectric spacer layer 315 is a material such as, but not limited to, silicon nitride, silicon carbide, carbon-doped silicon nitride, or any suitable non-oxygen containing material. In an embodiment, the dielectric spacer layer 315 has a thickness approximately in the range of 20-50nm. In another embodiment, the material layer stack 300 and the dual hardmask layer 313 have angled sidewalls between 80-90 degrees, and the dielectric spacer layer 315 is deposited to a thickness greater than 50nm.

Figure 3G illustrates the structure of Figure 3F following an anisotropic plasma etch of the dielectric spacer layer 315 to form a dielectric spacer 316. In an embodiment, a silicon nitride or carbon doped silicon nitride dielectric spacer layer 315 is reactive-ion etched utilizing a chemistry including Ar, O2, and a fluorocarbon such as but not limited to CHF3, CH2F2, or C4F8. In an embodiment, the resulting structure as depicted in Figure 3G has a vertical dielectric spacer structure that extends from the base of the first dielectric layer 302 to the top of the dual hardmask layer 313. In an embodiment, the dielectric spacer extends above the uppermost level of the top electrode 312 but below the uppermost portions of the dual hardmask layer 313. In an embodiment when the first dielectric layer 302 is exposed post formation of the bottom electrode layer 306, there may be a small but noticeable amount of recess 323 in the dielectric layer 302 depending on the etch selectivity to the first dielectric layer 302 (indicated by the dotted line in Figure 3G).

Figure 3H illustrates the structure of Figure 3G following formation of a second dielectric layer 318 covering the dual hardmask layer 313, the patterned material layer stack 300, the dielectric spacer 316, and the first dielectric layer 302. In an embodiment, the total thickness of second dielectric layer 318 is in the range of 250-350 nm. Suitable materials for the second dielectric layer 318 may be the same as those described in association with the second dielectric layer 118. In an embodiment, a total thickness of the second dielectric layer 318 is

approximately 2 to 2.5 times the combined height of the material layer stack 300 and the dual hardmask layer 313.

Figure 31 illustrates the structure of Figure 3H following planarization to form coplanar surfaces of the second dielectric layer 318, the dielectric spacer 316, and the first dielectric hardmask layer 312. In an embodiment, a chemical mechanical polishing (CMP) process is used for the planarizing. The resulting structure may include uppermost portions of the second dielectric layer 318, the dielectric spacer 316 and the first dielectric hardmask layer 312 that are co-planar with one another.

Figure 3 J illustrates the structure of Figure 31 following formation of a third dielectric layer

320 on the coplanar surfaces of the second dielectric layer 318, the dielectric spacer 316, and the first dielectric hardmask layer 312. Suitable materials for the third dielectric layer 320 may be the same as those described in association with the third dielectric layer 120. In an embodiment, a total thickness of the third dielectric layer 320 is approximately in the range of 50-150nm.

Figure 3K illustrates the structure of Figure 3 J following patterning of a photoresist material to form a mask 326 to define a via location. Suitable materials for the mask 326 may be the same as those described in association with the mask 322.

Figure 3L illustrates the structure of Figure 3K following an etch process to create an upper portion 321 A of a via 321 in the third dielectric layer 320, followed by mask removal. In an embodiment, a silicon oxide or carbon doped silicon oxide dielectric layer is reactive-ion etched utilizing a chemistry including Ar, O2, CO and a fluorocarbon such as but not limited to CHF3, CH2F2, or C4F8. In an embodiment, the resulting upper portion 321 A of a via 321 has sloped sidewalls as is depicted in Figure 3L. In an embodiment, the etch selectivity between the third dielectric layer 320 and the first dielectric hardmask layer 312 is approximately in the range of 10-14. In other words the first dielectric hardmask layer 312 acts as an excellent etch stop for etching the third dielectric layer 320.

Figure 3M illustrates the structure of Figure 3L following an etch process to form a lower portion 321B of the via 321 in the first dielectric hardmask layer 312, the via 321 exposing the metal oxide switching layer 310. In an embodiment, a silicon oxide or carbon doped silicon oxide dielectric layer is reactive-ion etched utilizing a chemistry including Ar, and a

fluorocarbon such as but not limited to CHF3, CH2F2, or C4F8, CF4. In an embodiment, the etch is composed of multiple processes: a first timed process to remove the bulk of the first dielectric hardmask layer 312, a second end pointed process to gently land on the metal oxide switching layer followed by a third least aggressive cleanup process. In an embodiment, O2 containing chemistry is utilized to etch the bulk of the dielectric hardmask layer 312, the clean-up process is however devoid of O2. In an embodiment, the sidewall of the upper portion 321A of via 321 and the lower portion 321B of via 321 is collinear as depicted in Figure 3M. In another embodiment, the lower portion 321B of via 321 is more vertical compared to the sidewall profile of the upper portion 321 A of via 321 in the third dielectric layer 320. In yet another embodiment, the lower portion 321B of via 321 is more sloped compared to the sidewall of the upper portion 321 A of via 321 in the third dielectric layer 320. In an embodiment, a wet etch is employed to clean the remaining first dielectric hardmask layer 312 after a plasma etch.

Figure 3N illustrates the structure of Figure 3M following formation of a top electrode layer 322 and a top electrode fill layer 324 in the via 321. The top electrode layer 322 is formed in the via opening 321 , on the metal oxide switching layer 310, on the sidewalls of the first dielectric hardmask layer 312, the sidewalls of the third dielectric layer 320 and on the uppermost surface of the third dielectric layer 320. In embodiment, not shown, a thin layer of additional metal oxide material is deposited on the exposed metal oxide switching layer 310 prior to deposition of the top electrode layer 322.

In an embodiment, the top electrode layer 322 is a material having a composition and a thickness such as described above in association with the top electrode 122. In an embodiment, the top electrode layer 322 is formed using a physical vapor deposition (PVD) or an ALD process. In an embodiment the top electrode layer 322 includes a material deposited by a physical vapor deposition (PVD) process. In an embodiment, the top electrode layer 322 is composed of a material such as, but not limited to, Pt, W, Pd and Ir. In one embodiment, the top electrode layer 322 is composed of a material such as, but not limited to, TiN, TaN or Ru.

Materials processed by a PVD technique are characterized by a less conformal deposition profile. In an embodiment, the thickness of top electrode layer 322 on the uppermost surface of metal oxide switching layer 310 is greater than the thickness of the top electrode layer 322 on the sidewalls of the via 321. In an embodiment, a seam may form at an interface between the sidewalls of the lower portion 321B of via 321 and the metal oxide switching layer 310.

In another embodiment, the top electrode layer 322 is formed using an atomic layer deposition (ALD) process. The ALD process may offers advantages such as greater film thickness uniformity (~1 %) compared to a PVD process (-5%), but may have a slower deposition rate, e.g., a deposition rate of 0.5 nm - 2nm/min. ALD processing may also be less aggressive compared to an energetic deposition of the PVD process leading to virtually no damage of the metal oxide switching layer. In an embodiment, the top electrode layer 322 deposited by an ALD process is composed of a material such as, but not limited to, Pt, W, Pd and Ir. In another embodiment, the top electrode layer 322 deposited by an ALD process is composed of a material such as, but not limited to, TiN, TaN or Ru.

In an embodiment, the top electrode fill layer 322 is also formed by a PVD deposition process and is composed of a material such as, but not limited to, TiN, TaN or W. In an embodiment, as depicted in Figure 3N, the thickness of the top electrode fill layer 322 is chosen, so as to completely fill the via 321 and extend 50nm-100nm above the level of the uppermost surface of the third dielectric layer 320.

Figure 30 illustrates the structure of Figure 3N following planarization to form a top electrode 327 and a top electrode contact 325. In an embodiment, a chemical mechanical polishing (CMP) process is used for the planarizing. In an embodiment depicted in Figure 30, the resulting structure includes uppermost surfaces of the third dielectric layer 320, the top electrode 327 and the top electrode contact 325 that are coplanar or substantially coplanar with one another.

Figures 4A-4K illustrate cross-sectional views representing various operations in another method of fabricating an RRAM device having a bottom oxygen exchange layer, in accordance with another embodiment of the present invention.

Figure 4A illustrates the structure of Figure 3H following planarization of the second dielectric layer to form coplanar surfaces of the second dielectric layer 418, the dielectric spacer 416, and the second dielectric hardmask layer 414. In an embodiment, a chemical mechanical polishing (CMP) process is used for the planarizing. The resulting structure may include uppermost portions of the second dielectric layer 418, the dielectric spacer 416 and the second dielectric hardmask layer 414 that are co-planar with one another.

Figure 4B illustrates the structure of Figure 4A following patterning of a photoresist material to form a mask 417 to define a first via location. Suitable materials for the mask 417 may be the same as those described in association with the mask 322 in Figure 3C.

Figure 4C illustrates the structure of Figure 4B following an etch process to create an upper portion 419A of a first via 419 in the second dielectric hardmask layer 414, followed by a mask removal. Etch processes may be comparable to those described in association with the formation of the lower portion of via 321b. In an embodiment, the mask 417 is removed using an ash process. In an embodiment, the ash process includes use of a gas containing C , H2/N2, etc. In an embodiment, mask 417 is removed before exposure of the uppermost surface of metal oxide switching layer 410 in order to avoid deliberate O2 bombardment of the metal oxide switching layer 410.

Figure 4D illustrates the structure of Figure 4C following an etch process to form a lower portion 419B of the first via 419 in the first dielectric hardmask layer 412, the first via 419 exposing the metal oxide switching layer 410. Etch processes may be comparable to those described in association with the formation of the lower portion of via 321B. In an embodiment, completing the etch with a wet chemical clean-up process is desirable to protect the uppermost surface of the metal oxide switching layer 410. In an embodiment, via size 419 is approximately in the range of 10-30nm at the top of the opening 419. In one such embodiment, the taper in the sidewall profile of the second dielectric hardmask layer 414 and the first dielectric hardmask layer 412 forms an opening at the surface of the metal oxide switching layer 410 that is approximately in the range of 5-10nm. In an embodiment, a hot phosphoric acid heated to 155 degrees Celsius is used to remove any surface remaining nitride on the surface of the metal oxide switching layer 410.

Figure 4E illustrates the structure of Figure 4D following formation of a top electrode layer 422 in the first via 419 and on the metal oxide switching layer 410. Techniques and materials utilized in the formation of the top electrode layer 322 described in association with Figure 3N, may be applicable to forming the top electrode layer 422 as depicted in Figure 4E. In an embodiment, the relatively small opening in via 419 utilizes an ALD process to completely or almost completely fill the via 419

Figure 4F illustrates the structure of Figure 4E following a planarization process to form a top electrode 423. In an embodiment, a chemical mechanical polishing (CMP) process is used for the planarizing. In an embodiment depicted in Figure 4F, the resulting structure includes uppermost surfaces of the second dielectric layer 418, dielectric spacer 416, the first dielectric hardmask layer 412 and top electrode 423 that are co-planar or substantially co-planar with one another. In an embodiment some remnants of the second dielectric hardmask layer 414 may remain on the uppermost surface of the first dielectric hardmask layer 412.

Figure 4G illustrates the structure of Figure 4F following formation of a third dielectric layer 420 on the coplanar surfaces of the second dielectric layer 418, the dielectric spacer 416, the first dielectric hardmask layer 412 and the top electrode 423. Techniques, materials and material thickness utilized in formation of the third dielectric layer 320 described in association with Figure 3J, may be applicable to forming the third dielectric layer 420, as depicted in Figure 4G.

Figure 4H illustrates the structure of Figure 4G following patterning of a photoresist material to form a mask 421 to define a second via location. Suitable materials for the mask 421 may be the same as those described in association with the mask 417.

Figure 41 illustrates the structure of Figure 4H following an etch process to create a second via 426 in the third dielectric layer 420, followed by mask removal. In an embodiment, a silicon oxide or carbon doped silicon oxide based third dielectric layer 420 is reactive-ion etched utilizing a chemistry including Ar, C , CO and a fluorocarbon such as but not limited to CHF3, CH2F2, or C4F8. In an embodiment, the resulting second via 426 has a sloped sidewall profile as is depicted in Figure 4J. In an embodiment, the etch selectivity between the third dielectric layer 320 and the first dielectric hardmask layer is approximately in the range of 10-14. In an embodiment, the etch selectivity between the third dielectric layer 420 and the top electrode layer 422 is approximately in the range 20-40. In an embodiment, differences in etch selectivity between two material surfaces that are simultaneously exposed during an etch can lead to non- coplanar surfaces. In one such embodiment, not shown in the Figure 41, the upper most surface of the first dielectric hardmask layer 412 is below the upper most surface of the top electrode layer 422.

Figure 4J illustrates the structure of Figure 41 following formation of a top electrode contact layer 425 in the second via 426. Techniques, materials and material thickness utilized in formation of the top electrode fill layer 324 described in association with Figure 3N may be applicable to forming the top electrode fill layer 424.

Figure 4K illustrates the structure of Figure 4J following a planarization process to form a top electrode contact. In an embodiment, a chemical mechanical polishing (CMP) process is used for the planarizing. In an embodiment depicted in Figure 30, the resulting structure includes uppermost surfaces of the third dielectric layer 420 and the top electrode contact 425 that are coplanar or substantially coplanar with one another.

Figure 5A illustrates a cross-sectional view representing a patterned material layer stack 300, where the width of a bottom electrode 306 is smaller than the width of a conducive interconnect 304, in accordance with an embodiment of the present invention. In one such embodiment, etching of the bottom electrode layer 306 exposes the uppermost surface of the conductive interconnect 304. In the case that the exposed uppermost surface of the conductive interconnect 304 is an exposed copper surface, the etch may undesirably create recesses 510 and sputter copper particles 520 across the surface of the substrate.

Accordingly, when the bottom electrode 306 is smaller than the conductive interconnect

304, it may be desirable to utilize an interconnect having a capping layer. For example, Figure 5B illustrates a cross-sectional view representing an RRAM device where the width of a bottom electrode is smaller than the width of a conductive interconnect 500, and the conductive interconnect 500 includes a capping layer, in accordance with an embodiment of the present invention. The conductive interconnect 500 includes capping layer 502 over a conductive fill material 504 and between a barrier layer 506. The capping layer 502 is composed of a material different than the material of the fill material 504. In one embodiment, the conductive interconnect 500 is fabricated by recessing a fill material of the conductive interconnect 304. A conductive capping material is then formed in the recess and on the uppermost surface of the first dielectric layer 302 and planarized to provide the capping layer 502. In one embodiment, the capping layer 402 is composed of a different material than the bottom electrode 306 such that the bottom electrode 306 may be selectively etched such that the capping layer 502 is not recessed during the etch. In another embodiment, the capping layer 502 is composed of the same material as the bottom electrode 306 and is recessed to form recesses 508 during the formation of the bottom electrode 306. Ideally, in one such embodiment, the capping layer 502 is sufficiently thick such that the recesses 508 do not expose an uppermost copper surface of conductive fill material 504.

Figures 6A-6D illustrate cross-sectional views representing various operations in a method of fabricating a bottom electrode 606 integrated on a conductive interconnect 604, in accordance with an embodiment of the present invention.

Figure 6A illustrates a conductive interconnect 604 formed in a first dielectric layer 602 above a substrate 600. Conductive interconnect 604 may be fabricated in a manner similar to the conductive interconnect 304 described in association with Figure 3A.

Figure 6B illustrates the structure of Figure 6A following recessing of the conductive interconnect 604 to a level below an uppermost surface of the first dielectric layer 602 to form a recess 603.

In an embodiment, the recessing is performed by a combination of a dry and a wet etch process. In an embodiment, the recess 603 has a depth approximately in the range of 30nm- 60nm. The recessing process may or may not recess all components of the conductive interconnect 604. For example, in an embodiment, a conductive fill material is recessed and a diffusion barrier layer is not recessed and extends above the recessed conductive fill material. In another embodiment, both a conductive fill material and a diffusion barrier layer are recessed.

Figure 6C illustrates the structure of Figure 6B following formation of a bottom electrode material 605 on the recessed conductive interconnect 604 and on the uppermost surface of the first dielectric layer 602. Exemplary materials and deposition processes for the bottom electrode material 605 are as described above in association with bottom electrode 306.

Figure 6D illustrates the structure of Figure 6C following planarization of the bottom electrode material 605 to form a bottom electrode 606. In an embodiment, the bottom electrode material 605 is planarized using a CMP process. In one such embodiment, the CMP process provides the bottom electrode 606 with an uppermost surface co-planar with the uppermost surface of the first dielectric layer 602.

Figure 7 A illustrates a cross-sectional view representing an RRAM device 700 where the width of a bottom electrode 606 and the width of the top electrode 122 may each be

independently controlled with respect the width of the oxygen exchange layer, in accordance with an embodiment of the present invention. The oxygen exchange layer 108 is formed on the uppermost surface of a bottom electrode 606 and on the first dielectric layer 602. In an embodiment, the fabrication process of structure 710 is carried out in a manner similar to the methods described in association with Figures 3C-30. In an embodiment, the first dielectric layer 602 is a non-oxygen containing material such as but not limited to silicon nitride and carbon doped silicon nitride.

In an embodiment, the width of the oxygen exchange layer 108 and the metal oxide switching layer 1 10 is greater than the width of the top electrode 122 where the top electrode 122 is in contact with the metal oxide switching layer 1 10. The width of the oxygen exchange layer 108 and the metal oxide switching layer 110 is also greater than the width of the bottom electrode 106. In one such embodiment, filament formation for the RRAM device is centralized, away from the edges of the metal oxide switching layer 110. In an embodiment, the arrangement provides an effectively smaller RRAM device without a need for scaling the width of the metal oxide switching layer 110 and the oxygen exchange layer 108. Figure 7B illustrates a cross-sectional view representing an RRAM device 710 where the width of a bottom electrode 606 and the width of the top electrode 222 may each be

independently controlled with respect the width of the oxygen exchange layer, in accordance with an embodiment of the present invention. The oxygen exchange layer 108 is formed on the uppermost surface of a bottom electrode 606 and on the first dielectric layer 602. In an embodiment, the fabrication process of structure 710 is carried out in a manner similar to the methods described in association with Figures 4A-4K. In an embodiment, the first dielectric layer 602 is a non-oxygen containing material such as but not limited to silicon nitride and carbon doped silicon nitride.

In an embodiment, the width of the oxygen exchange layer 108 and the metal oxide switching layer 110 is greater than the width of the top electrode 122 where the top electrode 122 is in contact with the metal oxide switching layer 110. The width of the oxygen exchange layer 108 and the metal oxide switching layer 110 is also greater than the width of the bottom electrode 106. In one such embodiment, filament formation for the RRAM device is centralized, away from the edges of the metal oxide switching layer 110. In an embodiment, the arrangement provides an effectively smaller RRAM device without a need for scaling the width of the metal oxide switching layer 110 and the oxygen exchange layer 108.

In an embodiment after completion of an RRAM device fabrication process RRAM devices, presented in connection with Figure 1 A and 2 A, are connected to form a two terminal device such as is illustrated in Figure 12. RRAM devices such as shown in Figure 1A and Figure 2A undergo a high temperature anneal process at the end of the fabrication process. In an embodiment, anneal temperatures reach 400°C and last for a time period of 60 minutes.

Annealing is a thermal phenomenon that serves to drive the O ^2" from the metal oxide switching layer thus creating Oxygen vacancies, V ₀ in this layer. The O ^2" from the metal oxide switching layer diffuses to the oxygen exchange layer below. The effect serves to increase the V ₀ density in the metal oxide switching layer 110 layer priming it for creation of one more conductive filaments.

Figures 9A illustrates an I-V plot, demonstrating concepts involved with filament formation and voltage cycling (reading and writing) in an RRAM device, such as is depicted in Figure 9B, in accordance with embodiments of the present invention. The initial operation of an RRAM device begins by gradually applying a voltage that is increasing in magnitude, between the top electrode 122 and the bottom electrode 106. In an "intentional" one-time breakdown process, known as forming, oxygen vacancies, V ₀ , are pumped in from the oxygen exchange layer 108 into the metal oxide switching layer 110 to augment the vacancies created during the anneal process described above. This leads to a formation of a "conductive V ₀ filament" in the metal oxide switching layer 110 (point B), also shown in the RRAM device in Figure 9B. With a conductive filament bridging the top electrode 122 and the bottom electrode 106, the RRAM device is said to be almost immediately conductive and thus, in a low resistance state (point C). By sweeping the voltage between the top electrode 122 and bottom electrode 106 in a reversed direction (point C to D and then to F), causing a reversal in an electric field direction, the oxygen vacancies (technically positively charged ions) are now directed towards the oxygen exchange layer 108 leading to a dissolution of the conductive filament in the metal oxide switching layer 110. Filament dissolution takes place at some critical voltage (point F), termed VReset, and the device returns to a high resistance state (point G). It is to be appreciated that the high resistance level of the RRAM device, point G, is different and lower in magnitude compared to the resistance level of the device before the onset of the forming process. By once again "sweeping" the voltage in the opposite direction, traversing from point G to H and then to point I in the I-V plot, the momentarily dissolved filament begins to manifests again under the action of vacancy migration. At some critical voltage, Vset, the filament completely bridges the top electrode 122 and the bottom electrode 106 and the device is once again said to be in a conductive mode or a low resistance state, point J. The cycling of an RRAM device in this manner, where the resistance levels remain unchanged about the 0 voltage point, leads to the effect of non-volatile memory. In other words, even with the voltage turned off, the resistance of the RRAM device is maintained to within a certain range. In an embodiment, when an RRAM device undergoes a read operation where a voltage, less than the switching voltage (Vset or VReset) is applied, the device exhibits a numerical resistance value approximately similar in value before the voltage is turned off. It is to be appreciated that the values Vset and VReset, generally refer to a portion of a voltage that is applied to a transistor in series with the RRAM element. The RRAM device coupled with a transistor in this manner is given the term embedded memory.

Figure 10 illustrates a RRAM device 1004, formed on a conductive interconnect 1002 disposed in a via formed in a dielectric 1007 and integrated with a logic transistor 1030 disposed above a substrate 1005. RRAM device 1004 includes a bottom electrode 1006, an oxygen exchange layer 1008, a metal oxide switching layer 1010 and a top electrode 1014. In one such embodiment, the RRAM device 1004 is a device such as described in association with Figure 1A. In one such embodiment, the RRAM device is disposed directly on a conductive interconnect coupled to a contact structure 1012 connected to the drain 1020 of the transistor. In an embodiment, RRAM device 1004 is connected to an upper interconnect 1016. In other embodiments, the RRAM device 1004 is a device such as described in association with Figure 1A.

In an embodiment, the underlying semiconductor substrate 1005 represents a general workpiece object used to manufacture integrated circuits. The semiconductor substrate often includes a wafer or other piece of silicon or another semiconductor material. Suitable semiconductor substrates include, but are not limited to, single crystal silicon, poly crystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other

semiconductor materials. The substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates.

In an embodiment, transistors associated with substrate 1005 are metal-oxide- semiconductor field-effect transistors (MOSFET or simply MOS transistors), fabricated on the substrate 1005. In various implementations of the invention, the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include Fin- FET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all- around gate transistors such as nanoribbon and nanowire transistors.

In an embodiment, each MOS transistor 1030 of substrate 1005 includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (S1O2) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.

The gate electrode layer of each MOS transistor of substrate 1005 is formed on the gate dielectric layer and may consist of at least one P-type work function metal or N-type work function metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a conductive fill layer.

For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a work function that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a work function that is between about 3.9 eV and about 4.2 eV.

In some implementations, the gate electrode may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the invention, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

In some implementations of the invention, a pair of sidewall spacers 1040 may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process operations. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

As is well known in the art, source 1050 and drain 1020 regions are formed within the substrate adjacent to the gate stack of each MOS transistor. The source and drain regions are generally formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions. In some implementations, the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxial deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source and drain regions.

To provide further context, integrating memory directly onto a microprocessor chip would be advantageous since it enables higher operation speeds compared to having physically separate logic and memory chips. Unfortunately, traditional charge-based memory technologies such as DRAM and NAND Flash are now facing severe scalability issues related to increasingly precise charge placement and sensing requirements. As such, embedding charge-based memory directly onto a high performance logic chip is not very attractive for future technology nodes. However, a memory technology that does have the potential to scale to much smaller geometries compared to traditional charge-based memories is resistive random access memory (RRAM), since it relies on resistivity rather than charge as the information carrier. However, in order to exploit the potential benefits of a high performance logic chip with embedded RRAM memory, an appropriate integrated logic plus RRAM structure and fabrication method is needed.

Embodiments of the present invention include such structures and fabrication processes.

Relating to one or more embodiments described herein, it is to be appreciated that traditional DRAM memory is facing severe scaling issues and, so, other types of memory devices are being actively explored in the electronics industry. One future contender is RRAM devices. Embodiments described herein include a fabrication method for embedding RRAM bit cell arrays into a logic process technology. Embodiments described may be advantageous for processing schemes involving the fabrication of logic processors with embedded memory arrays.

In an aspect, an RRAM element may be included in an integrated circuit in regions typically referred to as back end or back end of line (BEOL) layers of the integrated circuit. As examples, Figures 11 A-l IE illustrate schematic views of several options for positioning an RRAM element in an integrated circuit, in accordance with embodiments of the present invention.

Referring to all Figures 11 A-l IE, in each case, a memory region 1100 and a logic region 1102 of an integrated circuit are depicted schematically. Each memory region 1100 includes a select transistor 1104 and overlying alternating metal lines and vias. Each logic region includes a plurality of transistors 1106 and overlying alternating metal lines and vias which can be used to connect the plurality of transistors 1106 into functional circuits, as is well known in the art.

Referring to Figure 11 A, an RRAM device 1120 is disposed between a lower conductive via 1122 and an upper conductive line 1124. In one embodiment, the lower conductive via 1122 is in electrical contact with a bottom electrode of the RRAM device 1120, and the upper conductive line 1124 is in electrical contact with a top electrode of the RRAM device 1120. In a specific embodiment, the lower conductive via 1122 is in direct contact with a bottom electrode of the RRAM device 1120, and the upper conductive line 1124 is in direct contact with a top electrode of the RRAM device 1120.

Referring to Figure 11B, an RRAM device 1130 is disposed between a lower conductive line 1132 and an upper conductive via 1134. In one embodiment, the lower conductive line 1132 is in electrical contact with a bottom electrode of the RRAM device 1130, and the upper conductive via 1134 is in electrical contact with a top electrode of the RRAM device 1130. In a specific embodiment, the lower conductive line 1132 is in direct contact with a bottom electrode of the RRAM device 1130, and the upper conductive via 1134 is in direct contact with a top electrode of the RRAM device 1130.

Referring to Figure 11C, an RRAM device 1140 is disposed between a lower conductive line 1142 and an upper conductive line 1144 without an intervening conductive via. In one embodiment, the lower conductive line 1142 is in electrical contact with a bottom electrode of the RRAM device 1140, and the upper conductive line 1144 is in electrical contact with a top electrode of the RRAM device 1140. In a specific embodiment, the lower conductive line 1142 is in direct contact with a bottom electrode of the RRAM device 1140, and the upper conductive line 1144 is in direct contact with a top electrode of the RRAM device 1140.

Referring to Figure 11D, an RRAM device 1150 is disposed between a lower conductive via 1152 and an upper conductive via 1154 without an intervening conductive line. In one embodiment, the lower conductive via 1152 is in electrical contact with a bottom electrode of the RRAM device 1150, and the upper conductive via 1154 is in electrical contact with a top electrode of the RRAM device 1150. In a specific embodiment, the lower conductive via 1152 is in direct contact with a bottom electrode of the RRAM device 1150, and the upper conductive via 1154 is in direct contact with a top electrode of the RRAM device 1150.

Referring to Figure 1 IE, an RRAM device 1160 is disposed between a lower conductive line 1162 and an upper conductive via 1164 in place of an intervening conductive line and conductive via pairing. In one embodiment, the lower conductive line 1162 is in electrical contact with a bottom electrode of the RRAM device 1160, and the upper conductive via 1164 is in electrical contact with a top electrode of the RRAM device 1160. In a specific embodiment, the lower conductive line 1162 is in direct contact with a bottom electrode of the RRAM device 1160, and the upper conductive via 1164 is in direct contact with a top electrode of the RRAM device 1160.

Figure 12 illustrates a schematic of a memory bit cell, which includes a metal-conductive oxide-metal RRAM device, in accordance with embodiments of the present invention.

Referring to Figure 12, the RRAM memory device 1210 may include a bottom electrode 1212 with an extended metal oxide switching layer 1213 formed on the bottom electrode 1212. An oxygen exchange layer 1214 is formed on the extended metal oxide switching layer 1213. A top electrode 1216 is formed on the oxygen exchange layer 1214. The top electrode 1216 may be electrically connected to a bit line 1232. The bottom electrode 1212 may be coupled with a transistor 1234. The transistor 1234 may be coupled with a wordline 1236 and a source line 1238 in a manner that will be understood to those skilled in the art. The RRAM cell 1200 may further include additional read and write circuitry (not shown), a sense amplifier (not shown), a bit line reference (not shown), and the like, as will be understood by those skilled in the art, for the operation of the RRAM cell 1200. It is to be appreciated that a plurality of the RRAM cells 1200 may be operably connected to one another to form a memory array, wherein the memory array can be incorporated into a non-volatile memory region of a substrate in common with a logic region.

Figure 13 illustrates a block diagram of an electronic system 1300, in accordance with an embodiment of the present invention. The electronic system 1300 can correspond to, for example, a portable system, a computer system, a process control system, or any other system that utilizes a processor and an associated memory. The electronic system 1300 may include a microprocessor 1302 (having a processor 1304 and control unit 1306), a memory device 1308, and an input/output device 1310 (it is to be appreciated that the electronic system 1300 may have a plurality of processors, control units, memory device units and/or input/output devices in various embodiments). In one embodiment, the electronic system 1300 has a set of instructions that define operations, which are to be performed on data by the processor 1304, as well as, other transactions between the processor 1304, the memory device 1308, and the input/output device 1310. The control unit 1306 coordinates the operations of the processor 1304, the memory device 1308 and the input/output device 1310 by cycling through a set of operations that cause instructions to be retrieved from the memory device 1308 and executed. The memory device 1308 can include a memory element having a conductive oxide and electrode stack as described in the present description. In an embodiment, the memory device 1308 is embedded in the microprocessor 1302, as depicted in Figure 13. In an embodiment, the processor 1304, or another component of electronic system 1300, includes an array of RRAM devices.

Figure 14 illustrates a computing device 1400 in accordance with one embodiment of the invention. The computing device 1400 houses a board 1402. The board 1402 may include a number of components, including but not limited to a processor 1404 and at least one communication chip 1406. The processor 1404 is physically and electrically coupled to the board 1402. In some implementations the at least one communication chip 1406 is also physically and electrically coupled to the board 1402. In further implementations, the communication chip 1406 is part of the processsor 1404.

Depending on its applications, computing device 1400 may include other components that may or may not be physically and electrically coupled to the board 1402. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touch screen display, a touch screen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The communication chip 1406 enables wireless communications for the transfer of data to and from the computing device 1400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1406 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 1400 may include a plurality of communication chips 1406. For instance, a first communication chip 1406 may be dedicated to shorter-range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1406 may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 1404 of the computing device 1400 includes an integrated circuit die packaged within the processor 1404. In some implementations of embodiments of the invention, the integrated circuit die of the processor includes one or more arrays, such as RRAM memory arrays integrated into a logic processor, built in accordance with embodiments of the present invention. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 1406 also includes an integrated circuit die packaged within the communication chip 1406. In accordance with another implementation of an embodiment of the invention, the integrated circuit die of the communication chip includes RRAM memory arrays integrated into a logic processor, built in accordance with embodiments of the present invention.

In further implementations, another component housed within the computing device 1400 may contain a stand-alone integrated circuit memory die that includes one or more arrays, such as RRAM memory arrays integrated into a logic processor, built in accordance with

embodiments of the present invention.

In various implementations, the computing device 1400 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra- mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set- top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 1400 may be any other electronic device that processes data.

Accordingly, one or more embodiments of the present invention relate generally to the fabrication of embedded microelectronic memory. The microelectronic memory may be nonvolatile, wherein the memory can retain stored information even when not powered. One or more embodiments of the present invention relate to the fabrication of RRAM memory arrays integrated into a logic processor. Such arrays may be used in an embedded non-volatile memory, either for its non-volatility, or as a replacement for embedded dynamic random access memory (eDRAM). For example, such an array may be used for 1T-1R memory or 2T-1R memory (R = resistor) at competitive cell sizes within a given technology node.

Figure 15 illustrates an interposer 1500 that includes one or more embodiments of the invention. The interposer 1500 is an intervening substrate used to bridge a first substrate 1502 to a second substrate 1504. The first substrate 1502 may be, for instance, an integrated circuit die. The second substrate 1504 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer 1500 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 1500 may couple an integrated circuit die to a ball grid array (BGA) 1506 that can subsequently be coupled to the second substrate 1504. In some embodiments, the first and second substrates 1502/1504 are attached to opposing sides of the interposer 1500. In other embodiments, the first and second substrates 1502/1504 are attached to the same side of the interposer 1500. And in further embodiments, three or more substrates are interconnected by way of the interposer 1500.

The interposer 1500 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

The interposer may include metal interconnects 1508 and vias 1510, including but not limited to through-silicon vias (TSVs) 1512. The interposer 1500 may further include embedded devices 1514, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio- frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 1500. In accordance with

embodiments of the invention, apparatuses or processes disclosed herein may be used in the fabrication of interposer 1500.

Resistive random access memory (RRAM) devices having a bottom oxygen exchange layer and their methods of fabrication are described.

In an embodiment, a resistive random access memory cell includes a conductive interconnect disposed in a first dielectric layer above a substrate. A resistive random access memory device is coupled to the conductive interconnect and includes a bottom electrode metal layer formed above the conductive interconnect. An oxygen exchange metal layer is formed on the bottom electrode metal layer. A metal oxide switching layer is formed on the oxygen exchange metal layer. A first dielectric hardmask layer is formed on the metal oxide switching layer and includes an opening with bottom and sidewalls. A portion of a top electrode metal layer is formed in the opening, on the oxygen exchange metal layer and on the bottom and along the sidewalls of the opening. A top electrode fill metal layer is then formed on the top electrode metal layer.

In one embodiment, the bottom electrode metal layer, the oxygen exchange metal layer, the metal oxide switching layer, and the first and second dielectric hardmask layers form a stack having sidewalls. The resistive random access memory device further includes a dielectric spacer film surrounding the sidewalls of the stack, extending from a lowermost portion of the bottom electrode to the uppermost portion of the second dielectric hardmask layer.

In one embodiment, the second dielectric layer is disposed on a substrate adjacent the dielectric spacer layer. An uppermost surface of the second dielectric layer, the dielectric spacer layer and the second dielectric hardmask layer are coplanar or substantially coplanar with each other.

In one embodiment, a third dielectric layer is formed on the second dielectric layer, on the dielectric spacer layer and on the second dielectric hardmask layer. The third dielectric layer includes a second opening exposing a first opening.

In one embodiment, the top electrode metal layer extends along the sidewalls of second opening in the third dielectric layer. The top electrode fill metal layer is formed in the second opening on the top electrode metal layer.

In one embodiment, the top electrode metal layer is formed on a portion of the metal oxide switching layer.

In one embodiment, metal oxide switching layer has a chemical composition, MC -x, where M is a metal and O is an oxide, and where X is approximately in the range from 0 to 0.05.

In one embodiment, the metal oxide switching layer has a thickness approximately in the range of 1-5 nanometers and the oxygen exchange metal layer has a thickness between 5-20nm.

In one embodiment, the bottom electrode metal layer and the top electrode metal layer include a material, the material selected from the group consisting of titanium nitride, tantalum nitride, tungsten and ruthenium.

In one embodiment, top electrode metal layer comprises a high work function metal selected from the group consisting of palladium (Pd), tungsten (W) and platinum (Pt), a noble metal or a metal alloy distinct from the bottom electrode metal layer.

In one embodiment, the resistive random access memory device of claim 1, wherein the top electrode metal layer and the top electrode metal fill layer are a same material, the material selected from the group consisting of titanium nitride, tantalum nitride and tungsten.

In an embodiment, a method of fabricating resistive random access memory (RRAM) device includes forming a conductive interconnect in a dielectric layer above a substrate. A bottom electrode metal layer is formed on the conductive interconnect. An oxygen exchange metal layer is formed on the bottom electrode metal layer. A metal oxide switching layer is formed on the oxygen exchange metal layer. The method further includes forming a first dielectric hardmask layer on the metal oxide switching layer and forming a second dielectric hardmask layer on the first dielectric hardmask layer. The first and the second dielectric hardmask layers are patterned to form a patterned first and a second dielectric hardmask layer. The method further includes etching the metal oxide switching layer, the oxygen exchange metal layer and the bottom electrode metal layer to form a patterned material layer stack having sidewalls. Subsequent to forming a material layer stack a dielectric spacer is formed surrounding the patterned material layer stack. The dielectric spacer layer extends from the bottom electrode metal layer to the top of the second dielectric hardmask layer. A second dielectric layer is formed on the first dielectric layer, on the patterned second dielectric hardmask layer, on the uppermost surface of the dielectric spacer layer and along the sidewalls of the dielectric spacer layer. The method further includes planarizing the second dielectric layer to form coplanar surfaces of the second dielectric layer, the first dielectric hardmask layer and the dielectric spacer layer. A third dielectric layer is formed on the first dielectric hardmask layer, the dielectric spacer layer and the second dielectric layer. A via is formed in the third dielectric layer and the first dielectric hardmask layer. A layer of top electrode metal layer is formed in the opening and along the sidewalk The method further includes forming a top electrode fill metal layer on the top electrode fill metal layer and planarizing to expose coplanar surfaces of the third dielectric layer, top electrode metal layer and the top electrode fill metal layer.

In one embodiment, forming the oxygen exchange metal layer includes a physical vapor deposition process and the metal oxide switching layer comprises a physical vapor deposition process or an atomic layer deposition process.

In one embodiment, the bottom electrode layer, the oxygen exchange metal layer and the metal oxide switching layers are formed sequentially without an air break via a physical vapor deposition process.

In one embodiment, the hardmask is formed from a material including silicon nitride, silicon carbide and any other dielectric not containing any oxygen.

In one embodiment, the sidewalls of the opening in the third dielectric layer and the first dielectric hardmask layer are vertical.

In an embodiment, a method of fabricating resistive random access memory (RRAM) device includes forming a conductive interconnect in a dielectric layer above a substrate. A bottom electrode metal layer is formed on the conductive interconnect. An oxygen exchange metal layer is formed on the bottom electrode metal layer. A metal oxide switching layer is formed on the oxygen exchange metal layer. The method further includes forming a first dielectric hardmask layer on the metal oxide switching layer and forming a second dielectric hardmask layer on the first dielectric hardmask layer. The first and the second dielectric hardmask layers are patterned to form a patterned first and a second dielectric hardmask layer. The method further includes etching the metal oxide switching layer, the oxygen exchange metal layer and the bottom electrode metal layer to form a patterned material layer stack having sidewalls. Subsequent to forming a material layer stack a dielectric spacer is formed surrounding the patterned material layer stack. The dielectric spacer layer extends from the bottom electrode metal layer to the top of the second dielectric hardmask layer. A second dielectric layer is formed on the first dielectric layer, on the patterned second dielectric hardmask layer, on the uppermost surface of the dielectric spacer layer and along the sidewalls of the dielectric spacer layer. The method further includes planarizing the second dielectric layer to form coplanar surfaces of the second dielectric layer, the second dielectric hardmask layer and the dielectric spacer layer. An opening is formed in the second dielectric hardmask layer and in the first dielectric hardmask layer to expose a portion of the metal oxide switching layer. A top electrode metal layer is formed in and along the sidewall of the opening. The top electrode metal layer is planarized to form coplanar surfaces of the top electrode, the first dielectric hardmask layer, the dielectric spacer layer and the second dielectric layer. A third dielectric layer is formed on the top electrode, the first dielectric hardmask layer, the dielectric spacer layer and the second dielectric layer. An opening is formed in the third dielectric layer to expose the top electrode and the first dielectric hardmask layer. A top electrode fill metal layer is formed in the opening, on the top electrode, the first dielectric hardmask layer and along the sidewalls of the third dielectric layer. The top electrode fill metal layer is planarized to form a top electrode contact.

In one embodiment, the opening in the first dielectric hardmask layer is smaller than the opening in the third dielectric layer.

In one embodiment, the hardmask is formed of a material consisting of silicon nitride, silicon carbide and any other dielectric not containing any oxygen.

In one embodiment, the bottom electrode layer, the oxygen exchange metal layer and the metal oxide switching layers are formed sequentially without an air break via a physical vapor deposition process.