CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is related to and claims priority to United States Provisional Application No. 62/171,739, filed June 5, 2015, the entire contents of which are herein incorporated by reference.

FIELD OF THE INVENTION

[0002] The present invention relates to methods for void-less filling of features such as vias and trenches with low resistivity ruthenium (Ru) metal for microelectronic devices.

BACKGROUND OF THE INVENTION

[0003] An integrated circuit contains various semiconductor devices and a plurality of conducting metal paths that provide electrical power to the semiconductor devices and allow these semiconductor devices to share and exchange information. Within the integrated circuit, metal layers are stacked on top of one another using intermetal and interlay er dielectric layers that insulate the metal layers from each other.

[0004] Normally, each metal layer must form an electrical contact to at least one additional metal layer. Such electrical contact is achieved by etching a feature (i.e., a via) in the interlayer dielectric that separates the metal layers, and filling the resulting via with a metal to create an interconnect. Metal layers typically occupy etched pathways in the interlayer dielectric. A "via" normally refers to any feature such as a hole, line or other similar feature formed within a dielectric layer that provides an electrical connection through the dielectric layer to a conductive layer underlying the dielectric layer. Similarly, metal layers connecting two or more vias are normally referred to as trenches.

[0005] The use of copper (Cu) metal in multilayer metallization schemes for manufacturing integrated circuits creates problems due to high mobility of Cu atoms in dielectrics, such as Si0 ₂ , and Cu atoms may create electrical defects in Si. Thus, Cu metal layers, Cu filled trenches, and Cu filled vias are normally encapsulated with a barrier material to prevent Cu atoms from diffusing into the dielectrics and Si. Barrier layers are normally deposited on trench and via sidewalls and bottoms prior to Cu seed deposition, and may include materials that are preferably non-reactive and immiscible in Cu, provide good adhesion to the dielectrics and can offer low electrical resistivity. [0006] An increase in device performance is normally accompanied by a decrease in device area or an increase in device density. An increase in device density requires a decrease in via dimensions used to form interconnects, including a larger aspect ratio (i.e., depth to width ratio). As via dimensions decrease and aspect ratios increase, it becomes increasingly more challenging to form diffusion barrier layers with adequate thickness on the sidewalls of the vias, while also providing enough volume for the metal layer in the via. In addition, as via and trench dimensions decrease and the thicknesses of the layers in the vias and trenches decrease, the material properties of the layers and the layer interfaces become increasingly more important. In particular, the processes forming those layers need to be carefully integrated into a

manufacturable process sequence where good control is maintained for all the steps of the process sequence.

[0007] The problems associated with the use of Cu metal in increasingly smaller features in a substrate will require replacing the Cu metal with other low-resistivity metals. SUMMARY OF THE INVENTION

[0008] A method is provided for void-less Ru metal feature fill for interconnects in a microelectronic device.

[0009] According to an embodiment of the invention, method is provided for at least partially filling a feature in a substrate by providing a substrate containing a feature, depositing a ruthenium (Ru) metal layer to at least partially fill the feature, and heat-treating the substrate to reflow the Ru metal layer in the feature.

[0010] According another embodiment, a method is provided for filling a feature in a substrate by providing a substrate containing a feature, depositing a conformal ruthenium (Ru) metal layer that fills the feature, and heat-treating the substrate to reflow the conformal Ru metal layer in the feature, where the conformal Ru metal layer has seam voids in the feature and the heat-treating seals the seam voids and increases the grain size of the conformal Ru metal layer in the feature.

[0011] According to yet another embodiment of the invention, a method is provided for at least partially filling a feature in a substrate by providing a substrate containing a feature formed in a dielectric layer on the substrate, forming a nucleation layer in the feature, depositing a conformal ruthenium (Ru) metal layer on the nucleation layer to at least partially fill the feature, and heat-treating the substrate to reflow the conformal Ru metal layer in the feature, where the heat-treating reduces voids in the feature fill and increases the grain sizes of the conformal Ru metal layer in the feature. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] A more complete appreciation of the invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:

[0013] FIG. 1 illustrates dimensions of narrow features in a substrate used for Ru metal fill according to an embodiment of the invention;

[0014] FIGS. 2A and 2B show cross-sectional and top view scanning electron microscopy (SEM) images of the features in a substrate used for Ru metal film filling according to an embodiment of the invention;

[0015] FIG. 3 A shows cross-sectional SEM images of Ru metal deposition in narrow features in a substrate according to an embodiment of the invention;

[0016] FIG. 3B shows cross-sectional SEM images of Ru metal deposition in narrow features in a substrate according to an embodiment of the invention;

[0017] FIGS. 4A and 4B show cross-sectional SEM images of as-deposited Ru metal layer in features in a substrate according to an embodiment of the invention; and

[0018] FIGS. 5A and 5B show cross-sectional SEM images of a heat-treated Ru metal layer in features in a substrate according to an embodiment of the invention.

DETAILED DESCRIPTION OF SEVERAL EMBODIMENTS

[0019] Methods for void-less filling of features with low resistivity Ru metal for microelectronic devices are described in several embodiments.

[0020] According to one embodiment, a method is provided for at least partially filling a feature in a substrate. The method includes providing a substrate containing a feature, depositing a Ru metal layer to at least partially fill the feature, and heat-treating the substrate to reflow the Ru metal layer in the feature. The at least partial filling takes advantage of capillary action to pull heat-softened Ru metal down into very narrow features and recrystallization of the Ru metal to form larger Ru metal grains. The inventors have discovered that this unique and unexpected result of low temperature Ru metal recrystallization and reflow can be used to replace Cu metal fill with Ru metal fill. The large grain size of the reflowed Ru metal has low electrical resistance that is needed for replacing Cu metal fill in narrow features. It has been shown that Ru metal, with its short effective electron mean free path, is an excellent candidate to meet International Technology Roadmap for Semiconductors (ITRS) resistance requirements as a Cu metal replacement at about lOnm (5nm node) minimum feature sizes. Due to many material and electric properties of Ru metal, it is less affected by downward scaling of feature sizes than Cu metal.

[0021] The feature can, for example, include a trench or a via. The feature diameter can be less than 30nm, less than 20nm, less than lOnm, or less than 5nm. The feature diameter can be between 20nm and 30nm, between lOnm and 20nm, between 5nm and lOnm, or between 3nm and 5nm. A depth of the feature can, for example be greater 20nm, greater than 50nm, greater than lOOnm, or greater than 200nm. The features can, for example, have an aspect ratio (AR, depth:width) between 2: 1 and 20: 1, between 2: 1 and 10: 1, or between 2: 1 and 5: 1. In one example, the substrate (e.g., Si) includes a dielectric layer and the feature is formed in the dielectric layer.

[0022] FIG. 1 illustrates dimensions of narrow features in a substrate used for Ru metal fill according to an embodiment of the invention. The narrow features were prepared by etching features in a Si substrate and thereafter depositing (backfilling) an oxide layer (Si0 ₂ ) in the etched features to reduce the diameter of etched features. The etched features had diameters of 50nm, 56nm, 64nm, and 80 nm. The backfilled features had diameters (widths) of about 11.5nm, about 14nm, about 17.4nm, and about 28.5nm, near the mid-depths of the features.

[0023] FIGS. 2A and 2B show cross-sectional and top view SEM images of the features in a substrate used for Ru metal film filling according to an embodiment of the invention.

Preparation of the features in the substrate was described in FIG. 1. The features in FIG. 2A had a diameter of about 14nm, a depth of about 120nm, an aspect ratio of about 8.5, and a pitch of about 112nm. The features in FIG. 2B had a diameter of about 11.5nm, a depth of about 1 lOnm, an aspect ratio of about 9.5, and a pitch of lOOnm.

[0024] FIG. 3 A shows cross-sectional SEM images of Ru metal deposition in narrow features in a substrate according to an embodiment of the invention. Preparation of the features in the substrate was described in FIG. 1. The features had diameters of about 11.5nm, about 17.4nm, and about 28.5nm. Prior to Ru metal deposition, a 15A thick TaN nucleation layer was deposited in the features using atomic layer deposition (ALD) with alternating exposures of tert- butylimido-tris-ethylmethylamido-tantalum (TBTEMT, Ta(NCMe ₃ )(NEtMe) ₃ ) and ammonia (NH ₃ ) at a substrate temperature of about 350°C. A conformal Ru metal layer with a thickness of 70A was deposited on the TaN nucleation layer by chemical vapor deposition (CVD) using Ru ₃ (CO) i2 and CO carrier gas at a substrate temperature of about 200°C. FIG. 3A shows that the features having diameters or 11.5nm and 14.5nm were effectively filled with Ru metal, whereas the narrow features having a diameters 28.5nm were not completely filled and had a void in the upper part of the narrow features.

[0025] FIG. 3B shows cross-sectional SEM images of Ru metal deposition in narrow features in a substrate according to an embodiment of the invention. Conformal Ru metal deposition of 15θΑ shows that all the features were effectively filled with Ru metal.

[0026] FIGS. 4A and 4B show cross-sectional SEM images of as-deposited Ru metal layer in features in a substrate according to an embodiment of the invention. The Ru metal layer was deposited by CVD using Ru ₃ (CO)i ₂ and CO carrier gas at a substrate temperature of about 200°C, and the features also contained a TaN nucleation layer as described in reference to FIG. 3A. The SEM magnifications in FIGS. 4A and 4B are 200,000 and 350,000, respectively. The ~28nm wide features at mid-depth are not completely filled but have a void in the Ru metal that is about 9nm wide near the top of the features.

[0027] FIGS. 5 A and 5B shows cross-sectional SEM images of heat-treated Ru metal in features in a substrate according to an embodiment of the invention. The SEM magnifications in FIGS. 4A and 4B are 200,000 and 350,000, respectively. The as-deposited Ru metal layer was heat-treated at a substrate temperature of 450°C in the presence of a forming gas for 5 min. FIGS. 5A and 5B show that the heat-treating reflowed the Ru metal in the features to effectively fill the narrow features with Ru metal having large grain sizes, and reduced or eliminated voids in the Ru metal feature fill. The filling takes advantage of capillary action to pull heat-softened Ru metal down into the very narrow features. Further, any Ru metal seam voids in the feature are sealed by the heat-treating.

[0028] The structures in FIGs. 5A and 5B may be further processed, for example by performing a planarization process (e.g., chemical mechanical polishing (CMP)) that removes excess Ru metal from above the features.

[0029] According to some embodiments, the nucleation layer may be deposited in the features by ALD or CVD prior to the Ru metal fill. The nucleation can, for example, include a nitride material. According to one embodiment, the nucleation layer may be selected from the group consisting of Mo, MoN, Ta, TaN, W, WN, Ti, and TiN. A role of the nucleation layer is to provide a good nucleation surface and an adhesion surface for Ru metal in the feature to ensure conformal deposition of the Ru metal layer with a short incubation time. Unlike when using a Cu metal fill, a good barrier layer is not required between the dielectric material and the Ru metal in the features. Therefore, in the case of a Ru metal fill, the nucleation layer can be very thin and may be non-continuous or incomplete with gaps that expose the dielectric material in the features. This allows for increasing the amount of Ru metal in a feature fill compared to a Cu metal feature fill. In some examples, a thickness of the nucleation layer can be 2θΑ or less, 15A or less, lOA or less, or 5A or less.

[0030] According to some embodiment, the Ru metal layer may be deposited by ALD, CVD, plating, or sputtering. In one example, the Ru metal layer may be deposited by CVD using Ru ₃ (CO)i2 and CO carrier gas. However, other Ru metal precursors may be used to deposit the Ru metal layer. In some examples, the Ru metal layer may include a Ru-containing alloy.

[0031] According to embodiments of the invention, the Ru metal layer may be deposited at a first substrate temperature and the subsequent heat-treating of the as-deposited Ru metal layer may be carried out at a second substrate temperature that is higher than the first substrate temperature. For example, the heat-treating may be performed at a substrate temperature between 200°C and 600°C, between 300°C and 400°C, between 500°C and 600°C, between 400°C and 450°C, or between 450°C and 500°C. Further, the heat-treating may be performed at below atmospheric pressure in the presence of Ar gas, H ₂ gas, or both Ar gas and H ₂ gas. In one example, the heat-treating may be performed at below atmospheric pressure in the presence of forming gas. Forming gas is a mixture of H ₂ and N ₂ . In another example, the heat-treating may be formed under high-vacuum conditions without flowing a gas into a process chamber used for the heat-treating.

[0032] According to one embodiment, the heat-treating may be performed in the presence of a gaseous plasma. This allows for lowering the heat-treating temperature compared to when a gaseous plasma is not employed. This allows the use of heat-treating temperatures that are compatible with low-k and ultra-low-k materials. According to some embodiments, the features may be formed in a low-k material with 2.5 < k < 3.9 or an ultra-low-k material with k < 2.5. In one example, the gaseous plasma can include Ar gas. The plasma conditions may be selected to include low-energy Ar ions.

[0033] According to another embodiment, prior to depositing the Ru metal layer, the substrate may be exposed to a treatment gas that modifies the surfaces in the features and increases the nucleation rate of Ru metal layer in the features. In one example, the treatment gas can include a nitrogen plasma, a NH ₃ plasma, a NH ₃ anneal, or a combination thereof. The exposure to the treatment gas can nitride the surfaces in the features. In one example, the treatment gas increases the hydrophilicity of surfaces in the features and thereby increases the nucleation rate of the Ru metal in the feature.

[0034] In one example, the opening of a feature may pinch off (close) and a void may form inside the feature before the feature is completely filled with a Ru metal layer. According to one embodiment, the void may be removed by removing excess Ru metal from above the feature, for example by a planarization process, thereby removing the excess Ru metal that caused the pinch off. Thereafter, the heat-treating process may be performed to reflow the Ru metal layer in the feature. According to one embodiment, this may be followed by depositing additional Ru metal layer on reflowed Ru metal layer and repeating the heat-treating process to achieve void-free filling of the feature.

[0035] Methods for void-less filling of features such as vias and trenches with low resistivity Ru metal for microelectronic devices have been disclosed in various embodiments. The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. This description and the claims following include terms that are used for descriptive purposes only and are not to be construed as limiting. Persons skilled in the relevant art can appreciate that many modifications and variations are possible in light of the above teaching. Persons skilled in the art will recognize various equivalent combinations and substitutions for various components shown in the Figures. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.