RELATED APPLICATION

[0001] This application claims priority to, and the benefit of, U.S. Provisional Application No. 63/377,925, filed September 30, 2022, which is incorporated by reference in its entirety herein.

TECHNICAL FIELD

[0002] The description here relates to semiconductor devices and, more particularly, to silicon photomultiplier (SiPM) devices.

BACKGROUND

[0003] A silicon photomultiplier (SiPM) is a solid-state, high-gain radiation detector that produces an output current pulse upon absorption of a photon. Some SiPM applications include biophotonics, LiDAR and 3D ranging, high-energy physics, aero particle physics, sorting and recycling, hazard and threat detection, fluorescence spectroscopy, scintillators, medical imaging, and more. SiPM market sectors include industrial, aerospace, automotive, oil and gas, electronics, and information and communications technology.

SUMMARY

[0004] In a general aspect, a method includes identifying a region of interest on an array of single-photon avalanche photodiodes disposed on a surface of a semiconductor device, enabling the single-photon avalanche photodiodes in the region of interest, and disabling the single-photon avalanche photodiodes that are outside the region of interest. The method further includes, in response to illumination incident on the surface of the semiconductor device, combining photocurrent outputs of the single-photon avalanche photodiodes in the region of interest in an analog photocurrent output channel of the semiconductor device.

[0005] In a general aspect; a semiconductor device includes an array of sub-pixels disposed on a surface of a semiconductor substrate. At least one of the array of sub-pixels includes a plurality single-photon avalanche detectors in a parallel configuration. A digital electronics interface is coupled to the semiconductor device. The digital electronics interface transmits a set of digital signals to configure the array of sub -pixels to include an inactive region and an active region. The sub-pixels in the inactive region are disabled and the subpixels in the active region are enabled to respond to radiation incident on the active region. In a general aspect, a semiconductor device includes an array of sub-pixels disposed in rows and columns across a plurality of sub-areas on a surface of a semiconductor substrate. At least one sub-pixel includes a plurality of single-photon avalanche detectors in a parallel configuration. A digital electronic interface is coupled to the semiconductor device. The digital electronic interface is configured to transmit a set of digital signals to configure the array of sub-pixels to include an inactive region and an active region. One or more first subpixels in the inactive region are disabled. One or more second sub-pixels in the active region are enabled to respond to radiation incident on the active region.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] FIG. l is a block diagram illustrating an example silicon photomultiplier (SiPM) device having an optically active area and an optically inactive area on its surface.

[0007] FIG. 2 symbolically illustrates an example microcell including one single-photon avalanche photodiode (SPAD).

[0008] FIGS. 3 A through 3C illustrate three example sub-pixels, each including a number of SPADs that are hard-wired in parallel in a row.

[0009] FIG. 4 illustrates regions or sub-areas of an example SiPM.

[0010] FIG. 5 A illustrates an example SiPM, in accordance with the principles of the present disclosure.

[0011] FIG. 5B illustrates an example logic circuit for configuring regions of interest (ROIs) on a SiPM.

[0012] FIG. 5C illustrates example analog output channels corresponding to different ROIs in SiPM of FIG. 5 A.

[0013] FIG. 5D illustrates an example set of signals transmitted over an SPI bus to configure the ROIs on the SiPM of FIG. 5 A.

[0014] FIG. 6A illustrates another example SiPM.

[0015] FIG. 6B illustrates two example ROIs formed in the SiPM of FIG. 6A.

[0016] FIG. 6C illustrates an example sub-pixel deployed in the SiPM of FIG. 6 A.

[0017] FIG. 6D illustrates an example set of signals for configuring ROIs in the SiPM of FIG. 6A.

[0018] FIG. 7 pictorially illustrates three example shapes of ROIs.

[0019] FIG. 8A illustrates an example set of control signals for configuring a ROI in a SiPM. [0020] FIG. 8B illustrates another example set of control signals for configuring a ROI in a SiPM.

[0021] FIG. 9 is a flow chart illustrating an example method for configuring regions of interest on a SiPM.

[0022] FIG. 10 illustrates an example sub-pixel with three selection switches.

[0023] FIG. 11 illustrates a relationship between consecutive sub-areas and primary output channels in an example SiPM.

[0024] FIG. 12 illustrates a relationship between edge sub-areas and secondary output channels of the example SiPM of FIG. 11.

[0025] FIG. 13 illustrates another example SiPM.

[0026] FIG. 14 illustrates an example method for improving a signal-to-noise ratio of an SiPM.

DETAILED DESCRIPTION

[0027] The disclosure herein is directed to silicon photomultiplier (SiPM) devices. A SiPM may include arrays of avalanche photodiodes, for example, single-photon avalanche photodiodes (SPAD), operated, for example, in Geiger mode, configured for the detection of extremely weak light, down to a single photon. Each SPAD may include, for example, an integrated series resistor which quenches the avalanche and resets the diode for the next incoming photon. Depending on the light source and application, several hundred to thousands of SPADs are connected in parallel on a silicon substrate to form a light sensitive or optically area of a SiPM. The SPADs may be arranged individually in microcells, or in groups in pixels or sub-pixels. The dimension of each single SPAD can vary from 10 to 100 micrometers, with a density of up to 10,000 per square millimeter. A SiPM is not an imaging device because all SPAD pixels, which can be referred to as microcells, share a common summing node. All the SPADs, or at least some SPADs in some implementations, in a SIPM can contribute to output signal, for example, an analog photocurrent.

[0028] Some light detection systems, for example, laser imaging, detection, and ranging (LiDAR) systems, involve, for example, determining ranges by targeting an object or a surface with a laser beam and measuring the time-of-flight. The time-of-flight, for example, can include a time for the reflected light to return to a receiver. In a SiPM device used for LiDAR of an object, not all SPADs may receive the optical signal reflected by the object, due to optical alignment, laser beam spot size, and other illumination conditions. In some implementations, the optical signal can be the returning LiDAR system laser beam. These inactive SPADs can contribute only to the noise component of the SiPM output signal, reducing the device’s signal -to-noise ratio (SNR) and worsening the overall LiDAR performance. In some implementations, the inactive SPADs may not receive an optical signal corresponding to the returning LiDAR system’s laser beam.

[0029] Systems and methods are disclosed herein for improving the signal-to-noise ratio (SNR) of a SiPM, for example, in laser imaging, detection, and ranging (LiDAR) systems, in accordance with the principles described herein.

[0030] The systems and methods for improving the SNR of a SiPM can be based on distinguishing SPADs that are, for example, active in that they receive a reflected light beam from a target object, for example, illuminated by a LiDAR system laser. The systems and methods for improving the SNR of a SiPM can be based on distinguishing SPADs that are, for example, inactive in that they do not receive the reflected light beam from the target object illuminated by the LiDAR system laser. In some implementations, the active SPADs may form an active region or regions on the surface of the SiPM, and the inactive SPADs may form an inactive region or regions on the surface of the SiPM.

[0031] The systems and methods for improving the SNR may involve turning-off the SPADs in the inactive region(s) while the SPADs in the active region(s) are turned-on. In some implementations, turning-off the SPADs in the inactive region(s) may include disabling (or not powering, or changing to an unpowered state) the SPADS in the inactive region(s). In some implementations, turning-off the SPADs in the inactive region(s) may include not reading the SPADs in the inactive region(s). In some implementations, turning-off the SPADs in the inactive region(s) may include excluding the output of these SPADs in the inactive region(s) from the output of the SiPM.

[0032] In example implementations, a silicon photomultiplier (SiPM) is a multipixel semiconductor device in which the photodiode pixels are joined together on a common silicon substrate. A SiPM can include multiple P-N junction-based sensors, for example, a single-photon avalanche photodiode (SPAD) with single-photon sensitivity that can detect light wavelengths from near-ultraviolet (UV) to near-infrared (IR). Generally, a compact solid-state SiPM provides a better alternative to bulky photomultiplier tubes and is suitable for sensing, quantifying, and timing all levels of light down to a single photon. The performance of the SiPMs makes them suitable for a wide range of photometry (light detection) applications, especially in situations where precise timing is necessary.

[0033] FIG. 1 schematically illustrates a portion of a surface S, and an example SiPM 100 with an active region 110 and an inactive region 120. In some implementations, active region 110 (also called region of interest (ROI)) includes SPAD microcells, pixels, and/or subpixels, that are enabled and contribute to the output, for example, output 150 of the SiPM. In some implementations, inactive region 120 includes SPAD microcells and/or pixels that are disabled and do not contribute to the output, for example, output 150 of the SiPM.

[0034] In example LiDAR system implementations, active region 110 may have a size and shape corresponding to the shape of the light beam spot reflected from the target object illuminated the LiDAR system laser. In the example shown in FIG. 1, active region 110 has a rectangular shape overlapping and/or covering a circular or oval shape of the light beam spot, for example, spot 110S, reflected from the target object illuminated by the LiDAR system laser. In some implementations, the shape of active region 110 may be a square, a circle, and/or an oval shape that matches, overlaps, and/or covers the circular and/or oval shape of the light beam spot.

[0035] In example implementations, a SiPM may include one or multiple active regions, for example, active region 110 in FIG. 1, called regions of interest (ROIs). The ROIs may have different size and shape. In example implementations, SiPM 100 may be coupled to a controller such as, for example, digital electronics interface 102, that can be used to dynamically control a designation and/or definition of the multiple active regions or ROIs, for example, active region 110, of different size and shape for increasing the SNR of an output current. The output current may be an analog photocurrent output of the SiPM. In example implementations, digital electronics interface 102 may be serial peripheral interface (SPI). Digital electronics interface 102 can allow a user to define a ROI and swap between different ROIs very quickly to obtain a high SNR in the output current, for example, by optimizing a size of the active region to match a footprint of an incident laser spot. In example implementations, a high SNR can be obtained by enabling a ROI which matches a physical footprint of the reflected laser spot on the sensor active area. In some implementations, matching the region of interest to a physical footprint can include covering, or at least partially covering, the physical footprint.

[0036] An input-output device, for example, device 104, may be coupled to SiPM 100. Digital electronics interface 102 may be part of the input-output device, for example, device 104. In example implementations, input-output device 104 may be a configuration and readout ASIC. In example implementations, the ASIC may be hybrid bonded to a silicon substrate (not shown) on which the SiPM is fabricated.

[0037] Input-output device 104, for example, an ASIC or other programmable device, coupled to the SiPM can allow a user to define a ROI and swap between different ROI very quickly to obtain a high SNR in the output current, for example, by minimizing a size of the active area in the SiPM. In example implementations, a high SNR can be obtained by enabling a ROI on the surface S of the SiPM that conforms to the size and shape of the light beam or spot illuminating the surface.

[0038] In example implementations, a SiPM may be configured to allow a user to define specific ROI within the surface of the SiPM. In some implementations, defining specific ROIs within the surface of the SiPM can allow the user to improve the signal -to-noise ratio of the device by enabling only the SPADs that are illuminated by the light source of interest. In some implementations, defining specific ROIs within the surface of the SiPM can allow the user to improve the signal -to-noise ratio of the device by disabling SPADs that are not illuminated by the light source of interest and would otherwise contribute only to the SiPM device noise. In some implementations, defining specific ROIs within the surface of the SiPM can allow the user to improve the signal-to-noise ratio of the device by enabling only the SPADs that are illuminated by the light source of interest, and disabling SPADs that are not illuminated by the light source of interest and would otherwise contribute only to the SiPM device noise.

[0039] FIG. 2 illustrates a microcell including one single-photon avalanche photodiode (SPAD). A few SPADs may be arranged in parallel in a row to form a small or mini SiPM with a single output. A group of the few SPADs arranged in parallel may be called a subpixel. In example implementations, the SPADs in a sub-pixel may be hard wired in parallel. A sub-pixel may correspond to a minimum resolution size or distance for defining areas or regions on the SiPM. The number of SPADs in a sub-pixel may be, for example, an integer number in the range from 2 to 50.

[0040] FIGS. 3A, 3B, and 3C show example sub-pixels, for example, sub-pixel 300, subpixel 310, and sub-pixel 320, respectively. Each sub-pixel may include any number of SPADs. For example, sub-pixel 300 may contain eight SPADs. Sub-pixel 310 may contain ten SPADs. Sub-pixel 320 may contain four SPADs. In example implementations, a given sub-pixel may have a Y dimension and X dimension on the order of 10s or 100s of micrometers. For example, sub-pixel 300 may have a Y dimension of about 10 pm, and an X dimension of about 80 pm. Sub-pixel 310 may have a Y dimension of about 10 pm, and an X dimension of about 100 pm or about 110 pm. Sub-pixel 320 may have a Y dimension of about 10 pm, and an X dimension of about 40 pm. Other dimensions of each sub-pixel are possible. [0041] The array of SPADs may be arranged in a SiPM as an array of sub-pixels, for example, sub-pixel 300. The array may be split or divided across multiple sub-areas or subregions of a surface of the SiPM. FIG. 4 schematically shows the various sub-areas, for example sub-areas 1, 2, . . . , M, of a SiPM.). The term region, for example, a region R as shown in FIG. 4, may refer to a selected one of the multiple sub-areas or sub-regions.

[0042] A region of interest (RO I), for example, active region 110, FIG. 1, on the surface of the SiPM may be defined in terms of the sub-pixels contained in the ROI. A minimum resolution of the dimensions of the ROI may be determined by the size of a sub-pixel included in the ROI. In example implementations, a SiPM includes sub-pixels of 1 x N microcells giving, for example, a resolution of 10 pm in the Y direction and 10 x N pm in the X direction (assuming a microcell pitch of 10 pm).

[0043] Each analog output channel, or a portion thereof, of SiPM may be a combination or sum of the analog photocurrent (or photovoltage) outputs of a ROI within the array of SPADs or sub-pixel. In some example implementations, a number of analog output channels may be, for example, between one and 50. The outputs of a ROI can be allocated, for example, one or more specific analog output channels.

[0044] In example implementations, a surface of a SiPM may be divided into M equal, or substantially equal, sub-areas or regions, for example, M = 34 regions. In example implementations, each region may include P x Q sub-pixels, for example, with P = 16, Q= 33. In example implementations, each sub-area or region may provide the ROI for up to four analog output channels, for example, channel A, B, C and S. In example implementations, each sub-area or region may be included in the ROI for up to four analog output channels, for example, channel A, B, C and S.

[0045] In example implementations, each sub-pixel may be associated with, or coupled to, up to four selection transistors that can select which of the one to four output channels, for example, channel A, B, C and S, is associated with the sub-pixel. In some implementations, if none of the four output channels are selected, then the sub-pixel is turned off to become inactive.

[0046] FIG. 5A shows an example SiPM 500, in accordance with the principles of the present disclosure. SiPM 500 may include several regions or sub-areas, for example, M subareas: sub-area 500-1, sub-area 500-2, . . ., and sub-area 500-M. Each of these sub-areas can include an array of sub-pixels 300 arranged in row and columns. In the example shown in FIG. 5A, each of the sub-areas, sub-area 500-1, sub-area 500-2, . . ., or sub-area 500-M, include 528 sub-pixels such as sub-pixel 300. The 528 sub-pixels may be distributed in 33 rows, for example, rows rl, r2, . . . , r33, and sixteen columns, for example, columns Cl, . . ., C16. For visual clarity, these 33 rows and 16 columns are not individually marked or fully delineated in FIG. 5A, which is not to scale. Each of these sub-areas may have a width W of 16 sub-pixels for the foregoing example of 33 rows for a total of 528 sub-pixels.

[0047] As noted previously, SIPM 500 may have several analog output channels. In example implementations, each analog output channel, or a portion thereof, may be a combination or a sum of the analog photocurrent (or photovoltage) outputs of a ROI within the array of SPADs or sub-pixel. In some example implementations, the number of analog output channels may be, for example, between one and 32 or between one and 36.

[0048] Each analog output channel may be a sum of the outputs of the sub-pixels in a single ROI within the array of SPADs. In example implementations, SIPM 500 may have, for example, four different analog output channels corresponding to four different ROIs. As shown in FIG. 5C, the four analog output channels may include channel A, channel B, channel C, and channel S, which correspond to ROI A, ROI B, ROI C, and ROI S, respectively. Three of the four output channels, for example, channel A, channel B, and channel C, may be called the primary output channels. The fourth output channel, for example, channel S, may be called the secondary output channel.

[0049] As shown in FIG. 5 A, the different analog outputs are summed by a summing circuit 520. For example, the four outputs of each sub-area 500-2, 500-2. . . 500-M may be input into the summing circuit 520. A sum or combination of channel A outputs, channel B outputs, and channel C outputs may be output by a summing circuit 520 as the primary channel outputs 522. A sum or combination of channel S outputs may be output by summing circuit 520 as the secondary channel outputs 524.

[0050] In example implementations, the secondary channel outputs 524 may represent the analog outputs of sub-pixels that are within a limited distance from an edge, for example, edge E, of the sub-area. For example, the limited distance may be within one quarter of the width of a sub-area, or another distance. In the example shown in FIG. 5 A, one quarter of the width of the sub-area may correspond to the distance between column 12 and column 16. The secondary channel outputs 524 may represent the analog outputs of ROI sub-pixels that are between column 12 and column 16 (FIG. 5A).

[0051] Furthermore, the primary channel outputs 522 may represent the analog outputs of sub-pixels that are more than one quarter of the width of a sub-area away from the edge (e.g., edge E) of the sub area. In the example shown in FIG. 5 A, the primary channel outputs 522 may represent the analog outputs of ROI sub-pixels that are between column 1 and column 12.

[0052] In some implementations, a user may use a digital interface, for example, digital electronics interface 102 in FIG. 1, coupled to SiPM 500 to define or build the different ROIs corresponding to the different analog output channels, for example, channel A, channel B, channel C, and channel S. A ROI may be constructed or built up sub-pixel by sub-pixel, using, for example, logic circuitry to turn a sub-pixel on or off, or to enable or disable that subpixel. The logic circuitry may include, for example, an AND-OR logic circuit in digital electronics interface 102. The tumed-on or enabled sub-pixel becomes a part of the ROI while the disabled sub-pixels in SIPM 500 are excluded from the ROI.

[0053] FIG. 5B shows, for example, logic circuit 540 that can be used to define four ROIs in SIPM 500 corresponding to four analog output channels, for example, channels A, B, C and S. Logic circuit 540 can be used to enable a sub-pixel 300 to belong to one of the four ROIs in SiPM 500 corresponding to four analog output channels. A user may specify the coordinates of the ROI that they want to define. The coordinates are translated into column and row address lines. The user may use a logic circuit 540, for example, an AND-OR logic circuit, to enable a sub-pixel 300 to belong to a ROI. By verifying the coordinates of the subpixel, for example, (col A, row A), (col B, row B), (col C, row C), and (col S, row S), logic circuit 540 may generate an enable signal, for example, enable signal 550. In some implementations, enable signal 550 determines that the sub-pixel, for example, sub-pixel 300, is a part of the region of interest that the user has defined.

[0054] Further, sub-pixel 300 is associated with four selection switches, for example, transistors 55A, 55B, 55C, and 55S. These transistors may be switched on to allocate at least one analog output channel , for example, channels A, B, C or S, to sub-pixel 300. When none of the four analog output channels are allocated to sub-pixel 300, the sub-pixel is designated, or determined, to be inactive and turned off.

[0055] FIG. 5C shows a portion 500C of the surface S of a SiPM 500 (FIG. 5A) on which four different ROI, for example, ROI A, ROI B, ROI C, and ROI S, have been defined by user input and are associated respective output channels, for example, Ch A, Ch B, Ch C, or Ch S. Portion 500C may represent any one of the regions or sub-areas identified as sub-areas 500-1 to 500-M in FIG. 5A. Portion 500C may be the same as sub-area 500-1 (FIG.5A). Portion 500C may have dimensions X = 16 sub-pixels and Y= 33 sub-pixels. As shown in FIG. 5C, each of ROI A, ROI B, ROI C, and ROI S may have a rectangular or square shape. ROI A may have diagonally opposite corner coordinates (AX1, AY1) and (AX2, AY2) that correspond to the top left comer and the bottom right corner of a rectangular shape. ROI A may be associated with analog output channel A, for example, CH A. ROI B may have diagonally opposite corner coordinates (BX1, BY 1) and (BX2, BY2). ROI B may be associated with analog output channel B, for example, CH B. ROI C may have diagonally opposite comer coordinates (CXI, CY 1) and (CX2, CY2). ROI C may be associated with analog output channel C , for example, CH C. ROI S may have diagonally opposite comer coordinates (SX1, SYl)and (SX2, SY2). ROI S may be associated with analog output channel S, for example, CH S.

[0056] These four ROIs may be defined by diagonally opposite corner coordinates data input through a serial peripheral interface (SPI), for example, in digital electronics interface 102 in FIG. 1. The digital electronics used to define these regions will be required to first define the XY coordinates of each of ROI A, ROI B, ROI C, and ROI S.

[0057] In the foregoing example, the region, for example, sub-area 500-1 in FIG.5 A, includes 16 sub-pixels in the X direction and 33 sub-pixels in the Y direction, which implies that the comer X coordinates, for example, AX1 and AX2, of the ROI, are between 0 and 15, and that the comer Y coordinates, for example, AY1 and AY2, of the ROI, are between 0 and 33. A number between 0 and 15 can be represented by 4 data bits, and a number between 0 and 33 can be represented by 6 data bits. Thus, 4 + 6 =10 data bits may be needed to define the XY comer coordinates of a ROI. In all, 80 bits may be needed to define the eight diagonally opposite corner coordinates of the four ROIs in portion 800.

[0058] Using an SPI bus, for example, in digital electronics interface 102, FIG. 1, with a clock frequency of 25 MHz may take 3.2 ps to transfer the 80 bits needed to define the eight diagonally opposite corner coordinates of the four ROIs in portion 500C.

[0059] FIG. 5D shows a set of signals 500D that may be transmitted over an SPI bus, for example, in digital electronics interface 102 in FIG. 1, to the SiPM to configure the ROIs, for example, ROI A, ROI B, ROI C, and ROI S, on the SiPM. The set of signals 500D may include, for example, a Clock signal, a Data signal, and a reset signal (NCS).

[0060] FIG. 6A illustrates another example SiPM 600, in accordance with the principles of the present disclosure. In SiPM 600, the array of SPADs may be arranged as sub-pixels 320 (FIG. 3C) that include only four SPADs that are hard-wired in parallel. Sub-pixels 320 (of 4 x 1 SPADs) may, for example, provide a distance resolution of 10 pm in the Y direction and 40 pm in the X direction.

[0061] In SiPM 600, the array of SPADs in the SiPM may be split or divided across sixteen sub-areas or sub-regions, for example, sub-areas 600-1, 600-2, . . . , 600-M, M=16, as shown in FIG. 6A. Each sub-area may include a total of 1254 sub-pixels 320 distributed in 19 columns and 66 rows. Further in SiPM 600, each sub-area may include only two ROIs, for example, ROI A, and ROI B, associated with two respective analog output channels, CH A, CH B, that are shown in FIG. 6B. Similarly, as shown in FIG. 6C, each sub-pixel 320 as deployed in SiPM 600 may be associated with two selection switches, for example, transistors 55A and 55B. These transistors may be switched on to allocate at least one analog output channel, for example, channel A or channel B, to sub-pixel 320. When none of the analog output channels A or B are allocated to sub-pixel 320, the sub-pixel is designated, or determined, to be inactive and is turned off.

[0062] The two ROI (ROI A and ROI B) can have any rectangular or square shape covering or overlapping the illuminating light spots being measured. FIG. 7 pictorially shows three example shapes, Example 1, Example 2, and Example 3, of the two ROIs formed in a sub-area, for example, sub-area 600-1.

[0063] In example implementations, ROI A and ROI B may be defined by two diagonally opposite comer coordinates of their respective rectangular or square shapes. For example, as shown in FIG. 6B, ROI A is defined by diagonally opposite comer coordinates (AX1, AY1) and (AX2, AY2); and ROI B is defined diagonally opposite comer coordinates (BX1, BY1) and (BX2, BY2). Since the sub-areas, for example, sub-areas 600-1, 600-2, . . . , 600-M, M=16, in which the two ROIs are defined have dimensions of 19 sub-pixels in the X direction and 66 sub-pixels in the Y direction, it may take up to 48 data bits to define the two ROIs.

[0064] FIG. 6D shows a set of signals 600D that may be transmitted over an SPI bus, for example, in digital electronics interface 102 in FIG. 1, to the SiPM to configure ROI A and ROI B on the SiPM. The SPI bus with a clock frequency 25 MHz and a period of 40 ns may take up to 1.92 ps to transfer the 48 bits needed to define the four diagonally opposite comer coordinates of the two ROIs (e.g., ROI A and ROI B) in a sub-area, for example, sub-area 600-1.

[0065] In example implementations, to configure the two ROIs in any one of the 16 subareas, using an SPI bus, may take, for example, up to 2 ps at a maximum SPI frequency of 25 MHz.

[0066] In some example implementations, to configure the ROIs on the SiPMs, for example, SiPM 500 and SiPM 600 described herein, a high-speed low-voltage differential signaling (LVDS) data transfer scheme with speeds of about 385 Mbps may be implemented to configure the ROIs on the SiPMs. The high speed LVDS may be capable of configuring the ROIs, for example, in 2 ps or less.

[0067] In some example implementations, an SPI at 25 MHz with 16 DATA lines may be used, as shown in FIG. 8A, to configure the ROIs on the SiPMs described herein. In this example, configuration of the ROIs can be achieved in 1.6 ps.

[0068] In some example implementations, a byte wide (8-bit) parallel data bus with chip select and write signals, as shown in FIG. 8B, may be used to configure the ROIs on the SiPMs described herein. In this example, with a 20 ns access time, configuration of the ROIs can be achieved in 1.6 ps.

[0069] FIG. 9 is a flow chart illustrating an example method 900 for configuring regions of interest on a SiPM.

[0070] Method 900 includes receiving input parameters (910). The input parameters may include the coordinates of an ROI in a sub-area of the SiPM. In one branch, for example, branch A, of the flow chart, the method includes setting an invalid state if the input parameters are illegal (920), and clearing all selection switches on the sub-pixels in the subarea of the SiPM (930). In a second branch, for example, branch B, of the flow chart, the method includes detecting XY coordinates of a ROI in the sub-area of the SiPM (940). The XY coordinates may include coordinates of the corners of a square or rectangular ROI. Method 900 further includes enabling the sub-pixels that are disposed within the defining XY coordinates of the ROI in the sub-area of the SiPM (950).

[0071] In the example implementations of the SiPM described in the foregoing, the array of SPADs in the SiPM are split or divided across distinct sub-areas, for example, sub-areas 500-1, 500-2, . . . , and 500-M. Further, each ROI, for example, ROI A, ROI B, ROI C, or ROI S is constructed to lie within the boundaries of a single sub-area.

[0072] In other example implementations of the SiPM described below, a ROI may extend beyond the boundaries of a single sub-area into a neighboring sub-area (or even into a next neighbor sub-areas). In some example implementations of an SiPM, an enlarged ROI can be defined to extend over up to three contiguous or consecutive sub-areas.

[0073] An example SiPM with enlarged ROIs may include an array of sub-pixels, for example, sub-pixel 330, FIG. 10. Sub-pixel 330 may be associated with three selection switches (e.g., transistors 55A, 55B, and 55C). These transistors may be switched on to allocate at least one of three analog output channel, for example, channel A, B or C, to subpixel 330. [0074] The example SiPM including ROIs and/or enlarged ROIs may have an array of sub-pixels, for example, sub-pixel 330, disposed over thirty two sub-areas and have a corresponding number analog output channels, for example, channel 0, 1, 2, 3, . . ., and 31. In some implementations, the number of analog output channels can include up to 32 channels. Some of these channels, for example, channel 0 and channel 31, may be boundary end channels associated with sub-areas at the boundaries or ends of the device. In example implementations, each non-boundary channel, for example, channel 1 2, 3, . . ., and 30, may be associated with enlarged ROIs that extend over up to three contiguous or consecutive subareas. The output of the sub-pixels in the enlarged ROI may be routed to any of the respective three output channels from among channel 0, 1, 2, 3, . . ., and 31 associated with the three contiguous or consecutive sub-areas over which the enlarged ROI extends.

[0075] FIG 11 illustrates a relationship between consecutive sub-areas and primary output channels of an example SiPM. FIG. 12 illustrates a relationship between edge subareas and secondary output channels of the example SiPM of FIG. 11.

[0076] FIG. 11 and FIG. 12 show portions of an example SiPM 1100 having an array of sub-pixels, for example, sub-pixel 300, arranged in columns and rows in 10 columns and 99 rows, on the SiPM surface. The SiPM surface may include several consecutive regions or sub-areas, for example, such as sub-area 500-1, 500-2 . . ., 500-M in FIG. 5A. These subareas are relabeled as regions, respectively R0, Rl, R2, . . ., Rn-3, Rn-2, Rn-1, and Rn in FIG. 11.

[0077] FIG. 11 illustrates the overlap of output channels and regions, for the example SiPM 1100. The sub-pixels, for example, sub-pixel 300, from a given region of the SiPM can be output onto any of the 3 primary output channels and 1 secondary output channel. However, sub-pixels in the two regions at extreme ends of array are excluded from the 3 primary output channels, as shown in FIG. 11 and FIG. 12. The purpose of the exclusion of the two regions at the extreme ends of the array may be to avoid defined partitions between the regions. A ROI can spread or extend across a boundary of a region into a neighboring region in some implementations.

[0078] In some implementations, the secondary output channels are used to enable a larger ROI, which in example implementations can span up to one quarter of the total sensor area.

[0079] In SiPM 1100, the array of sub-pixels may be disposed over 10 columns, for example, col. 0 ,. . ., and 9, and 99 rows, for example, row 98, . . ., and row 0. The SiPM may have several (e.g., 32 to 36 ) specific analog output channels including primary output channels, such as primary channel outputs 522, FIG. 5A, and secondary channel outputs, such as secondary channel outputs 524, FIG. 5A. In example implementations, as schematically shown in FIG. 11, there may be 32 primary channels, for example, CHO, CHI, CH2, CH3, CH4, . . ., CH30, and CH 31. Each primary channel may include the analog photocurrent outputs of the active sub-pixels in 10 columns, for example, col. 0,. . ., and 9, that extend over 3 consecutive sub-areas or regions, for example, from regions RO, Rl, R2, . . ., Rn-3, Rn-2, Rn-1, and Rn, and extend over 99 sub-pixel lines, for example, row 98, . . ., and row 0.

[0080] In example implementations, as shown in FIG. 11, primary channel CHO can include output contributions from active (enabled) sub-pixels in three consecutive regions Rl, R2, and R3 : primary channel CHI can include output contributions from active sub-pixels in three consecutive regions R2, R3, and R4; primary channel CH2 includes output contributions from active sub-pixels in three consecutive regions R3, R4, and R5. Furthermore, primary channel CH30 includes output contributions from active sub-pixels in three consecutive regions Rn-3, Rn-2, and Rn-1; and primary channel CH31 includes output contributions from active sub-pixels in three consecutive regions Rn-2, Rn-1, and Rn.

[0081] In SiPM 1100, as schematically shown in FIG. 12, there may be 4 secondary channels, for example, CH32, CH33, CH34, and CH35, in addition to the primary channels, for example, CHO, CHI, CH2, CH3, CH4, . . ., CH30, and CH31, shown in FIG. 11. Each secondary channel may include the analog photocurrent outputs of the sub-pixels that extend over one quarter of the array of sub-pixels. The array of sub-pixels may have a total of 1122 row lines in 10 columns. The number of 1122 row lines is not divisible exactly by four (1122/4 = 280.5), therefore all the four secondary channels cannot be assigned exactly one quarter of the array of sub-pixels. Instead, CH32 and CH35 may each be allotted row lines 0 to 281, which is one more than the number of lines, for example, row lines 0 to 280, allotted to each of CH33 and CH34. As shown in FIG. 12, in example implementations, secondary channels CH32 and CH35 may include the analog photocurrent outputs of the sub-pixels that are in row lines (0 to 280) under columns (0 to 9), and secondary channels CH33 and CH34 may include the analog photocurrent outputs of the active sub-pixels that are in row lines (0 to 279) under columns (0 to 9).

[0082] FIG. 13 illustrates another example SiPM including various regions of interest (ROI) defined in the array of SPADs on the surface of the SiPM.

[0083] SiPM 1300 may include M regions or sub-areas (e.g., SiPM Region #1, Region #2, Region #3, . . . Region #M). The array of SPADs may be an array of sub-pixels, for example, sub-pixel 300. Each of these sub-areas can include an array of sub-pixels 300 arranged in row and columns across the M regions. A number N of the ROIs may be formed in the array of sub-pixels 300 across the M regions. The ROIs, for example, ROI 1, ROI 2, ROI 3, . . . ROI N, may have a rectangular or a square shape. Each region may have ROIs of different shape, size, and number. The various ROIs may include different numbers of subpixels, have different aspect ratios (width and length) and different positions, for example, relative to a center or an edge of a region.

[0084] As shown in FIG. 13, region 1 may contain two non-overlapping ROIs, for example, ROI 1 and ROI 2. ROI 1 and ROI 2 may both have rectangular shapes of different sizes. Region 2 and region 3 may include an enlarged ROI, for example, ROI 3, that extends from region 2 to region 3. ROI 3 may have a square shape. Region 3, in addition to a portion of ROI 3, includes another ROI (e.g., ROI 4). ROI 4 may have a rectangular shape. Further, region M may include a single ROI, for example, ROI N. ROI N may, for example, have a rectangular shape of a different size than the previously mentioned ROIs, for example, ROI 1, ROI 2, and ROI 4, having rectangular shape.

[0085] The N ROIs in M regions of SiPM 1300 can be readout through a number of parallel output channels, for example, N channels: CH 1, CH 2, CH 3, CH 4, . . ., and CH N.

[0086] A dedicated summing circuit 1320 may be implemented to arrange the sub-pixels from the regions to create the ROIs providing an analog output signal for each of the N output channels.

[0087] FIG. 14 illustrates a method 1400 for improving a signal -to-noise ratio (SNR) of an SiPM. Method 1400 includes identifying a region of interest on an array of single-photon avalanche photodiodes disposed on a surface of a semiconductor device (1410). The method further includes enabling the single-photon avalanche photodiodes in the region of interest (1420), and disabling the single-photon avalanche photodiodes that are outside the region of interest (1430). The method further includes, in response to illumination incident on the surface of the semiconductor device, combining photocurrent outputs of the single-photon avalanche photodiodes in the region of interest in an analog output channel of the semiconductor device (1440).

[0088] In method 1400, combining the photocurrent outputs of the single-photon avalanche photodiodes in the region of interest under illumination in the analog photocurrent output of the semiconductor device includes excluding current outputs of the single-photon avalanche photodiodes that are outside ROI. [0089] Further, in method 1400, identifying the region of interest includes identifying the region of interest matching in shape and size to a spot of illumination incident on the surface of the semiconductor device.

[0090] In method 1400, identifying the region of interest includes receiving a corner coordinate of the ROI over a digital electronics interface coupled to the semiconductor device.

[0091] The various apparatus and techniques described herein may be implemented using various semiconductor processing and/or circuit design techniques. Some embodiments may be implemented using various types of semiconductor processing techniques associated with semiconductor substrates including, but not limited to, for example, Silicon (Si), Gallium Arsenide (GaAs), Silicon Carbide (SiC), and/or so forth.

[0092] It will also be understood that when an element, such as a layer, a region, or a substrate, is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, it may be directly on, connected or coupled to the other element, or one or more intervening elements may be present. In contrast, when an element is referred to as being directly on, directly connected to or directly coupled to another element or layer, there are no intervening elements or layers present. As used herein, coupled to, or coupled with can refer to being electrically coupled to, electrically coupled with, physically coupled to, and/or physically coupled with.

[0093] Although the terms directly on, directly connected to, or directly coupled to may not be used throughout the detailed description, elements that are shown as being directly on, directly connected or directly coupled can be referred to as such. The claims of the application may be amended to recite exemplary relationships described in the specification or shown in the figures.

[0094] As used in this specification, a singular form may, unless definitely indicating a particular case in terms of the context, include a plural form. Spatially relative terms, for example, over, above, upper, under, beneath, below, lower, and so forth, are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. In some implementations, the relative terms above and below can, respectively, include vertically above and vertically below. In some implementations, the term adjacent can include laterally adjacent to or horizontally adjacent to.

[0095] Example implementations can include a non-transitory computer-readable storage medium comprising instructions stored thereon that, when executed by at least one processor, are configured to cause a computing system to perform any of the methods described above. Example implementations can include an apparatus including means for performing any of the methods described above. Example implementations can include an apparatus including at least one processor and at least one memory including computer program code, the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus at least to perform any of the methods described above.

[0096] Various implementations of the systems and techniques described here can be realized in digital electronic circuitry, integrated circuitry, specially designed ASICs (application specific integrated circuits), computer hardware, firmware, software, and/or combinations thereof. These various implementations can include implementation in one or more computer programs that are executable and/or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0097] These computer programs (also known as programs, software, software applications or code) include machine instructions for a programmable processor, and can be implemented in a high-level procedural and/or object-oriented programming language, and/or in assembly/machine language. As used herein, the terms “machine-readable medium” “computer-readable medium” refers to any computer program product, apparatus and/or device (e.g., magnetic discs, optical disks, memory, Programmable Logic Devices (PLDs)) used to provide machine instructions and/or data to a programmable processor, including a machine-readable medium that receives machine instructions as a machine-readable signal. The term “machine-readable signal” refers to any signal used to provide machine instructions and/or data to a programmable processor.

[0098] In addition, the logic flows depicted in the figures do not require the particular order shown, or sequential order, to achieve desirable results. In addition, other steps may be provided, or steps may be eliminated, from the described flows, and other components may be added to, or removed from, the described systems. Accordingly, other implementations are within the scope of the following claims.

[0099] Methods discussed above, some of which are illustrated by the flow charts, may be implemented by hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented in software, firmware, middleware or microcode, the program code or code segments to perform the necessary tasks may be stored in a machine or computer readable medium such as a storage medium. A processor(s) may perform the necessary tasks.

[00100] In the above illustrative implementations, reference to acts and symbolic representations of operations (e.g., in the form of flowcharts) that may be implemented as program modules or functional processes include routines, programs, objects, components, data structures, etc., that perform particular tasks or implement particular abstract data types and may be described and/or implemented using existing hardware at existing structural elements. Such existing hardware may include one or more Central Processing Units (CPUs), digital signal processors (DSPs), application-specific-integrated-circuits, and/or field programmable gate arrays (FPGAs) computers.

[00101] While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes, and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the embodiments. It should be understood that they have been presented by way of example only, not limitation, and various changes in form and details may be made. Any portion of the apparatus and/or methods described herein may be combined in any combination, except mutually exclusive combinations. The embodiments described herein can include various combinations and/or sub-combinations of the functions, components and/or features of the different embodiments described.