Title:
STACKED 1T-nMEMORY CELL STRUCTURE
Document Type and Number:
WIPO Patent Application WO2003098636
Kind Code:
A3
Abstract:
This invention relates to memory technology and new variations on memory array architecture to incorporate certain advantages from both cross-point and 1T-1Cell architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1Cell architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor (16) is used to read multiple memory cells, which can be stacked vertically above one another in a plurality of memory array layers arranged in a "Z" axis direction. This memory architecture can be applied for various memories such as MRAM, PCRAM, FERAM, polymer memory and chalcogenide memory.
Inventors:
NEJAD HASAN
SEYYEDY MIRMAJID
SEYYEDY MIRMAJID
Application Number:
PCT/US2003/015435
Publication Date:
July 15, 2004
Filing Date:
May 16, 2003
Export Citation:
Assignee:
MICRON TECHNOLOGY INC (US)
International Classes:
G11C11/15; G11C11/16; H01L21/8246; H01L27/22; H01L27/24; (IPC1-7): G11C11/15; G11C11/16; H01L27/22; H01L27/10; H01L27/24; H01L21/8246; G11C7/18
Foreign References:
| EP1109170A2 | 2001-06-20 | |||
| US20020037595A1 | 2002-03-28 | |||
| EP1321941A1 | 2003-06-25 | |||
| US20030103377A1 | 2003-06-05 |
Other References:
PATENT ABSTRACTS OF JAPAN vol. 2000, no. 25 12 April 2001 (2001-04-12)
PATENT ABSTRACTS OF JAPAN vol. 2002, no. 04 4 August 2002 (2002-08-04)
PATENT ABSTRACTS OF JAPAN vol. 2002, no. 04 4 August 2002 (2002-08-04)
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