Title:
SAFETY ENHANCEMENT FOR MEMORY CONTROLLERS
Document Type and Number:
WIPO Patent Application WO/2019/140364
Kind Code:
A1
Abstract:
A memory controller includes a generator circuit configured to generate a predetermined pattern of data, an address input, and a memory interface circuit. The memory interface circuit is configured to write the predetermined pattern of data to a memory at an address identified in the address input. The memory interface circuit is further configured to read a stored pattern of data from the memory at the address. The memory controller further includes an integrity checker circuit configured to compare the predetermined pattern of data and the stored pattern of data and identify an error of the memory based upon the comparison.
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Inventors:
VERGNES ALAIN (FR)
MATULIK ERIC (FR)
MAUNIER MARC (FR)
MATULIK ERIC (FR)
MAUNIER MARC (FR)
Application Number:
PCT/US2019/013461
Publication Date:
July 18, 2019
Filing Date:
January 14, 2019
Export Citation:
Assignee:
MICROCHIP TECH INC (US)
International Classes:
G11C29/08; G11C29/02; G11C29/04; G11C29/10; G11C29/12; G11C29/34; G11C29/36; G11C29/38; G11C29/52
Foreign References:
| US20020184578A1 | 2002-12-05 | |||
| US4827476A | 1989-05-02 | |||
| US20120099389A1 | 2012-04-26 |
Other References:
None
Attorney, Agent or Firm:
SLAYDEN, Bruce W., II (US)
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