The invention relates to a sampling device which comprises a plurality of track-and-hold-units that are operated in a time-interleaved mode.

The increasing need for wideband communication systems drives an increasing demand for suitable measurement systems. For analyzing those communication systems, the measurement systems need a really high bandwidth and a good jitter performance. In order to obtain a measurement system having such a good jitter performance, the whole clock tree has to be stabilized. The publication E. W Jacobs et al . "Optically clocked track-and-hold for high-speed, high-resolution analog-to- digital conversion" IEEE MWP '04, 2004, pages 190 - 192, describes a track-and-hold-unit that can be used within an analogue-to-digital-converter, wherein the track-and-hold- unit receives an optical clock. The track-and-hold-unit therefore comprises two photodiodes that are used for generating an electrical current which is fed into a diode circuit thereby turning off a lower current from two current sources. Whenever an optical pulse is received by the two photodiodes, a high frequency signal is kept constant at the output of the diode bridge.

It is a drawback of the publication that the sampling rate is limited, because the necessary hold-times for the analog/digital-converter cannot be reduced anymore.

It is therefore the object of the present invention to create a sampling device that has a very high sampling rate as well as a good jitter performance. This object is solved by the features of the independent claim 1 relating to a sampling device. Any beneficial further developments of the invention are defined in the dependent claims.

The inventive sampling device comprises a first input port and a second input port, wherein an input-signal is fed to the first input port and wherein an optical clock signal is fed to the second input port. The sampling device further comprises a plurality of track-and-hold-units, wherein each of the plurality of the track-and-hold-units is connected to the first input port and wherein the plurality of the track-and-hold-units is also connected to the second input port through an optical waveguide in such a manner that the plurality of the track-and-hold-units operate in a time-interleaved mode. It is very

advantageous that a plurality of track-and-hold-units are used and that a single optical clock signal can be

forwarded to those plurality of track-and-hold-units, so that only one light source is needed. It is further beneficial that the plurality of the track-and-hold-units operate in a time-interleaved mode. This ensures that the input-signal is captured by the plurality of the track- and-hold-units at different times, thereby allowing each of the plurality of the track-and-hold-units to store a part of the input-signal for a longer time.

It is also very advantageous if the optical waveguide comprises delay units, wherein the delay units delay the optical clock signal by a period of At=l/ (N-f _c i _k ) , wherein f _c i _k is the frequency of the optical clock signal and wherein N is the number of the plurality of the track-and- hold-units. Therefore, each track-and-hold-unit has N times more time to hold a part of the input-signal for the following analogue-to-digital-conversion circuit, thereby increasing the sampling frequency by the factor of N. It is very advantageous if each delay unit is a part of the optical waveguide and if each delay unit has the shape of a meander and/or if each delay unit has segments that are parallel to each other and if each delay unit has other segments that connect the parallel segments to each other, wherein the other segments are round having a diameter that is equal or larger than the distance between the two parallel segments. The use of such delay units, that have the shape of a meander having parallel segments as well as the use of the other round segments connecting the parallel segments to each other, ensure that the power loss of the optical clock signal is minimized. However, no corners or other disadvantageous changeovers are used within the delay units. It is further beneficial if the delay unit is a part of the optical waveguide and if this part of the optical waveguide, which forms the delay unit, has the shape of a spiral, wherein an inner segment of the delay unit which is also an inner segment of the spiral is lead to the outside within a straight line, thereby crossing the other segments at an angle of about 90°. If an angle of 90° is maintained, it is possible that the optical clock signal in different segments of the optical waveguide can cross itself without interfering itself. Therefore, the optical waveguide can be applied very easily.

It is also very advantageous, if the optical waveguide comprises N-l optical power dividers, wherein N is the number of the plurality of the track-and-hold-units , wherein each optical power divider splits the optical waveguide into a first branch and a second branch, and/or if the ratio of the signal power at each branch can be selected by adjusting the divergency angle of the first branch and the divergency angle of the second branch with respect to an incoming signal line of the optical power divider. The use of such optical power dividers is very helpful, because the jitter performance is not degraded. It is also very useful, if the signal power at each branch can be adjusted, because it can be guaranteed that each of the plurality of the track-and-hold-units receives the same signal level.

It is also very beneficial if the N-l optical power dividers are connected in the structure of a binary tree whose root is located at the second input port and whose N terminal branches connect to the N track-and-hold units. The terminal branches are also the leaf nodes of the binary tree. It should be noted, that all kinds of binary trees can be used, like a perfect binary tree or a

complete binary tree.

Furthermore, it is advantageous, if at least one delay unit is arranged within the second branch of each of the N-l optical power dividers. This ensures that every track- and-hold-unit operates at a different time, so that every track-and-hold-unit captures a different part of the input-signal . It is further beneficial if the depths of all branches of the tree-structure comprising all descendants of the first optical power divider are the same and/or if the number of the delay units that are ranged within the second branch of every optical power divider equals the number of the track-and-hold-units that are connected as descendants to that respective branch and/or if no delay unit is arranged within the first branch of every optical power divider. This ensures that all N-l optical power dividers are arranged symmetrically so that the only difference in the various branches is the number of the delay units. This allows that the signal power can be adjusted more easily within the N-l optical power dividers, so that each of the plurality of the track-and-hold-units receives

approximately the same signal level.

It is also very advantageous if the sampling device comprises a plurality of opto-electronic flip-flops, wherein each of the plurality of the opto-electronic flip- flops transforms the optical clock signal into an

electrical clock signal, wherein each of the plurality of the opto-electronic flip-flops connects each of the track- and-hold-units to the optical waveguide. This ensures that the electrical clock signal has a duty cycle of

approximately 50%, wherein the light pulses of the optical clock signal are much smaller.

It is also very beneficial if the optical waveguide is made of a layer of germanium or S1O ₂ and/or if the optical waveguide, the optical power splitters and the delay units are made of germanium or S1O ₂ and if they are arranged on a first part of the wafer and if the plurality of the track-and-hold-units and the opto-electronic flip-flops are made of SiGe and if they are arranged on a second part of the wafer and if the opto-electric flip-flop comprises a photodiode that is arranged in between the two parts of the wafer. This ensures that the wafer can be used by the optic elements as well by the electronic elements. This allows that all of the aforementioned components can be integrated within a single chip, thereby reducing the unit costs .

It is further beneficial if a mode locked laser is used to generate the optical clock signal and if the mode locked laser is connected through an optical fiber to the second input port. A mode locked laser has very good jitter performance as well as an output power on the order of 30 mW .

Different embodiments of the present invention are

described exemplary in the following with reference to the description. This is done by the way of example only, without limitation. Identical elements have the same reference signs. The figures in the drawings show:

Fig. 1 a high speed sampling unit comprising an

embodiment of the sampling device according the present invention and a plurality of track- and-hold-units which are operated in a time- interleaved mode;

Fig. 2 a sampling device according to an embodiment of the present invention;

Fig. 3 a simplified layout of the sampling device

according to an embodiment of the present invention ; Fig. 4 a simplified layout of the sampling device

according to another embodiment of the present invention ; Fig. 5A an embodiment of an optical power divider according to the present invention;

Fig. 5B an embodiment of an optical waveguide operating as delay unit according to the present invention ;

Fig. 5C another embodiment of an optical waveguide

operating as delay unit according to the present invention;

Fig. 6 an embodiment of an opto-electronic flip-flop used as an electronic clock generator; Fig. 7 an embodiment of a simplified track and hold

unit; and an embodiment of a simplified chip structure carrying the sampling device according to the present invention.

Fig. 1 shows a high-speed sampling unit 1 comprising the sampling device 2, which in turn comprises track-and-hold- units li, I2 to 7 _N which are operated in a time-interleaved mode. In some cases, the high-speed sampling unit 1 can be integrated within a single chip or ASIC. However, it is also possible that the sampling device 2 can be integrated on a chip of its own while the analog/digital-converters 3i, 3 ₂ to 3 _N are located on separate chips. It should be noted, that the analog/digital-converters 3i, 3 ₂ to 3 _N are only incorporated within Fig. 1 for a better understanding and that they are not a necessary part of the invention. The sampling device 2 further comprises a first input port 4 and a second input port 5. An electrical input-signal, i.e. a RF-signal, is fed to the first input port 4. The RF-signal is a high-frequency signal having a bandwidth of approximately up to 30 GHz and above. The RF-signal is then amplified by at least one amplifier 6. However, if N is small, for example four or eight the RF-signal does not need to be amplified. The amplification factor of the at least one amplifier 6 is preferably adjustable. The amplified RF-signal is then fed to each of a plurality of the track-and-hold-units li, 7 ₂ to 7 _N . The amplified RF-signal can therefore be split up for example by using a 3-dB hybrid-coupler. It is also possible to abstain from using a 3-dB hybrid-coupler within a chip, because the signal lines should be short enough.

Furthermore, the high-speed sampling unit 1 comprises an optical clock source 8. The optical clock source is preferably a mode locked laser 8. The mode locked laser 8 is difficult to integrate within a chip together with the other components of the high-speed sampling unit 1. The mode locked laser 8 generates an optical clock signal having a frequency f _c i _k of, for example, 10 GHz. The energy for each pulse exceeds for example 3 pJ and the timing jitter is smaller than 20 fs RMS.

The sampling device 2 preferably comprises the at least one amplifier 6, the plurality of the track-and-hold-units 7i, I2 to 7 _N as well as at least one optical power divider 9 and at least one delay unit lOi, 10 ₂ .

The mode locked laser 8 is connected to the second input port by using an optical fiber. Within the sampling device 2 which can also be within a chip, an optical waveguide 11 is used to lead the optical clock signal to each of the plurality of the track-and-hold-units 1 \ , I 2 to 7 _N . It is very important that the optical clock signal is fed to the plurality of the track-and-hold-units 7i, I 2 to 7 _N in such a manner that the plurality of the track-and-hold-units are operated in a time-interleaved mode.

The second input port 5 which is connected to the optical waveguide 11 is connected to a first optical power divider 9. A first branch of the first optical power divider is connected to the first track-and-hold-unit 7χ. A second branch of the first optical power divider 9 is connected to a first delay unit lOi. The first delay unit lOi is further connected to a another delay unit 10 _M , wherein M > 1 and eN. Within the first delay unit lOi there is also another optical power divider which splits up the optical clock signal into a signal that is fed to the second track-and-hold-unit 7 ₂ . Another signal of the another optical power divider is then fed to the other track-and-hold-units 7 _N , wherein N > 2 and NeN.

It should also be noted that all branches which extend from every optical power divider 9 still belong to the optical waveguide 11. Every delay unit lOi to 10 _M delays the optical clock signal by a period At=l / (N · f _c i _k ) , wherein f _c i _k is the frequency of the optical clock signal. If the number for N is three for example, each delay unit lOi to 10 _M delays the optical clock signal by the factor of 1/3 period. This means that the track-and-hold-units 7ι, I 2 to 7 _N can store a part of the RF-signal for a whole clock period, thereby ensuring that the RF-signal is sampled with a frequency that is three times higher than the frequency of the optical clock signal. Each of the plurality of the track-and-hold-units l _\r I2 to 7 _N comprises further a plurality of opto-electronic flip- flops 12i, 12 ₂ to 12 _N which transform the optical clock signal into an electrical clock signal. The plurality of the opto-electronic flip-flops 12i, 12 ₂ to 12 _N therefore connect each of the track-and-hold-units 7i, I2 to 7 _N to the optical waveguide 11. The plurality of the opto ^¬ electronic flip-flops 12i, 12 ₂ to 12 _N also enhance the duty cycle of the electrical clock signal to approximately 50%. The opto-electronic flip-flops 12i, 12 ₂ to 12 _N can be integrated within the track—and—hold—units 7χ, 7 ₂ to 7^, but they can also be separated from the respective track- and-hold-units li, 7 ₂ to 7 _N . Thus they can be integrated somewhere in the sampling device 2.

The output of each of the plurality of the track-and-hold- units li, 7 ₂ to 7 _N is preferably connected to an amplifier 13i, 13 ₂ to 13 _N . The amplifiers 13i, 13 ₂ to 13 _N drive the inputs of the analog/digital converters. Furthermore, the analog/digital-converters 3i, 3 ₂ to 3 _N are preferably arranged outside of the chip, because the chip may not be large enough. Each of the analog/digital-converters 3i, 3 ₂ to 3 _N has a plurality of parallel output ports which can be used for a high-speed data transfer.

Fig. 2 shows a sampling device 2 according to the present invention. The sampling device 2 comprises a plurality of track-and-hold-units 7i, 7 ₂ to 7 _N . In this case the

interleaving factor N equals eight, which also means that there are eight track-and-hold-units 7i, I2 to 7 _N . It can also be seen that there is a plurality of delay units lOi to 10 _M . Each delay unit lOi, 10 _M is a part of the optical waveguide 11 which is explained in detail below. The optical waveguide 1 1 further comprises N-l optical power dividers 9i to 9N-I wherein N is the interleaving factor as well as the number of the plurality of the track-and-hold-units 7 i , I 2 to 7 _N . Each optical power divider 9i to 9N-I splits the optical waveguide 1 1 into a first branch and into a second branch. If the optical waveguide 1 1 is nearly lossless, each branch should get half the incoming optical power. In practice, the optical waveguide may have substantial losses, whereby a larger attenuation will occur on a branch with a large delay compared to a branch with a small delay. In this case, it is preferable to provide more power to the branch with a large delay so that the power at the output of each branch will be substantially equal. The ratio of the signal power at each branch can be selected by adjusting the divergency angle of the first branch and the divergency angle of the second branch with respect to the incoming signal line of the respective optical power divider 9i to 9 _N _i . These details will also be explained below.

The ratio of the signal power of all N-l optical power dividers 9i to 9 _N -i is adjusted in such a way that the signal power at each end node of the optical waveguide 1 1 or at each of the plurality of the track-and-hold-units

7 i , 7 ₂ to 7 _N is approximately the same. More precisely, the ratio of the signal power of all N-l optical power

dividers 9i to 9 _N -i has to be adjusted in such a way that the signal power should be the same at the input port of the plurality of the opto-electronic flip-flops 12 i , 12 ₂ to 12 _N , wherein the opto-electronic flip-flops 12 i , 12 ₂ to 12 _N are integrated within the track-and-hold-units 7 ι , I 2 to 7 _N or wherein the opto-electronic flip-flops 12 i to 12 _N are arranged in front of the track-and-hold-units 1 _\ , 7 ₂ to 7 _N , i.e. upstream in the signal path.

Fig. 2 describes a symmetrical tree-structure of the optical waveguide 11. This means that the depth of all branches of the tree-structure is the same, wherein the tree-structure comprises all descendants of the first optical power divider 9i. The descendants comprise the further optical power dividers 9 ₂ to 9 _N _i as well as the plurality of the delay units lOi, 10 ₂ to 10 _M . The

descendants are connected to the first branch or the second branch of the first optical power divider 9i. The first optical power divider 9i is thereby connected to the second input port 5. In the embodiment of Fig. 2 the depth of the tree-structure is three.

Furthermore, the number of the delay units lOi to 10 _M arranged within a second branch of every optical power divider 9i to 9 _N _i equals the number of the track-and-hold- units 7i, 7 ₂ to 7 _N that are connected as descendants to the respective branch. For example, the second branch of the first optical divider 9i comprises four delay units lOi. This is indicated by the number "4" before At. However, the second branch of the first optical divider 9i is connected to four track-and-hold-units li, 7 ₂ to 7 _N at the end. The same also applies to the second branch of the second optical divider 9 ₂ . The second branch of the second optical divider 9 ₂ is connected to two track-and-hold- units 7i, 7 ₂ to 7 _Ni which means that two delay units 10 ₂ are incorporated within the second branch of the second optical power divider 9 ₂ .

A branch is a line segment of the optical waveguide 11 that extends from the output of each of the optical power dividers 9i to 9 _N -I and ends at the input of the descendant optical power divider 9i to 9 _N -i or at the input port of the opto-electronic flip-flop 12i to 12 _N or at the input port of the track-and-hold-unit 7i, I2 to 7 _N . Into each branch a delay unit lOi to 10 _M can be incorporated. As described in detail below the delay unit lOi to 10 is an integral part of the optical waveguide 11 having a special wiring . In the embodiment of Fig. 2 according to the present invention no delay units lOi to 10 _M are arranged within the first branch of every optical power divider 9i to 9 _N _i . It is clear that the optical clock signal, which is fed to the first track-and-hold-unit li _r is only delayed by the length of the optical waveguide 11 from the second input port 5 to the respective input port of the opto-electronic flip-flop 12i of the first track-and-hold-unit 7χ. However, the optical clock signal of the second track-and-hold-unit 7 ₂ is delayed by one delay unit by a period At=l / (N · f _c i _k ) . If the period has a length of 100 ps the optical clock signal for the second track-and-hold-unit 7 ₂ is delayed by 12.5 ps. It is also clear that the clock signal for the third track-and-hold-unit 7 ₃ is delayed by 25 ps compared to the clock signal fed to the first track-and-hold-unit 7L

When calculating the division ratio of the optical power dividers 9i to 9 _N _i the amount of the descendant branches have to be taken into account comprising the amount of the descendant delay units 9i to 9 _N _i . For example, the first branch of the first optical power divider 9i comprises four descendant delay units lOi to 10 _M , wherein the second branch of the first optical power divider 9i comprises eight delay units lOi to 10 _M . Putting all this information together, the division ratio of all the optical power dividers 9i to 9 _N -i can be calculated, so that the input signal level is the same for all of the plurality of the opto-electronic flip-flop 12 i to 12 _N or for the plurality of the track-and-hold-units 7 ι , 7 ₂ to 7 _N .

However, it should be clear that the tree-structure described above can also be brought forward to a sampling device 2 having more or less track-and-hold-units li, 7 ₂ to 7 _N than shown in Fig. 2 .

There are also other tree-structures possible that do not have to be symmetrical. However, all tree-structures have in common that the root-node is connected to the second input port 5 and that a plurality of end-nodes are

connected to the plurality of the track-and-hold-units li, 7 ₂ to 7 _N or to the plurality of the opto-electronic flip- flops 12 i to 12 _N . The at least one delay unit l O i to 10 _M delays the optical clock signal in such a manner that each of the plurality of the track-and-hold-units li, 7 ₂ to 7 _N captures a part of the RF (radio frequency) -input-signal at a different time.

As already mentioned other tree-structures for the optical waveguide 11 can also be used. For example, the N-l optical power dividers 9i to 9 _N -i can be connected in series so that each optical power divider 9i to 9 _N is connected to the second branch of a respective parent optical power divider 9i to 9 _N _i , wherein the first optical power divider 9 i is connected to the second input port 5 and wherein the first branch of each of the N-l optical power dividers 9 i to 9 _N _i is connected to the respective track-and-hold-unit 7 i , 7 ₂ to 7 _N . Such a structure is shown in Fig. 1 for example. Furthermore, one delay unit 1 0 i to 1 0 _M is arranged within the second branch of each of the N- 1 optical power

dividers 9i to 9N-I · This kind of tree-structure can preferably be used if the number of the track-and-hold- units li, I2 to 7 _N is small. Thus, the division ratio within the first optical power divider 9i can easily be adjusted. However, if there are, for example, 32 track- and-hold-units li, 7 ₂ to 7 _N the first optical power divider 9i should have a division ratio of at least 1 : 32 which is difficult to obtain.

The plurality of the track-and-hold-units li, 7 ₂ to 7 _N are connected to the plurality of amplifiers 13 i to 13 _N , wherein the output of the plurality of the amplifiers 13 i to 13 _N is preferably also the output of the chip.

Fig. 3 shows a simplified layout of the sampling device 2 according to an embodiment of the present invention. As already mentioned an RF-signal is fed to the first input port 4 . Within an RF-distribution circuit 30 , the RF- signal is split into N individual signals which are fed to the plurality of the track-and-hold-units 7 ι , I2 to 7 _N . The RF-distribution circuit 30 comprises several amplifiers 6 for amplifying each of the individual RF-signals. It should be noted that the RF-distribution circuit 30 is matched with respect to the first input port 4 .

Furthermore, as already described, an optical clock signal is fed to the second input port 5. This optical clock signal is preferably generated by a mode locked laser 8 . The optical clock signal is then split up by a first optical power divider 9i which is part of the optical waveguide 1 1 . In order to simplify the arrangement, the plurality of opto-electronic flip-flops 12i to 12 _N which transform an optical clock signal into an electrical clock signal are not shown within Fig. 3.

The plurality of the delay units 10i to 10 _M are also shown within the layout of Fig. 3. The delay units 10i to 10 _M which are part of the optical waveguide 11 have the shape of a meander. It has to be noted that the corners of the meander of the delay units 10i to 10 _M are illustrated disproportionately. As described below, the meander structure has only round segments which connect the parallel segments to each other. The meander structure thereby increases the light length with respect to the typically straight lines of the optical waveguide 11. It can clearly be seen that the optical clock signal for the first track-and-hold-unit li does not travel through any delay unit 10i to 10 _M . The optical clock signal for the last track-and-hold-unit 7 _N travels through N-l delay units 10i to 10 _M .

If the clock signal has a period of 100 ps each output port is delayed to the respective adjacent output port by 12.5 ps. Because a mode locked laser has a very good jitter performance, the difference between the delay times of each output port is constant.

Fig. 4 shows a simplified layout of the sampling device 2 according to another embodiment of the invention. The interleaving factor N is higher in Fig. 4 compared to the interleaving factor in Fig. 2. The interleaving factor N equals 16 so that there are also 16 track-and-hold-units 7i, 7 ₂ to 7 _N . It can also be seen that an RF-signal is fed to the first input port 4 . The RF-signal is then split into two signal paths, wherein each signal path comprises an amplifier 6 . Each signal path is then further split, so that a part of the RF-signal which is fed to the first input port 4 also applies at the input port of each of the plurality of the track-and-hold-units 7 ι , I ₂ to 7 _N .

Fig. 4 also shows the second input port 5 which is connected through an optical fiber to the mode locked laser 8 . The input port 5 consists of a grating, which couples the incident light into the optical waveguide 11 .

This ensures that as much power of the light pulses as possible can be injected into the optical waveguide 11 .

Other forms which also reduce the power loss of the optical clock signal at the second input port 5 are also suitable .

As already described, the optical waveguide 11 is split by first optical power divider 9i into a first branch and a second branch. As already described a plurality of delay units lOi to 10M are formed within the optical waveguide 11 . Each delay unit lOi to 10 _M is separated from the adjacent delay unit lOi to 10 _M as indicated by a dotted line. The number of the delay units lOi to 10 _M which are arranged within the second branch of the first optical power divider 9i also equals the number of the track-and- hold-units 7 i , I ₂ to 7 _N that are connected as descendants to the respective branch. In this case eight track-and- hold-units 7 i , I ₂ to 7 _N are connected as descendants to the second branch of the first optical power divider 9i. Thus, there are eight delay units inserted within the second branch. The same also applies for example for the second optical power divider 9 ₂ - In this case there are four track-and-hold-units l i , 7 ₂ to 7 _N that are connected to the second branch of the second optical divider 9 ₂ . Therefore, the second branch of the second optical power divider 9 ₂ comprises four delay units 10i to 10 _M . On the other hand, as already mentioned, the first branch of every optical power divider 9i to 9 _N -i does not comprise any delay unit 10i to 10 _M .

Fig. 4 also shows the plurality of the opto-electronic flip-flops 12i to 12 _N . Each of the opto-electronic flip- flops 12i to 12 _N is arranged at an input port of a track- and-hold-units li, 7 ₂ to 7 _N . Each opto-electronic flip-flop 12i to 12 _N transforms an optical clock signal to an electronic clock signal that is fed to the respective track-and-hold-unit li, 7 ₂ to 7 _N . It is also desirable that the optical clock signal has about the same power level at every opto-electronic flip-flop 12i to 12 _N . This goal is achieved by a suitable angle between the first and the second branch of each of the optical power dividers 9i to 9 _N -i with respect to the input port of the optical power divider 9i to 9 _N _i .

Fig. 5A shows a simplified embodiment of the optical power divider 9i to 9 _N -i . It can be seen that the optical power divider 9i to 9N-I has one incoming signal line 50 which is part of the optical waveguide 11. The incoming signal line 50 is split into a first branch 51i and a second branch 51 ₂ . The ratio of the signal power at each branch 51i, 51 ₂ can be selected by adjusting the divergency angle 52i of the first branch and the divergency angle 52 ₂ of the second branch 51 ₂ with respect to the incoming signal line 50 of the optical power divider 9i to 9 _N -i . If the starting point of the first branch 51i and the second branch 51 ₂ is in the middle of the incoming signal line and if both divergency angles are 45°, the optical power divider 9i to 9N-I divide the optical clock signal into two clock signals both having the same signal power level.

Furthermore, a corner 53 which connects the first branch 51i to the second branch 51 ₂ can be slid along the width of the incoming signal line 50 to further adjust the division ratio which allows building optical power

dividers 9i to 9N-I that have a very high division ratio of for example 1:30 or above. Those kind of optical power dividers 9i to 9 _N _i can be used if an asymmetrical tree- structure of the optical waveguide 11 should be realized.

The first branch 51i and the second branch 51 ₂ shown in the embodiment of Fig. 5A have a smaller width than the incoming signal line 50. It should be clear that the first branch 51i and the second branch 51 ₂ can also have a width that equals the width of the incoming signal line 50 or they can have a width that is larger than the one of the incoming signal line 50.

As already mentioned, the incoming signal line 50 as well as the first branch 51i and the second branch 51 ₂ of each optical power divider 9i to 9 _N -i are part of the optical waveguide 11 and are therefore made of a transparent layer of germanium or SiC>2. The optical power divider 9i to 9N-I as well as the whole optical waveguide 11 can easily be structured on a common wafer. Furthermore it is also possible to create an optical power divider that has more than two branches.

Fig. 5B shows an embodiment of a part of an optical waveguide 11 operating as delay unit 10i to 10 _M according to the present invention. Within Fig. 3 and Fig. 4 it is shown that the delay unit 10i to 10 _M is part of the optical waveguide 11 and that this part of the optical waveguide 11 has the shape of a meander. However, the delay units 10i to 10 _M can also have the shape of a spiral, wherein an inner segment 55 of the delay unit 10i to 10M is lead to the outside by using a straight line 56 thereby crossing the other segments 57 i , 572 at an angle of about 90°. An angle of 90° ensures that the delayed clock signal on the straight line 56 does not interfere with the more or less delayed clock signals on the other segments 57 i , 57 ₂ . As already mentioned it has to be assured that no corners are used.

The larger the radius of all parts of the spiral shaped delay units 10i to 10 _M is, the more can the loss of the optical power be reduced.

Fig. 5 C shows another embodiment of an optical waveguide 11 operating as a delay unit 10i to 10 _M according to the present invention. As mentioned above, the delay unit 10i to 10 _M can have the shape of a meander, wherein the delay unit 10i to 10M has segments 60ι, 6 Ο 2 that are parallel to each other and wherein the delay unit lOi to 10 _M has other segments 61 that are round, thereby connecting the

parallel segments 6 O 1 , 6 Ο 2 to each other. The radius of the other segments 61 can be equal to the distance between the two parallel segments 6 O 1 , 6 Ο 2 as shown in Fig. 4.

However, the diameter of the other segments can also be larger than the distance between the two parallel segments 6 O 1 , 6 Ο 2 as shown in Fig. 5 C . If the other segment 61 has a radius that is larger than the distance between the two parallel segments, the optical power loss is further reduced . Fig. 6 shows an embodiment of an opto-electronic flip-flop 12i to 12 _N that can be used as an electronic clock

generator. The opto-electronic flip-flop 12i to 12 _N comprises several transistors 60ι, 6Ο2, 6Ο ₃ , 6Ο4. The emitters of the transistors 6O1, 6Ο2 are connected to a photodiode 61, which, for its part, is connected to a negative supply voltage, which can also be connected to ground. Data inputs D and D are connected to the base terminals of the transistors 6O1, 6Ο2. The collectors of the transistors 6O1, 6Ο2 are each connected by means of a resistor 62i, 62 ₂ to a positive supply voltage.

The photodiode 61 in this circuit is connected in such a manner that only minimal leakage current flows, as long as no light falls on the photodiode 61. As soon as light falls onto the photodiode 61, a photocurrent passes from an n-doped to a p-doped region of the photodiode. The intensity of the photocurrent is, in a good approximation, proportional to the luminous power of the laser pulse.

Fig. 6 shows also a differential pair of transistors 6Ο ₃ , 6Ο4 which form a latch. The base terminals of this

differential pair are connected crosswise to the collector terminals of the transistors 6O1, 6Ο2. That is to say, the base terminal of the transistor 6Ο ₃ is connected to the collector terminal of the transistor 6O1. The base

terminal of the transistor 6Ο4 is connected to the

collector terminal of the transistor 6Ο2. Moreover, the collector terminal of the transistor 6Ο ₃ is connected to the collector terminal of the transistor 6Ο2. The

collector terminal of transistor 6Ο4 is also connected to the collector terminal of transistor 6O1. The emitter terminals of the transistors 6Ο ₃ , 6Ο4 are connected via a current source 63 to a negative supply voltage, which can also be connected to ground. As a result of the crosswise wiring, a positive feedback is generated, and accordingly, the logical status of the latch is maintained. In this context, the zero-signal current of the latch generated by the current source 63 must be significantly smaller than the photocurrent which is generated by the photodiode 61. Only if this condition is fulfilled, can the photocurrent of the photodiode 61 exceeds the zero-signal current of the current source 63 and accordingly varies the logical status of the latch.

The optically controlled D-flip-flop, also called the opto-electronic flip-flop 12i, 12 ₂ to 12 _N , illustrated here can be used for a plurality of applications. In

particular, it is suitable for use in a high-precision clock generator that can be used i.e. within a sampling device 2 according to the present invention. In order to generate an electrical clock signal, of which the clock statuses provide the same length (duty cycle 50%) , a feedback loop has also to be implemented.

Fig. 6 shows also a delaying device 64. The delaying device 64 comprises two transistors 65i, 65 ₂ , a current source 66 and two resistors 67i, 67 ₂ . The two resistors 67i, 67 ₂ are each connected between a positive supply voltage and the collector of one of the transistors 65i, 65 ₂ as load resistors. The emitters of the transistors 65i, 65 ₂ are each connected to the current source 66, which is connected to a negative supply voltage, which can also be connected to ground. The base of the transistor 65i is connected to the base of the transistor 6Ο ₄ . The base of the transistor 65 ₂ is connected to the base of the transistor 6Ο ₃ . Moreover, the collector of the transistor 65i is connected to the base of the transistor 6O ₁ as a feedback. Similarly, the collector of the transistor 65 ₂ is connected to the base of the transistor 6Ο ₂ .

Fig. 7 shows an embodiment of a simplified track-and-hold- unit li, I2 to 7 _N . It can be seen that the simplified track-and-hold-unit 7i, I2 to 7 _N has three input ports. An RF-signal is fed to the first input port 70, wherein a clock signal is fed to a second input port 71, wherein a clock-not-signal is fed to the third input port 72. The first input port of the track-and-hold-unit li to 7 _N is connected to one end of a resistor 73, wherein the other end of the resistor 73 is connected to a supply voltage. Furthermore, the first input port 70 is also connected to a base of a transistor 74 and to a collector of another transistor 75. The collector of the transistor 74 is also connected to the supply voltage. The emitter of the transistor 74 is connected to a collector of a further transistor 76 and to one end of a capacitor 77, wherein the other end of the capacitor 77 is connected to a supply voltage that can be ground for example. The base of the further transistor 76 is connected to the second input port 71 of the simplified track-and-hold-unit li to 7 _N , wherein the base of the other transistor 75 is connected to the third input port 72 of the simplified track-and- hold-unit li to 7 _N . The emitters of the other transistor 75 and the further transistor 76 are connected together and to a current source 79.

However, instead of connecting the third input port 72 of the simplified track-and-hold-unit li to 7 _N to a clock- not-signal, the third input port 72 can also be connected to a constant voltage source, if the voltage is lower than the logic "high" level of the electric clock signal and higher than the logic "low" level of the electrical clock signal, wherein the electrical clock signal is fed to the second input port 71. Otherwise, a clock-not-signal can be input to the third input port 72 too, wherein the clock- not-signal has a phase shift of 180° with respect to the electrical clock signal which is input to the second input port 71.

If the logic level of the electrical clock signal is

"high", the further transistor 76 is in a conducting state. Thus, the capacitor 77 is charged with a part of the RF-signal, wherein the part equals the RF-signal minus the voltage U _BE of the transistor 74. If the logic level of the electrical clock signal is "low" at the second input port 71 of the simplified track-and-hold-unit li to 7 _N , the other transistor 75 is in a conducting state which ensures that the transistor 74 is not in a conducting state. The resistor 73 enhances this effect.

Fig. 8 shows an embodiment of a chip structure carrying the sampling device 2 according to the present invention. The chip comprises a silicon wafer as a ground structure. Furthermore, the optical waveguide 11 comprising the optical power splitters 9i to 9 _N -i and the delay units 10i to 10 _M are arranged on a first part 80i of the wafer. The optical waveguide 11 together with the aforementioned components are made of a layer which is transparent for the respective wavelength of the light source, i.e.

germanium or SiC>2 . It should be mentioned that other materials that can be deposited on a wafer and that have a transparent structure can be used as well for creating the optical waveguide 11.

On the other side the plurality of the track-and-hold- units li to 7 _N and the opto-electronic flip-flops 12i to 12 _N are arranged on a second part 8Ο2 of the wafer. It should be noted that the photodiode 61 within the opto ^¬ electronic flip-flop 12i to 12 _N is preferably arranged at the changeover between the first part 8O1 and the second part 8Ο2 of the wafer. The components of the second part 8Ο2 are preferably made of SiGe. It should be clear that other materials can be used as well if they can be deposited on a wafer and if they are suitable for high ^¬ speed data rates.

Instead of using the optical delay units lOi to 10 _M it is also possible to delay the electrical RF-signal which is input at the first input port 4. This could be done in a limited range by a proper insertion of varactors, for example by insertion of voltage-dependent capacitors.

The invention is not restricted to the exemplary

embodiment presented. All of the features described above or illustrated in the drawings can be advantageously combined with one another as required within the scope of the invention. Other transistors, such as PNP bipolar transistors, NMOS or PMOS transistors or even other FET transistors can be used instead of NPN transistors. Other light sources instead of a mode locked laser can be used, such as stroke lamps, LEDs or other kind of lasers, such as semiconductor lasers. A semiconductor laser might be integrated on the same chip if layers of a III-V- semiconductor, such as InGaAs is applied on the Si- substrate by MBE for example.