Technical field

The present invention relates to the field of wireless communications and in particular to a sampling rate converter data flow control mechanism.

Background Art

A Sampling Rate Converter (SRC) converts a signal from an input sampling rate to an output sampling rate while preserving the signal's quality.

One of the major issues of SRCs is the data flow control, meaning the capability of sustaining data generation on its output at the requested output sampling rate while using the available number of samples available on its input at input sampling rate.

The sampling rate converter data flow control mechanism regulates the data flow of the sampling rate converter so that the sampling rate converter will always be able to provide the requested number of samples on its output starting from a defined number of samples on its input.

Typically, sampling rate converters are generating a defined number of samples on their output starting from a defined number of samples on their input. Their functionality is dependent on the sustainability of a defined exact ratio between the input and output sampling rate.

The typical SRC problem is that the ratio between the output and input sampling rates (sampling rate ratio) is different from the one supported by the SRC due to the limited accuracy of frequency synthesizers. In this case the SRC will start making errors due to either the lack of input samples for generating output samples (in case the actual sampling rate ratio is larger than the SRC supported sampling rate) or to too many input samples that cannot be stored for generating the requested number of output samples (in case the actual sampling rate is lower than the SRC supported sampling rate).

Summary of the invention

It is an object of the present invention to provide a process for regulating the SRC data flow.

It is another object of the present invention to preserve the SRC data flow even if the output sampling rate is being derived from a frequency modulated synthesizer. The invention is about a data flow control mechanism that regulates the SRC data flow so that even if the actual sampling rate ratio is different than the predefined sampling rate ratio, the SRC will preserve its functionality by dynamically adjusting its operation for accommodating the actual sampling rate ratio. The second part of the invention is that the SRC data flow is preserved even in the context of the output sampling rate being derived from a frequency modulated synthesizer, provided that the modulating signal and the modulation index is known.

Those objects are achieved by a sampling rate converter as defined in claim 1 which comprises:

- a circuit for up-sampling the incoming data stream;

- a filter for filtering the up-sampled incoming data stream;

- an interpolation filter for interpolating the filtered up-sampled incoming stream of data;

- a FIFO for storing the interpolated filtered up-sampled incoming stream of data, said storing being performed at said first frequency and the reading of said FIFO being performed at said second frequency so as to output the stored data at a second corresponding rate. The sampling-rate-converter further comprises a control block comprising a numerically controlled oscillator (NCO) used for generating said first frequency, the control of said NCO being based on information representative of the status of said FIFO and also information representative of the modulation of the data.

In one embodiment the information representative of the modulation of the data is derived from the counting, during a predetermined period of the number of quadrants passed by the vector corresponding to the modulation signal. Preferably, the predetermined period corresponds to a set of 50 symbols to be modulated.

The interpolation filter is based either on dynamic or static interpolation. Preferably, the sampling rate converter is based on a linear interpolation filter of a first order, combined with a 4X up-sampling.

The invention also achieves a sampling rate conversion of an incoming stream of data, clocked at a first frequency, and output at a second frequency; said process including the following steps:

- up-sampling the incoming data stream;

- filtering the up-sampled incoming data stream;

- interpolating the filtered up-sampled incoming stream of data;

- storing into a FIFO the interpolated filtered up-sampled incoming stream of data, said storing being performed at said first frequency and the reading of said FIFO being performed at said second frequency so as to output the stored data at a second corresponding rate;

characterized in that it further involves:

- controlling a numerically controlled oscillator (NCO) used for generating said first frequency on the basis of information representative of the status of said FIFO and also information representative of the modulation of the data. In one particular embodiment, the information representative of the modulation of the data is derived from the counting, during a predetermined period of the number of quadrants passed by the vector corresponding to the modulation signal.

The sampling-rate-converter and the process for performing sample rate conversion are particularly adapted for a transmission circuit of a User Equipment for a wireless telecommunication network.

Description of the drawings

Other features of one or more embodiments of the invention will be best understood by reference to the following detailed description when read in conjunction with the accompanying drawings.

Figure 1 illustrates an SRC equipped with the data flow control mechanism

Figure 2a illustrates the transfer function of the interpolation filter.

Figure 2b illustrates the write and read registers of the FIFO 5.

Figure 3 illustrates the four phase decomposition filter used in one embodiment.

Figure 4 illustrates a general overview of the way the NCO controls the interpolation process generating the required number of output samples and the correct values of these samples.. Figure 5 shows a table of values which can be used for correcting the NCO of data flow control block 10 - see the feedback control input.

Figure 6 is a graph representative of the ideal Delta NCO parameter as a function of the sampling rate ratio (Fout is imposed by the selected BT channel: Fout=(2402+BT_channel)MHz; Fin is 24MHz) and the modulation signal behavior (in this case characterized by a 75 quadrants advancement during the period of analysis); see the feed-forward control input in Fig. 1.

Description of the preferred embodiment

With respect to figure 1 , there is illustrated one embodiment of a sample-rate converter for converting a stream of incoming data - generated by a block Data_in 1 - sampled with a first clock CLKJN (generated by block 7) and pass the data without corrupting its integrity while changing the sampling rate.

The SRC converter is particularly intended for a transmitter of a User Equipment, such as a mobile phone, for a wireless telecommunication network.

For that purpose, the incoming data is input into a block 2 which performs an oversampling or more particularly an up-sampling of the incoming data with a predefined factor X. It should be noticed that up-sampling differs from the so-called oversampling by the adding of "0" in the up-sampled stream of data. The output of block 2 is connected to the input of a filtering block 3 and then to an interpolation filter 4 which are used for the purpose of providing an interpolated oversampled stream of data.

As known by the skilled man, the sampling-rate conversation requires interpolation, and a new set of data needs to be generated starting from the original one. Basically, interpolation filter 4 can be based on two mechanisms:

1. dynamic interpolation,

2. static interpolation. The dynamic interpolation mechanism is based on the adjustment of the transfer characteristic of the interpolation filter for each interpolated sample. By doing so, a perfect notch may be realized at the position of the original sampling frequency. The attenuation of the signal's image (around Fsjnput) is one of the major requirements of a sampling rate converter. The complexity of implementing a dynamically self-adjustable interpolation filter makes this approach attractive when large rejections are required and when the use of up-sampling (or up-sampling equivalences) are prohibited. The static interpolation mechanism may also be used but is limited by the fact that in the process of re-sampling, the original signal's image (around Fsjnput) will be aliased on top of the wanted signal. This image may be attenuated by:

1. Increasing the order of the interpolation filter,

2. Increasing the over-sampling factor before applying interpolation of a certain order.

Interpolation filter 4 can be based on one of those two mechanisms or, even, a mix of both techniques for the purpose of achieving an optimal implementation.

In one embodiment, the SRC is based on a linear interpolation filter of a first order, combined with a 4X up-sampling.

A first order interpolation is used preferably than a "0"-order one (re- sampling). Indeed, as justified by the table below, in order to achieve 70dB attenuation of the original sampling frequency images (assuming a sampled signal of 500kHz), an over-sampling rate of 1536 would be necessary and certainly not easy to implement (the over-sampling ratio is referred to the minimum sampling ratio to be used for the 500kHz signal, meaning 1 MS/s).

A similar analysis, for the case of a linear interpolation leads to the following figures:

It appears from the figures above, that a 2X up-sampling combined with a linear interpolation leads to almost 80dB of attenuation of the image signals.

In one particular embodiment, a poly-phase filter, associated with a 4X up- sampling is used. As the original OSR for this example was 24MS/s, the 4X up- sampling leads to an OSR of 96MS/s. The implemented attenuation of the aliased components (around the 96MHz frequency) inherent to linear interpolation is in excess of 91dB - in the table above an additional line should be added:

OSR=96, ATTN@500kHz=0.0007, Attn@OSR(MHz)-500kHz=91.2dB, Attn@OSR(Mhz)+500kHz=91.4dB

The filter used for removing the 24/48/72MHz images is:

[1 3 6 10 12 12 10 6 3 1].

For the sake of illustration, the transfer function of this filter is shown in figure 2a, which shows that the images attenuation levels are in excess of 80dBs: 23.5MHz is equivalent to 23.5/48=0.48958. The attenuation at this freq. is -62dB thus the overall filtering is 36(DC transfer level) +62=98dB. The linear interpolation process performed by block 4 produces the new data raw from the 4X up-samples data. The accuracy of the interpolation is imposed by the number of bits quantifying the position of the interpolated sample with respect to the adjacent samples of the original signal.

The number of bits used for implementing the linear interpolation has been set to 18. With this setting the maximum interpolation error that is performed is 144.44Hz which means that the data generated by interpolation can be calculated on a grid which is maximum 116Hz/-144Hz away from the "wanted" grid. This means that if the SRC is supposed to output 38.578125MS/s while starting from 24MS/S (BT channel 67), it will generate actually 38.57800888MS/S which means it will generate 116.12114 to many samples during one second. This effect is causing "data flow" problems which will be handled by the data flow control block 10 in order to comply with the requested data flow rate which is in the previous example an output of 38.578125MS/s.

In order to limit the sampling frequency, the implementation of the interpolation filter will be based on four-phase decomposition, as illustrated in figure 3, and showing three delay blocks 41 , 42, 43 and four individual blocks 31-34 which respectively processes the incoming sample X(z) and each delayed version of the samples. Each individual block 31 -34 outputs one component Y1 (z), Y2(Z), Y3(Z) and Y4(Z) which can then added by means of an adder 40.

In one particular embodiment the adder 40 can be omitted as there is no need of the actual addition. What is required is the interpolated values between the four equally time spaced outputs Y1(z)..Y4(z). The interpolation process is driven by a NCO (Numerical controlled Oscillator) controlled by an internal constant value NCO CT inside the data flow control block 10 which selects:

1. The number of (output) samples that need to be generated for 1 input frequency period

2. The branch (Y _x -Y _x- i) where the interpolated values lie 3. The actual position within the branch (s).

As seen in figure 1 , the sampling-rate - converter of figure 1 is clocked under the control of a data flow control block 10 including numerically controlled oscillator. Block 10 thus provides the clocking system for all components of the SRC, including up-sampling block 2, filter 3, interpolation filter 4 and also the writing mechanism of FIFO 5. To achieve this, block 10 receives control information monitoring the status of FIFO 5 and also information generated by a block 9 monitoring the ratio of the output and input sampling rates and the modulation of the data. The resulting information is stored into an accumulator (e.g. a 18 bits accumulator) carrying a parameter NCO_CO (NCO constant) used for controlling the rising and falling edges of the clocking.

The embodiment of figure 1 is particularly characterized by the fact that two distinctive control mechanisms are used for controlling the NCO oscillator:

1) a feedback control mechanism based on information representative of the status of the FIFO 5 ;

2) a feed-forward control mechanism based on information representative of the modulation of the data to be transmitted and the ratio between the input and output sample rates;

1) Feedback control mechanism

The so-called feedback control mechanism is based on the measurement of the_difference between the SRC supported data flow and the actual data flow. The feedback control mechanism is based on the monitoring of the FIFO state indicator. The FIFO state indicator is the instrument measuring the difference between the SRC supported data flow and the SRC actual data flow. If the actual data flow is higher than the supported data flow the FIFO will be emptied as the speed of taking samples out of the FIFO is higher than the speed of generating new samples into the FIFO. The FIFO state indicator will signalize this to the data-flow control block 10 which will speed up the process of generating output samples. The opposite will happen if the actual data flow is lower than the supported data flow.

If one considers the BT channel 0 for instance, the input sampling frequency of the SRC is 24MHz. The mean output sampling frequency is 2402 MHz*2.5/20/8=37.53125 M Hz.

The NCO_CT (NCO constant) to be accumulated is set to ROUND(2 ^A 18*24/37.53125)=167632.

Because of the rounding function, the output rate supported will be 24MHz ^* 167632/(2 ^* 18)=37.5313544MHz thus -104.395Hz less than requested.

The timing diagram of figure 4 illustrates a general overview of the way the NCO controls the SRC.

The FIFO block 5 comprises 8 registers and its status is monitored as described below: At start-up the FIFO 5 is written but not read. The difference between the writing pointer and the reading pointer is monitored. As soon as this difference is 4 (half way FIFO) the reading operation is enabled. As the difference (between read and write pointers) gets smaller (indication of the fact that the SRC doesn't produce enough samples) the SRC will be "speed-up" by lowering the NCO_CT by 1 LSB. The opposite happens if the pointer difference increases.

The estimation of the FIFO status takes place on chunks on 50 BT symbols and the NCO_CT is updated in accordance In one embodiment, the feedback of the feedback control mechanism is based on the following table: Mean DELTA_NCO_CT_FIFO

Δ

Pointer

1.5..2 4

2. 2.5 3

2.5..3 2

3 .3.5 1

3.5.A5 0

4.5 .5 -1

5. 5.5 -2

5.5...6 -3

6...6.5 -4

The ideal NCO_CT (used at start-up) may be changed by max. 4 LSB. While 1 LSB leads to a data flow rate change of approx. 6ppm, the max. change inflicted by 5 changing the NCO is quantified to be +/-24ppm.

This type of feedback loop is intended to control data flow issues created by:

1. the limited number of bits employed for the NCO_CT,

i o 2. the error of the 24MHz clock and of the RF synthesized clock.

The limited number of bits used for NCO_CT may lead to max. 3 ppm data flow error (0.5LSB) which are well under the range covered by the proposed algorithm.

15

The 24MHz frequency will be synthesized with 23bits on the fractional section whereas the reference clock will be around 1 MHz, leading to an error in the range of 1 ΜΗζ/2 ^Λ 23 which is equivalent with 0.11 ppm.

20 The RF synthesized frequency error will be less than 1 ppm (locked frequency error will be less than 2.4kHz). Under the assumption of a reference freq. of 52MHz the fractional bus width of the RF PLL needs to be in excess of 16 bits. All cases will be covered by the +/-24ppm range of the proposed mechanism.

Practically, the FIFO indicator used in the feedback control mechanism can be embodied as follows:

On the start of each chunk of 50us during 1024 events of 48MHz (actually implemented as rising and falling edges of the 24MHz) the following is performed: Delta_Pointer=Pointer_Read-Pointer_Write % calculate the pointer delta

Signed_Delta_Pointer=Delta_Pointer-4 for accumulating the error only Accumulate Signed_Delta_Pointer --> Acc_Pointer_Error.

At the end of the 1024 events, the sum is divided by 512 (round to the nearest). With the assumption that on average the delta pointer is 4.511 (500 reads @ 4 and 524 reads 5) the Acc Poiter_Error is expected to be 524. Dividing by 512 leads to l .xxx (less than 1.5) which is interpreted as Error Pointer being between 4.5 and 5, leading to DELTA_NCO CT FIFO being -1. This particular implementation is limiting the assessment of the FIFO position to only 1024/48=21.33us of the 50us chunk but this is not seen as a limitation due to the very slow changing rate of the FIFO indicator.

2) Feed-forward control mechanism

In addition to the described feedback control mechanism, the data flow control block 10 is also controlled by a so-called feed-forward mechanism, which is based on the regulation of the SRC data flow when the SRC actual data flow is controlled in a known manner. An example is regulating the SRC data flow when the SRC output rate (CLK_OUT) is derived from a synthesizer which is frequency modulated. A frequency modulated synthesizer will run faster or slower than the "central frequency" depending on the modulation data and the modulation index. In effect, if the modulating data leads to a higher synthesized frequency than the central one, the SRC output rate will also be higher. A conventional SRC would fail to correctly operate because of the difference between the actual and supported data flows. Thanks to the feed-forward mechanism the SRC data flow controller is used in such a way to adjust the actual data flow using the modulation information, meaning that by knowing that a synthesizer will be asked to run faster, the output data rate will be increased and so will the SRC actual data flow. The opposite happens if due to modulation information the synthesized frequency will be lower.

Practically, the feed-forward mechanism monitors the data modulation process - and thus the data flow rate resulting from the modulated data (due to its impact on the DPLL derived clock) and correspondingly adjusts the NCO_CT parameter controlling the Numerically Controller Oscillator of block 10.

In one embodiment, the modulated data is analyzed during a period corresponding to a set of 50 symbols being transmitted. Over such a period the number of quadrants passed by the vector (clock - anticlock -wise) is calculated and the corresponding parameter - the mean modulating frequency over 50 symbols - is used for adjusting the NCO_CT digital parameter controlling the Numerically Controlled Oscillator of block 10. It should be noticed that the adjusted NCO_CT at time Tk is representative for the previous 50us period but it is applied for the next 50 symbols. This will in effect lead to some signal distortion. However, simulations have indicated that while keeping the update rate at 50us, the distortion inflicted on the signal is negligible (DEVM <-40dB). Simulations have also indicated that while processing PRBS data we may not need this correction, as the FIFO state is stable due to the random properties of the signal. This control loop is however built-in for safety reasons. In addition it is necessary for supporting test modes where-in the signal is not PRBS but "all 1" or "all 0" in GFSK or continuous jumps of a certain angle in PSK modes. Practically, in one embodiment, the feed-forward correction mechanism is implemented as follows:

Consider the case of continuous jumps of 135 °. The number of quadrants covered during 50us is 75 which is equivalent with a modulation frequency of 375kHz. The ideal NCO_CT supporting the new DCO frequency is calculated to be within the 25..26 units range depending on the BT channel, as shown in the figure 6.

Therefore, in the embodiment being considered, the following calculation is applied for computing the DELTA_NCO_CT_MOD, being the constant to be applied for compensating the modulation impact is:

D E LTA N C O_CT_M O D = 44 ^* Nr_Quadr/128 for BT Channel 0:31

DELTA NCO CT MOD = 43*Nr_Quadr/128 for BT Channel 32:60

DELTA NCO CT MOD = 42*Nr_Quadr/128 for BT Channel 61 :78

The division by 128 has to be implemented using rounding to the nearest.

Each of the two DELTA NCO CT will be applied to the NCO_CT values depending on the settings of two enable signals:

ENABLE NCO CT FIFO ENABLE NCO CT MOD

Every 50us the NCO_CT_ACTUAL is updated as

NCO_CT_ACTUAL=NCO_CT

+ENABLE_NCO_CT_FIFO*DELTA_NCO_CT_FIFO

+ ENABLE_NCO_CT_MOD*DELTA_NCO_CT_MOD

3) Data flow errors assessment

Both dataflow algorithms are targeting the ... dataflow. This section assesses the FIFO activity during a regular packet without using these algorithms. The longest packet to be supported in a real BT link is DH5 thus less than

3ms.

The NCO_CT quantization is less than 3ppm. The 24MHz and RF LO freq. errors are assessed to be less than 2ppm.

First calculation doesn't take into account the impact of modulation. Taking all other mechanisms mentioned above into account leads to very worse case 5ppm dataflow error. A dataflow error of 5ppm means that during 1 second, instead of generating

38MS (case of the BT channel 30) will generate 38 ^* 1.000005=38.00019MS/s which means 190 additional samples during 1s which converts to 0.57 samples during 3ms. Having only 0.57 additional/less samples during a slot doesn't require the use of the FIFO control mechanism.

First conclusion: the other mechanism, taking into account the impact of the modulation contents over the data flow is highly dependent on the modulation content. During BT regular operating mode the FIFO control may be switched OFF: ENABLE_NCO_CT_FIFO=0.

Simulations have shown that due to the PRBS nature of the signal the FIFO is very stable - doesn't change state during several simulated ms.

Second conclusion: for actual BT packets this mechanism can be switched off as well. ENABLE NCO CT MOD = 0

Actual signals have whatever characteristics. In order to "randomize" them they are passed through a "whitening" sequence. This sequence is specified in the BT specification as being the D7 + D4 + 1 polynomial.

The length of this polynomial is 127 symbols. Based on its start-up sequence (seed) it may produce "all 1s" on its output if driven with a particular sequence (that can be generated easily by applying "all 1s" on its input. In this case a sequence of 127 "1s" will be generated. In order to continue this sequence the incoming signal needs to repeat itself. Theoretically it is possible to have "all 1s" even after whitening but it is impossible to have this for two consecutive packets because the seed of the whitening sequence changes for each slot so if a packet is lost due to this very unlikely behavior, data will be whitened during the next one when resend using a new seed.

Nevertheless, there exists a tiny chance that a packet even after whitening will generate a repetitive code that will lead to a significant mean frequency drift over the 3ms. The brute force method is to increase the FIFO length to +/-19 samples - this will cover the worst case for 3ms or enable the modulation compensation. The +/-19 samples FIFO is roughly estimated to cost about 0.01 mm2. The alternative is to implement +/-4 samples FIFO and keep the modulation compensation algorithm ON during normal BT operation. It has been described how to achieve effective sampling rate conversion by taking advantageous effect of the two feedback control and feedforward control mechanisms.

The advantage of the feed-back SRC data flow control mechanism is that it allows the SRC to function without errors in the presence of small variations of the sampling rate ratio. When the sampling rate ratio is not perfectly controlled the lack of such a mechanism leads to errors inside the SRC which inflict a degradation of the signal quality.

Small variations of the sampling rate ratio are common to systems which employ two different synthesizers controlling the input and the output data rates of the SRC.

The advantage of the feed-forward SRC data flow control mechanism is that it allows the SRC to function without errors in case the data flow varies in a known way. A typical case is the use of such a SRC in a chain where the output sampling rate is derived from a modulated synthesizer, like in the case of Polar transmitter architectures.