Technical Field

[0001] The present disclosure relates generally to analog-to-digital converters (ADCs) and, more particularly, to systems and methods for performing Successive-approximation-register (SAR) ADC in a wireless sensor node device.

Background

[0002] In battery-powered electronic devices, power dissipation is an important

consideration; power dissipation affects both battery life and device heat levels. Further, wireless sensor devices often include analog-to-digital converters (ADCs) for digitizing sensor outputs and it becomes important to reduce the power dissipation of each ADC to reduce the overall power consumption of the device. In the last decade, the SAR (Successive- approximation-register) ADC has become popular due to its low power dissipation and scalability with finer process geometries.

[0003] Typically, sensor readout systems measure when the sensor output crosses a certain threshold level. This is generally done by digitizing the sensor output and performing a comparison in the digital domain. However, even when using SAR ADC technology, this still consumes appreciable power.

[0004] The present disclosure is directed to addressing one or more deficiencies and/or disadvantages, e.g., as set forth above or otherwise. However, it should be appreciated that the solution of any particular problem is not a limitation on the scope of this disclosure or of the attached claims except to the extent expressly noted. Moreover, this Background section reflects the inventors' thoughts and is not intended to accurately or completely reflect any particular prior art. As such, Applicants expressly disclaim this material as admitted prior art.

Summary of the Disclosure

[0005] In one aspect of the disclosed principles, a method of analog-to-digital conversion is implemented in a sensor circuit with an input of V _IN and having an ADC with a capacitor array comprising a plurality of capacitors connected through a respective plurality of switches, a comparator, an SAR module and a multiplexer (MUX) connecting the SAR module to the DAC. The method includes executing a track phase when a sample clock signal CK_SMP is low by applying an input voltage V _IN over all capacitors in the capacitor array of the ADC. A sampling phase is then executed on a subsequent CK_SMP by opening the respective plurality of switches such that a sample of V _IN is stored over the capacitor array of the ADC. In a subsequent comparison phase, the MUX is set to select an n-bit threshold value D _THRE S _HOLD . _O which is applied to the ADC capacitor array, connecting all switches Si, where i is in the range from 0 to n-1 , which receive 1, to a reference voltage V _REF and connecting the remaining switches to a common mode voltage V _CM such that the output VP of the ADC reaches a value equal to the input voltage V _IN subtracted from the analog of D _THRE S _HOLD . _O , and completing the comparison to V _CM by the comparator at the comparator clock CK, such that if VP > V _CM , then DP is 1 and the sample of V _IN is larger than

D _THRE S _HOLD .O, and otherwise, if VP < V _CM , then DP is 0 and the sample of V _I N is smaller than D _THRE S _HOLD . _O - Another threshold value D _THRE S _HOLD J is selected, where j is in the range from 1 to M, and the comparison phase is repeated until all M threshold values have been compared. After any comparison between Vm and D _t hresholds , and as a consequence of the comparison, a full SAR conversion can be carried out to obtain a full resolution quantization of the input voltage. [0006] In another embodiment, a sensor system is provided including a processor configured to execute a method of analog-to-digital conversion in a sensor circuit with an input of V _IN and having an ADC with a capacitor array comprising a plurality of capacitors connected through a respective plurality of switches (collectively a DAC), a comparator, an SAR module and a multiplexer (MUX) connecting the DAC to the SAR module. The processor executes the method by executing a track phase when a sample clock signal CK_SMP is low by applying an input voltage V _IN over all capacitors in the capacitor array of the ADC. The processor then executes a sampling phase on a subsequent rising edge of CK_SMP by opening the respective plurality of switches such that a sample of V _IN is stored over the capacitor array of the ADC. Finally, a comparison phase is executed by setting the MUX to select an n-bit threshold value D _JHRE S _HOLD . _O which is applied to the ADC capacitor array, connecting all switches Si, where i is in the range from 0 to n-1 , to a reference voltage V _REF and connecting the remaining switches to a common mode voltage V _CM such that the output VP of the DAC reaches a value equal to the input voltage V _IN subtracted from the analog of D _JHRE S _HOLD . _O. The comparison to V _CM is completed at the rising edge of the comparator clock CK, such that if VP > V _CM , then DP is 1 and the sample of V _IN is larger than D _THRE S _HOLD .O, and otherwise, if VP < V _CM , then DP is 0 and the sample of V _I N is smaller than D _JHRE S _HOLD . _O - Another threshold value D _JHRE S _HOLD J is selected, where j is in the range from 1 to M, and the comparison phase is repeated until all M threshold values have been compared. After any comparison between Vm and D _t h _re shoid _, i , and as a consequence of the comparison, a full SAR conversion can be carried out to obtain a full resolution quantization of the input voltage.

[0007] In accordance with yet another embodiment, a sensor circuit is provided for executing analog-to-digital conversion of a sensed value V _IN - The sensor circuit includes an ADC having a capacitor array comprising a plurality of capacitors connected through a respective plurality of switches (collectively a DAC), a comparator, an SAR module, a MUX connecting the DAC to the SAR module, and a controller. The controller is configured to execute a track phase when a sample clock signal CK_SMP is low by applying an input voltage V _IN over all capacitors in the capacitor array of the ADC, and to execute a sampling phase on a subsequent rising edge of CK_SMP by opening the respective plurality of switches such that a sample of V _IN is stored over the capacitor array of the ADC. A comparison phase is executed by setting the MUX to select an n-bit threshold value

D _THRE S _HOLD . _O which is applied to the ADC capacitor array, connecting all switches S„ where i is in the range from 0 to n-1 , to a reference voltage V _REF, and connecting the remaining switches to a common mode voltage V _CM - In this way, the output VP of the DAC reaches a value equal to the input voltage V _IN subtracted from the analog of D _THRE S _HOLD . _O , and the comparison to V _CM is completed by the comparator at the rising edge of the comparator clock CK. If VP > V _CM , then DP is 1 and the sample of V _IN is larger than D _JHRE S _HOLD . _O , whereas otherwise, if VP < V _CM , then DP is 0 and the sample of V _IN is smaller than D _JHRE S _HOLD . _O - Another threshold value D _THRE S _HOLD j is selected, where j is in the range from 1 to , and the comparison phase is repeated until all M threshold values have been compared. After any comparison between Vj„ and D _t h _re shoid _, i , and as a consequence of the comparison, a full SAR conversion can be carried out to obtain a full resolution quantization of the input voltage.

[0008] These and other aspects and features will be more readily understood when reading the following detailed description in conjunction with the accompanying drawings.

Brief Description of the Drawings

[0009] Figure 1 is a schematic drawing of an implementation of an SAR ADC;

[0010] Figure 2 is an indexed signal plot showing example signal values during operation of the SAR ADC of Figure 1 ;

[0011] Figure 3 is a schematic drawing of an implementation of an SAR ADC in accordance with an embodiment of the disclosed principles; [0012] Figure 4 is an indexed signal plot showing example signal values during operation of the SAR ADC of Figure 3; and

[0013] Figure 5 is a flow chart showing an ADC process in accordance with an

embodiment of the disclosed principles.

[0014] While the following detailed description is given with respect to certain illustrative embodiments, it is to be understood that such embodiments are not to be construed as limiting, but rather the present disclosure is entitled to a scope of protection consistent with all embodiments, modifications, alternative constructions, and equivalents thereto.

Detailed Description

[0015] Before turning to a detailed discussion of the figures, a brief overview of certain disclosed features and principles will be given to aid the reader. As noted above, the ADC is often an integral part of sensor circuits, and the SAR ADC is increasingly used in this application. However, ADCs, including SAR ADCs, can consume or dissipate a significant amount of electrical power, and any energy savings in the SAR ADC will inure to the benefit of the device user in terms of lower heat and longer battery life. As such, in an embodiment of the disclosed principles, a threshold trigger functionality for reduced power consumption

[0016] Referring to Fig. 1, this figure shows a simplified schematic representation of an SAR ADC. For simplicity the figure shows a single-ended system, while many

implementations may be differential in order to resist noise in the circuit. While the illustrated circuit is a principal implementation of a SAR ADC, there exist a range of different implementations and the principles presented herein can be applied to any implementations that are based on charge conservation in the ADC. [0017] The illustrated circuit 100 includes a DAC 101, a comparator 103, and an SAR 105. The circuit modes of operation include a track phase, a sampling phase and a conversion phase. In the tracking phase, CK_SMP is low, SIN and SCM are closed (conducting) and the input voltage VIN is, applied over all capacitors in the capacitor array of the DAC. In the sampling phase, on rising edge of CK_SMP, the switches ¾v and SCM open, and a sample of Vi _N is stored over the capacitor array of the DAC.

[0018] In the conversion phase, a number of steps are executed. The SAR algorithm starts by connecting the MSB switch S _n -i to VREF while the rest of the switches S _N -2-So are connected to VCM- This is done by setting the MSB bit of the SAR[]-bus to 1 and the rest of the bits to 0. The comparator COMP 103 is now clocked by the rising edge of CK and the voltage VP is compared to the common mode voltage VCM. If VP > VCM then DP is set to 1 and MSB in the SAR[]-bus is maintained 1. If VP < V _C M then DP is set to 0 and MSB in the SAR[]-bus is set to 0.

[0019] The MSB- 1 bit in the SAR[]-bus is set and the procedure above is repeated until bit 0 of the SAR[]-bus is evaluated and set accordingly. The result is now made available at the ADC digital output D _out .

[0020] The indexed signal plot of Figure 2 shows the signal values in an example during the foregoing phases.

[0021] In case of threshold comparison, the output word D _out can now be compared to one or more threshold values in the digital domain. The power dissipation for such an ADC is strongly dependent on the number of clock cycles of CK, which is equal to number of bits in D _out . Additional power is consumed during the comparison to the threshold values in the digital domain.

[0022] In an embodiment of the disclosed principles, the comparison to the digital threshold values is executed directly in the analog domain, without resolving the output word D _out . This means that the number of comparisons, and thus the numbers of required periods of CK, equals number of threshold values instead of equaling the number of bits in the resolved output word. In this way, power is saved in the analog domain as well as in the digital domain.

[0023] A simplified schematic of an SAR DAC in accordance with an embodiment of the disclosed principles is shown in Figure 3. The only addition to the figure above is the MUX that can select between the ordinary output of the SAR or one of M+l threshold values DTHRESHOLD.O to DTHRESHOLDM _* ^eacn given as an n-bit digital word. The selection is done by the digital signal SEL. When the circuit is operated as an ordinary SAR ADC, the MUX selects the output the SAR as the input to the capacitor DAC, and goes through the number of cycles necessary to resolve the n-bit output word D _OUT . The procedure for resolving the n- bit output word is as explained above.

[0024] As noted above, the comparison of values to one of the digital threshold values can be executed in three phases, e.g., a track phase, a sampling phase and a comparison stage. During the track phase, CK_SMP is low, ¾v and S _CM are closed (conducting) and the input voltage V _IN is, applied over all capacitors in the capacitor array of the DAC. During the sampling phase, S _IN and S _CM open on the rising edge of CK_SMP, and a sample of V _IN is stored over the capacitor array of the DAC.

[0025] Finally, in the comparison phase, SEL is set such that the MUX selects the n-bit threshold value D _THRE S _HOLD . _O which is applied to the DAC capacitor array. All switches S„ where i is in the range from 0 to n-1 , which receive 1 connect to VREF. The remaining switches connect to V _CM - The value of VP will reach a value equal to the input voltage V _IN subtracted from the analog version of D _THRE S _HOLD . _O - The comparison to VCM is now done at the rising edge of CK by the comparator COMP.

[0026] If VP > V _CM , then DP is set to 1 and the sample of V _I N is larger than D _THRE S _HOLD .O- On the other hand, if VP < V _CM , then DP is set to 0 and the sample of V _IN is smaller than D _THRE S _HOLD . _O. The follow-up action can now be taken. [0027] Since the charge stored at the capacitors in the DAC capacitor array is conserved, a new comparison to one of the other D _JHRE S _HOLD J, where j is in the range from 1 to , can be performed by changing SEL such that new threshold value is selected for the next comparison occurring at the next rising edge of CK.

[0028] After any number of D _JHRE S _HOLD J comparisons, a full SAR conversion can be carried out on the same input sample. This can be done as a result of one of the threshold conversions. For example, if the sampled V¾v has crossed a threshold level, a full resolution digital value of the sample may be required.

[0029] Figure 4 shows the input voltage V _m , the comparator COMP input voltage Vp, and the waveforms of CK_SMP, CK and DP. First V _IN is sampled at the rising edge of CK_SMP. Then D _THRE S _HOLD, o is chosen and compared at the first rising edge of CK (denoted 1). The comparison result on DP is 0 since the sampled V _IN is less than the equivalent analog value of D _THRE S _HOLD - Further, D _THRE S _HOLD .O ^ ^' applied to the DAC, and the comparison is carried out at the 2nd rising edge of CK, denoted 2. DP becomes 1 since the sample of V _tN is larger than the equivalent analog value of D _THRE S _HOLD, I- On the 3rd rising edge of CK (denoted 3), a full SAR conversion is started and after n additional clock cycles of CK, the n-bit word Dour is ready at the ADC output.

[0030] To facilitate ultra-long battery life in sensor systems, power must be conserved. To this end, power-efficient sensor readout circuits are beneficial. The described principles conserve power by executing the threshold comparison in the analog domain and by requiring fewer conversion cycles for a full SAR conversion. Executing the threshold comparison directly in the analog domain saves both digital circuitry and electric power versus executing the comparison digitally.

[0031] In an embodiment of the disclosed principles, the input voltage V _IN is sampled, and the sample is compared to a pre-defined digital threshold value D _JHRE S _HOLD M- The result DP of the comparison is used as an input to a sensor baseline tracking algorithm, tracking low speed changes due to environment parameters other than the parameter the sensor system is intended to monitor, which is assumed to be high speed.

[0032] The baseline algorithm can force a full SAR conversion, on the same sample of the input voltage Vm, due to the value of DP obtained in this comparison and/or together with previous comparisons between D _THRE S _HOLD . _O to previous samples of the voltage Vm- The digital threshold value D _THRE S _HOLD S is then updated in accordance with a baseline algorithm and previous results of comparison between previous samples of Vm, and/or full SAR conversions.

[0033] In another embodiment of the described principles, a 2nd comparison of the same sample of Vm is made to a 2nd pre-defined digital threshold D _THRE S _HOLD, I and the result DP of the comparison is then used as a threshold trigger for further actions. Such actions could be, for example, a full SAR conversion of the same sample of Vm, to obtain a full resolution quantization of the sensor output, or other actions to other part of the system. In a further embodiment, the value of D _THRE S _HOLD, I is used as an offset D _0FF S _ET, I away from the baseline threshold D _THRESHO LD,O and D _THRESHO LD,I may be updated with D OFFSET,! + DTHRESHOLD.O when the baseline tracking algorithm updates D _THRE S _HOLD .O-

[0034] In another embodiment of the described principles, a 3rd comparison is performed of the same sample of Vm to a 3rd pre-defined digital threshold value D _THRE S _HOLD, 2 and the result DP is applied as a threshold trigger to further actions, e.g., a full SAR conversion of the same sample of VIN to obtain a full resolution of the sensor output or other actions to other parts of the system. Similar to the above embodiment, the value of D _THRE S _HOLD, 2 could be an offset D _OF FSET,2 {D ₀ FFSET,2≠ D _OF FSET,I) away from the baseline threshold D _TH RESHOLD,O, and D _THRE S _HOLD ,2 may be updated with D _0FF S _ET ,2 + D _THRE S _HOLD ,O when the baseline tracking algorithm updates DTHRESHOLD.O-

[0035] The processes described herein may be executed by controlling a circuit such as that shown in the figures, via a processor or controller executing computer-executable instructions read from a non-transitory computer-readable medium. Those of skill in the art will appreciate that many computer-readable medium exist, including optical and magnetic memory media, flash memory media, and so on.

[0036] Although the steps of such a method may be executed in various ways, Figure 5 is a flow chart showing exemplary steps in an illustrative embodiment. The process 500 begins at stage 501 of the illustrated process 500, when a sample clock signal CK_SMP goes low. A track phase then begins at stage 503 by applying an input voltage V _IN over all capacitors in the capacitor array of the ADC. At stage 505, a subsequent rising edge of CK_SMP is detected and a sampling phase is executed at stage 507 by opening the switches such that a sample of V _IN is stored over the capacitor array of the ADC.

[0037] A comparison phase is then begun at stage 509 by setting the MUX to select an n- bit threshold value D _THRE S _HOLD . _I for any i from 0 to M, which is applied to the ADC capacitor array. All switches Si, where i is in the range from 0 to n-1 , which receive T from the D _THRE S _HOLD word, are connected to reference voltage V _REF ^ stage 511 and the remaining switches are connected to a common mode voltage V _CM at stage 513. In this way, the output VP of the ADC reaches a value equal to the input voltage V _IN subtracted from the analog of D _THRE S _HOLD . _O - The comparison to V _CM by the comparator is then completed at stage 515 upon the rising edge of the comparator clock input CK, such that if VP > V _CM , then DP is 1 and the sample of V _IN is larger than D _THRE S _HOLD . _O , and otherwise, if VP < V _CM , then DP is 0 and the sample of V _IN is smaller than D _THRE S _HOLD . _O - If the comparison result reaches the trigger threshold at stage 517, a full SAR conversion is executed at stage 519, yielding the ADC output word Dout- Otherwise, another threshold value D _THRE S _HOLD J, is selected, where j is in the range from 1 to M, and the comparison phase is repeated until all M threshold values have been compared. After any comparison between Vm and D _t h _re shoid _, i , and as a consequence of the comparison, a full SAR conversion can be carried out to obtain a full resolution quantization of the input voltage. [0038] From the foregoing, it will be appreciated that while only certain embodiments have been set forth for the purposes of illustration, alternatives and modifications will be apparent from the above description to those skilled in the art. These and other alternatives are considered equivalents and within the spirit and scope of this disclosure and the appended claims.