CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit under 35 U.S.C. §119 of U.S. Provisional Patent Application No. 63/328,880 filed on April 8, 2022, which is hereby incorporated by reference herein in its entirety.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH

[0002] This invention was made with government support under FA8702-15-D-0001 awarded by the U.S. Air Force, and under W91 INF-18-1-0116 awarded by the Army Research Office. The government has certain rights in the invention.

BACKGROUND

[0003] Quantum computing has revolutionary potential. There are classes of computational problems related to chemistry, medicine, optimization, and machine learning that are intractable to even the most powerful modern supercomputers, but which can be solved exponentially faster using quantum hardware. While there have been recent demonstrations of small-scale quantum computers, contemporary devices are restricted in their performance due to high error rates and limited prospects for scalability.

[0004] Various modalities may be used for quantum computing, including photonic, atomic, and solid-state systems. Solid-state qubits, such as those formed by an electron spin or a superconducting circuit, have transition frequencies in the GHz range. Because their frequencies are in this range, they are compatible with commercial-off-the-shelf (COTS) RF and microwave components. Solid-state qubits have the further advantage that they leverage decades of investment in fabrication by the semiconductor industry.

Although convenient from the point of view of using COTS equipment, operation in the few-GHz range introduces the need for cooling the devices to avoid the qubit being inadvertently excited from “0” to “1” due to thermal effects.

[0005] The two primary types of superconducting qubits are the flux qubit and the charge qubit. With a charge qubit, the charging energy of its Josephson junctions dominates the coupling energy. In a Flux qubit, the situation is reversed, and the coupling energy dominates.

SUMMARY

[0006] Contemporary quantum hardware uses qubits with relatively high frequency /oi, typically around 5 GHz, such that the corresponding energy is much larger than the equivalent kT thermal energy scale at dilution refrigerator temperatures around T=20 mK. Operating in this limit can ensure that thermally induced excited-state population is small. Control is then generally performed by resonant (/ _O i) microwave pulses.

[0007] Here, as illustrated in FIG. 1A, the rotation of a qubit’s state 100 can be controlled by the amplitude of the applied microwave pulse 102. FIG. IB shows an example of a circuit (e.g., a superconducting circuit that may be on a 2D or 3D chip) in which this technique may be used to control the state of a qubit. Illustrative circuit 120 includes a flux qubit 122 and a flux bias line 124 inductively coupled thereto by inductors 126. Flux qubit 122 can include a terminal 128 for coupling to readout circuitry (not shown). A microwave pulse can be applied to a flux bias line 124 and, by way of the inductive coupling, can cause the state of flux qubit 122 to rotate/change. More generally, and depending on qubit type and bias point, a microwave pulse can be applied to either a charge or a flux bias line, which will couple either capacitively or inductively.

[0008] While such techniques have successfully demonstrated error rates as low as 0.1%, the approach suffer from a number of shortcomings related to amplitude noise, control complexity, high thermal load, and high cost/qubit. In addition, the driver/control electronics are generally held at room temperature, and the signals are brought to the qubit via wiring, such as coaxial cables. Further, since conventional Rabi driving must be implemented at a rate much smaller than f ₀₁ to avoid the impact of counter-rotating imperfections in the control, resonant driving of so-called “protected qubits” with small gaps becomes unreasonably slow and ameliorates their protected coherence advantage (the coherence times are longer, but so are the gate operations).

[0009] Contemporary quantum hardware uses one or more control and readout wires per qubit. In this “brute-force scaling era,” the standard approach is to increase the numbers of qubits from 10 to 100 and even to 1000 using this approach of one or more control and readout wires per qubit. However, while this may be viewed as extensible, it is recognized here that is not scalable (other than by simple linear extension). The bruteforce approach will ultimately be limited by the number of wires one can practically bring down to a chip or set of chips. One may contrast this with existing transistor chips, for which there are billions of transistors on the chip, yet only tens to hundreds of control wires coming to the chip.

[0010] There exist control technologies that operate at cryogenic temperatures, including cryogenic CMOS and single-flux quantum (SFQ) logic (a superconducting digital logic family). It is recognized here that these must be collocated with qubit chips at dilution refrigerator temperatures to leverage integration of the driver/control electronics with the qubit chips, in order to reduce the wire count. Maintaining cryogenic electronics at higher temperature stages is possible, but the run from that stage to the chip then requires a high wiring overhead. However, collocation of the cryogenic electronics presents a heating problem. If one takes the room temperature electronics and reproduces it at cryogenic temperatures, cryogenic CMOS would dissipate far too much power for today’s or even envisioned future dilution refrigerators. Single-flux quantum (SFQ) schemes - although less energy per op than cryogenic CMOS - would also struggle to maintain sufficiently low power for convention control of conventional qubits. In both cases, it reduces to the activity factor - namely, how many times is a logic element switching and dissipating power when implementing a control pulse.

[0011] Described herein are structures and techniques for implementing single-qubit and two-qubit control using collocated electronics - either SFQ or cryogenic CMOS - that circumvents the problems listed above. It is applicable to both the “brute-force scaling era” as well as for an era of scalability. The techniques described here may be applied to any type of quantum computer where the qubit’s longitudinal energy scale can be tuned by an external control parameter.

[0012] According to one aspect of the present disclosure, a system for performing quantum computations can include: a first environment for being maintained at an ambient temperature, having a classical computing processor; and a second environment for being maintained at a cryogenic temperature, having a plurality of qubits and a multiplexing circuit coupled to the plurality of qubits, each of the plurality of qubits having a gap transition frequency. The classical computing processor can be configured to change a state of each of the plurality of qubits by controlling the multiplexing circuit to couple particular ones of the plurality of qubits to a pulsed baseband waveform.

[0013] In some embodiments, the pulsed baseband waveform can include a non- adiabatic waveform that is not resonant with respect to the gap transition frequency of the particular ones of the plurality of qubits. In some embodiments, the multiplexing circuit may include a plurality of switches arranged in a binary tree structure. In some embodiments, the pulsed baseband waveform can include a first pulse having a first duration and a positive amplitude, and a second pulse having a second duration and a negative amplitude. In some embodiments, the first pulse, the second pulse, or both may be square pulses.

[0014] In some embodiments, the system can also include a driver circuit to generate the pulsed baseband waveform. In some embodiments, the driver circuit may be located within the first environment for being maintained at an ambient temperature. In some embodiments, the driver circuit may be located within the second environment for being maintained at a cryogenic temperature. In some embodiments, the driver circuit can be implemented using cryogenic CMOS or single-flux quantum (SFQ) logic.

[0015] In some embodiments, the multiplexer circuit can be located within the second environment for being maintained at a cryogenic temperature. In some embodiments, the multiplexer circuit can be implemented using cryogenic CMOS or single-flux quantum (SFQ) logic. In some embodiments, the multiplexer circuit may be collocated on the same chip as one or more of the plurality of qubits. In some embodiments, the multiplexer circuit can be bump bonded or wafer bonded to the plurality of qubits. In some embodiments, the multiplexer circuit may be connected to each of the plurality of qubits via chip-level interconnects.

[0016] According to another aspect of the present disclosure, a quantum computing system includes: a classical computing processor; a quantum processing unit (QPU) having a plurality of qubits; and means for controlling particular ones of the plurality of qubits to a pulsed baseband waveform responsive to commands received form the classical computing processor. [0017] It is appreciated that the concepts, techniques, and structures disclosed herein may be embodied in other ways, and that the above summary of disclosed embodiments is thus meant to be illustrative rather than comprehensive or limiting. In particular, individual elements of different embodiments described herein may be combined to form other embodiments not specifically set forth above. Various elements, which are described in the context of a single embodiment, also may be provided in other embodiments separately, or in any suitable sub-combination. Moreover, other embodiments not specifically described herein also may be within the scope of the claims set forth below.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The manner of making and using the disclosed subject matter may be appreciated by reference to the detailed description in connection with the drawings, in which like reference numerals identify like elements.

[0019] FIG. 1 A illustrates qubit control using resonant microwave pulses.

[0020] FIG. IB is a circuit diagram showing a flux qubit with readout and control, the flux qubit being controllable using the technique of FIG. 1 A.

[0021] FIG. 2A shows a technique for controlling a flux qubit using baseband pulsing, according to embodiments of the present disclosure.

[0022] FIG. 2B is a circuit diagram of a flux qubit controllable using baseband pulsing, according to some embodiments.

[0023] FIG. 2C shows a technique for controlling a charge qubit using baseband pulsing, according to embodiments of the present disclosure.

[0024] FIG. 2D is a circuit diagram of a charge qubit controllable using baseband pulsing, according to some embodiments.

[0025] FIG. 3 is a block diagram of a quantum computing system having a plurality of qubits controllable using baseband pulsing, according to some embodiments. [0026] FIG. 4A is a block diagram of a quantum computing system in which control electronics are collocated with a quantum processing unit (QPU) at cryogenic temperature, according to some embodiments.

[0027] FIG. 4B is a block diagram of a quantum computing system in which a portion of the control electronics are at cryogenic temperature and another portion of the control electronics are at higher temperature, according to some embodiments.

[0028] FIG. 4C is a block diagram of a quantum computing system in which a QPU is at cryogenic temperature and control electronics are at higher temperature, according to some embodiments.

[0029] FIG. 5 is a circuit diagram showing illustrative circuitry that can be used to generate a pulsed baseband waveform, according to some embodiments.

[0030] FIG. 6 is a circuit diagram showing an example of a multiplexing circuit that can be provided within embodiments of the present disclosure.

[0031] The drawings are not necessarily to scale, or inclusive of all elements of a system, emphasis instead generally being placed upon illustrating the concepts, structures, and techniques sought to be protected herein.

DETAILED DESCRIPTION

[0032] Embodiments of the present disclosure can provide qubit control using baseband pulsing. In more detail, single-qubit and two-qubit gates can be controlled using baseband pulses and nonadiabatic control. The control scheme relies on the size of the qubit avoided crossing and the timing of an approximately square baseband pulse applied to the qubit. Single qubit rotations and two-qubit gates may then be realized through “Landau-Zener interferometry” and quantum interference. While embodiments of the present disclosure are described in terms of superconducting qubit systems, the general concepts sought to be protected herein may also be applied to any type of system that features an avoided crossing, including but not limited to semiconducting qubit systems and naturally occurring atomic, molecular, or defect qubit systems. Avoided crossings may appear in single qubit systems and coupled qubit systems. [0033] Referring to FIG. 2 A, a first plot 200 illustrates a qubit avoided crossing, with horizontal axis 204 representing magnetic flux or current amplitude (A) and a vertical axis 206 representing qubit frequency or energy. A second plot 202 shares horizontal axis 204 and has a vertical axis 208 representing time.

[0034] To induce a transition between the qubit states (e.g., from |0) to |1) or vice versa), a waveform 210 having approximately square baseband pulses may be applied to a qubit (e.g., to a flux or charge superconducting qubit). The waveform 210 can include three segments, as shown in the figure and as follows. The first segment consists of waiting for a time t ₀ at amplitude A = 0, the idling point for the qubit. In the second segment, to initiate a gate operation, the amplitude is set to A = for a time t _± . In the third segment, to complete the gate, the amplitude is set to A = — zl ₂ for a time t ₂ . Finally, the waveform 210 is returned to the idling configuration with amplitude A = 0.

[0035] The parameters A _t , zl ₂ , t ₀ , t ₁₅ and t ₂ can be selected to define arbitrary rotations of the single- or two-qubit state. For the scheme to work, the slew rate of the amplitude A between the three segments must be faster than l/ ₀₁ , which is the minimum frequency gap 212 in FIG. 2 A. Unlike in the Rabi-driving case, where gate speeds must be much less than l/ ₀₁ to avoid counter-rotating pollution of the operation, the gate speed for the disclosed non-adiabatic control is only limited to 1/ _O i- The quantum interference needed to achieve the gate operation is controlled by an interference phase that accrues during the gates. It can be tuned by either the amplitudes A or /1 ₂ , by the duration in times t ₀ , t ₁₅ or t ₂ , or a combination thereof. For example, in some embodiments, arbitrary control can be implemented with just the three parameters t ₀ , _o = = zl ₂ , and G = t ₂ .

[0036] The pulsed baseband waveform 210 may be realized as a baseband signal that is selectively applied to control a flux qubit, such as the flux qubit of FIG. 2B. In the example of FIG. 2 A, waveform 210 may represent a current signal and, thus, A and d ₂ may correspond to current levels.

[0037] The advantages of the disclosed qubit control scheme include at least the following. First, this scheme may lead to better precision and lower susceptibility to instrumentation noise, since it is easier to precisely control the timing rather than the amplitude of the control pulses. In addition, the disclosed technique removes the need for costly, pulsed microwave sources, and it makes it possible control multiple qubits through a single control line (or a number of control lines less than the number of qubits being controlled) by using a network of switches. Next, the system has very low activity factor: only 3 amplitude settings need occur to realize this pulse scheme (off, positive, and negative). Also, the source of the signal may be either room temperature electronics, cryogenic (but not collocated electronics), or collocated electronics to the qubit. The low activity factor enables the use of collocated electronics, particular for low-power variants of SFQ logic, such us adiabatic quantum flux parametrons (AQFP). And embodiments enable the use of low-frequency “protected qubits” such as fluxonium or the 0-pi qubit, which have small gaps.

[0038] FIG. 2B shows an example of a flux qubit 220 that can be controlled using baseband pulsing, according to some embodiments. A pulse baseband waveform, such as waveform 210 of FIG. 2 A, can be applied to a flux bias line 222 and, by way of inductive coupling 224, can cause the state of flux qubit 220 to rotate/change. In more detail, a signal applied to flux bias line 222 may, at selected times, be generated to include two approximately square baseband pulses of opposite current to cause the state of qubit 220 to change. At other times, the applied signal may have substantially zero current such that the current qubit state is maintained.

[0039] Turning to FIG. 2C, a pulsed baseband waveform can be generated as a voltage signal for controlling a charge qubit, according to some embodiments. Like elements of FIG. 2A and 2C are showing using like reference numerals. A first plot 240 illustrates a qubit avoided crossing and a second plot 242 illustrates the pulsed baseband waveform. In this case, shared horizontal axis 244 represents charge or voltage. A waveform 246 may be generated as a baseband signal that is applied to control a charge qubit, such as the charge qubit of FIG. 2D. In the example of FIG. 2C, waveform 246 may be realized as a voltage signal and, thus, and A ₂ may correspond to voltage levels.

[0040] FIG. 2D shows an example of a charge qubit 260 that can be controlled using baseband pulsing, according to some embodiments. A pulsed baseband waveform, such as waveform 246 of FIG. 2C, can be applied to a terminal 262 (V _g ) that is coupled to the charge qubit via capacitor 264 (C _g ), as shown, causing the state of charge qubit 260 to rotate/change. In more detail, a signal applied to terminal 262 may, at selected times, be generated to include two approximately square baseband pulses of opposite voltage to cause the state of qubit 260 to change. At other times, the applied signal may have substantially zero voltage such that the current qubit state is maintained.

[0041] FIG. 3 shows a quantum computing system having a plurality of qubits controlled using baseband pulsing, according to some embodiments. Illustrative system 300 includes a driver circuit 302 electrically coupled to a multiplexing circuit 304 via one or more interface lines 306 (e.g., wires), and a plurality of qubits 308a, 308b, ..., 308n (308 generally) electrically coupled to multiplexing circuit 304 via respective ones of a plurality of control lines 310a, 310b, ..., 310n (310 generally, e.g., wires or chip-level interconnects). Qubits 308 can generally be provided as any type of qubit featuring an avoided crossing, including but not limited to superconducting, semiconducting, and naturally occurring qubits. For example, one or more of the qubits 308 can be the same as or similar to the flux qubit of FIG. 2B or the charge qubit of FIG. 2D.

[0042] Driver circuit 302 is configured to generate a pulse signal that has a repeating pulsed baseband waveform similar to that illustrated in FIG. 2A or FIG. 2C. The pulses can correspond to changes in voltage or current, depending on the type of qubits 308. The generated pulse signal can be provided to multiplexing circuit 304 via one of the interface lines 306. In some embodiments, driver circuit 302 may include one or more switches controlled using a timing signal generated by a classical computer according to the parameters t ₀ , t ₁₅ or t ₂ . In some embodiments, driver circuit 302 may include circuitry identical or similar to that described below in the context of FIG. 5. In some cases, driver circuit 302 may be collocated with qubits 308 as discussed further below in the context of FIG. 4A. In this case, driver circuit 302 may generate control pulses as charge/flux pulses that are selectively applied to individual or pairs of qubits 308 to control their state.

[0043] Multiplexing circuit 304 is configured receive the pulse signal from driver circuit 302 view one of the via interface lines 306 and, based thereon, to generate control signals on one or more of the plurality of control lines 310 to control the state of particular qubits 308. In more detail, to rotate the state of a particular qubit 308 (or pair of qubits) at a given time, multiplexing circuit 304 can cause the pulse signal to be passed from driver circuit 302 to that qubit/pair. At other times, multiplexing circuit 304 may apply zero current/voltage to that qubit/pair such that it maintains its current state. In some embodiments, multiplexing circuit 304 may comprise a plurality of switches connected to, and controllable by, one or more of the interface lines 306. In some embodiments, the switches arranged in a binary tree structure having N layers, with each layer connected to, and controllable by, one of the interface lines 306. In this arrangement, N interface lines 306 may be used to control 2 ^N of the qubits 308. In some embodiments, a single interface line 306 may be used to control multiple switching layers, or even all N switching layers. For example, an N-bit binary value may be communicated over single line/wire (e.g., using a digital serial protocol) to indicate which of the N layers of switches should be turned on/off In some embodiments, a single interface line 306 may be used to control all of the N layers. In some cases, multiplexing circuit 304 can include circuitry identical or similar to that described below in the context of FIG. 6.

[0044] Various components of system 300 may be collocated (e.g., on a single chip or other type of integrated device) or physical separated. For example, driver circuit 302 and multiplexing circuit 304 may be collocated with qubits 308 (meaning that, in the case of superconducting qubits, circuits 302, 304 are maintained a cryogenic temperature, made possible the disclosed baseband pulsing schema). As another example, driver circuit 302 and/or multiplexing circuit 304 may be physical separate from qubits 308. FIGS. 4A-4C show possible implementations of system 300 and, more generally, implementations of the disclosed baseband pulsing control techniques.

[0045] In some embodiments, driver circuit 302 and/or multiplexing circuit 304 can be implemented using cryogenic CMOS or SFG technologies. For example, cryogenic CMOS may be used as the multiplexing or switching elements to implement the nonadiabatic control. This may be used in any of the modes listed above. This approach is particularly useful for qubit modalities where the nonadiabatic pulse is a shift in electric charge or voltage. Cryogenic CMOS may be used to generate the voltages (i.e., within driver circuit 302 to generate the pulse signal) or it may be used solely as a multiplexing switch (e.g., within multiplexing circuit 304). As another example, SFQ logic may be used to implement the disclosed electronics. In particular, the low-power variants of SFQ, such as adiabatic quantum flux parametrons (AQFP), may be used with ultra-low power dissipation. This is particularly relevant for qubit modalities where the nonadiabatic pulse implements a shift in magnetic flux or current. SFQ may be used to generate the magnetic field (e.g., using a flux DAC within driver circuit 302) or it may be used solely as the multiplexing switch (e.g., within multiplexing circuit 304).

[0046] One advantage to the disclosed qubit control scheme is that only three settings may be required (i.e., t ₀ , = fl-L = A ₂ , and G ⁼ ) and so the activity factor of active devices is much lower than for resonant driving schemes, which generally require not only deep logic, but also deep memory.

[0047] FIGS. 4A-4C show different embodiments of a quantum computing system in which the disclosed baseband pulse control techniques can be implemented. The systems include a first environment for being maintained at an ambient temperature, having a classical computing processor (denoted “CPU” in the figures), and a second environment for being maintained at a cryogenic temperature, having a quantum processing unit (QPU) with a plurality of qubits. Control electronics may be located entirely within the first environment, entirely within the second environment, or split between these environments using a hybrid approach. The CPU may be configured to execute one or more computer programs for programming/controlling qubits of the QPU by sending control/signals commands to a multiplexer.

[0048] FIG. 4A shows a quantum computing system in which control electronics are collocated with a quantum processing unit (QPU) at cryogenic temperature, according to some embodiments. Illustrative system 400 includes an integrated device 402 comprising control electronics collocated with a QPU having a plurality of qubits, such as qubits 308 of FIG. 3. The collocated control electronics can include, for example, driver circuit 302 and multiplexing circuit 304 of FIG. 3. Here, the driver circuit and/or multiplexing circuit may be implemented on chip using cryogenic CMOS or SFQ technologies. In some cases, driver circuit and/or multiplexing circuit may be bump bonded or wafer bonded to the plurality of qubits. Integrated device 402 can be maintained at cryogenic temperature within a dilution refrigerator 406. System 400 can also include a central processing unit (CPU) 404 located outside the dilution refrigerator 406 and connected to the integrated device 402 via one or more interface lines 408. Interface lines 408 may be the same as or similar to interface lines 306 of FIG. 3. In this embodiment, control lines 310 of FIG. 3 may be formed within integrated device 402, for example, using scalable chip-level interconnects. [0049] FIG. 4B shows a hybrid implementation, wherein a portion of the control electronics are maintained at cryogenic temperature and another portion are at higher temperature (e.g., room temperature). Illustrative system 420 includes a multiplexing circuit 422 and a QPU 424 located within a dilution refrigerator 426 and connected together via a plurality of control lines 428. Here, multiplexing circuit 422 can be implemented on a chip (separate from QPU 424), using cryogenic CMOS or SFQ, for example. A driver circuit can be located outside the dilution refrigerator 426 along with CPU 430 and connected to multiplexing circuit 422 via one or more interface lines 432. In other embodiments, the driver circuit may be located within dilution refrigerator 426 but at higher temperature relative to multiplexing circuit 422 and/or QPU 424. In any case, interface lines 432 may include a line for carrying a pulse signal generated by driver electronics and one or more lines for carrying signals to control switches within multiplexing circuit 422. In some cases, a single interface line 432 may be used to control multiple switches or all switches of multiplexing circuit 422, as previously discussed.

[0050] FIG. 4C shows a quantum computing system in which a QPU is at cryogenic temperature and all control electronics are at higher temperature (e.g., room temperature). Illustrative system 440 includes QPU 442 located within dilution refrigerator 444 and electronics 446 located outside the dilution refrigerator 444 and connected to QPU 442 via a plurality of control lines 448 (e.g., one or more wires per qubit). Here, the generating of the pulse signal and multiplexing may be performed at higher temperature (e.g., room temperature). Control lines 448 can carry, at selected times, pulsed baseband control signals to individual or pairs of qubits within the QPU 442. This can be contrasted with existing systems where such per-qubit control lines (e.g., coaxial cables) are used to carry microwave pulses.

[0051] FIG. 5 shows circuitry that can be used to generate a pulse signal comprising approximately square pulses, according to some embodiments. Illustrative circuit 500 includes a switching element 502 configured to receive a bias current/voltage 504 and to output a pulse signal (or “switching waveform”) 506 responsive to the bias current/voltage 504 and to a timing signal 508. The bias current/voltage 504 and timing signal 508 may be generated externally (e.g., by a classical computer) according to the selected parameters t ₀ , t _r , t ₂ , A ₁₇ and ?1 ₂ . For example, in the case where d ₀ = = ,4 ₂ , the bias current/voltage 504 may be generated to have a fixed current/voltage d ₀ and timing signal 508 may include ticks/pulses at intervals t ₀ , t ₁₅ and t ₂ causing switch to alternate between three states: off, positive, and negative. In the off state, switching element 502 outputs zero current/voltage. In the positive state, switching element 502 outputs d ₀ . In the negative state, switching element 502 outputs — d ₀ . Thus, a pulsed baseband waveform similar to that shown in FIGS. 2A or 2C can be generated using circuit 500. Various other circuits and devices may be used to generate pulsed baseband waveforms according to the present disclosure.

[0052] FIG. 6 shows an example of a multiplexing circuit that can be provided within embodiments of the present disclosure. Illustrative circuit 600 includes an input line 602, a plurality of switches 604a, 604b, 604c, etc. (604 generally), and a plurality of outputs lines 606a, 606b, 606c, etc. (606 generally). Switches 604 may be arranged in a binary tree structure having N layers 608a, 608b, ..., 608n (608 generally), as shown. In this arrangement, circuit 600 can provide 2 ^N separate output lines 606, each of which can be connected to an individual qubit or pair of qubits.

[0053] All switches in a given layer 608 may be controlled using a common switch control signal applied via a common control line. For example, switch 604a in layer 608a may be connected to one control line, whereas both switches 604b, 604c in layer 608b may be connected to different control line. In some embodiments, these control lines may correspond to separate interface lines (e.g., separate interface lines 432 of FIG. 4B). In other embodiments, multiplexing circuit 600 may use a single interface line to control multiple layers 608 of switches or even all layers of switches. For example, circuit 600 may include digital circuitry to convert N-bit binary values received via a single interface line (e.g., using a digital serial protocol) into N control signals applied to respective ones of the N layers 608 of switches.

[0054] In operation, a pulse signal (i.e., a current/voltage signal having a pulsed baseband waveform disclosed herein) can be applied to input line 602 and switches 604 can be controlled to selectively output the pulse signal on a particular one of the output lines 606 (while outputting zero current/voltage on other output lines). For example, to control a qubit connected to first output line 606a, switches 604a, 604b, 604d, and 604e may be switched an “on” position. As shown, this routes the pulse signal from input 602 to first output line 606a. [0055] Various other circuits and devices may be used to route a pulse signal to particular ones of a plurality of qubits. For clarity, not all switches and output lines are labeled in FIG. 6. Also not shown are the per-layer switch control lines.

[0056] As used herein, the terms “processor” and “controller” are used to describe electronic circuitry that performs a function, an operation, or a sequence of operations. The function, operation, or sequence of operations can be hard coded into the electronic circuit or soft coded by way of instructions held in a memory device. The function, operation, or sequence of operations can be performed using digital values or using analog signals. In some embodiments, the processor or controller can be embodied in an application specific integrated circuit (ASIC), which can be an analog ASIC or a digital ASIC, in a microprocessor with associated program memory and/or in a discrete electronic circuit, which can be analog or digital. A processor or controller can contain internal processors or modules that perform portions of the function, operation, or sequence of operations. Similarly, a module can contain internal processors or internal modules that perform portions of the function, operation, or sequence of operations of the module.

[0057] As used herein, the term “predetermined,” when referring to a value or signal, is used to refer to a value or signal that is set, or fixed, in the factory at the time of manufacture, or by external means, e.g., programming, thereafter. As used herein, the term “determined,” when referring to a value or signal, is used to refer to a value or signal that is identified by a circuit during operation, after manufacture.

[0058] As used herein, the terms “processor” and “controller” are used to describe electronic circuitry that performs a function, an operation, or a sequence of operations. The function, operation, or sequence of operations can be hard coded into the electronic circuit or soft coded by way of instructions held in a memory device. The function, operation, or sequence of operations can be performed using digital values or using analog signals. In some embodiments, the processor or controller can be embodied in an application specific integrated circuit (ASIC), which can be an analog ASIC or a digital ASIC, in a microprocessor with associated program memory and/or in a discrete electronic circuit, which can be analog or digital. A processor or controller can contain internal processors or modules that perform portions of the function, operation, or sequence of operations. Similarly, a module can contain internal processors or internal modules that perform portions of the function, operation, or sequence of operations of the module.

[0059] As used herein, the term “predetermined,” when referring to a value or signal, is used to refer to a value or signal that is set, or fixed, in the factory at the time of manufacture, or by external means, e.g., programming, thereafter. As used herein, the term “determined,” when referring to a value or signal, is used to refer to a value or signal that is identified by a circuit during operation, after manufacture.

[0060] While electronic circuits shown in figures herein may be shown in the form of analog blocks or digital blocks, it will be understood that the analog blocks can be replaced by digital blocks that perform the same or similar functions and the digital blocks can be replaced by analog blocks that perform the same or similar functions. Analog-to- digital or digital-to-analog conversions may not be explicitly shown in the figures but should be understood.

[0061] In the foregoing detailed description, various features are grouped together in one or more individual embodiments for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that each claim requires more features than are expressly recited therein. Rather, inventive aspects may lie in less than all features of each disclosed embodiment.

[0062] References in the disclosure to “one embodiment,” “an embodiment,” “some embodiments,” or variants of such phrases indicate that the embodiment s) described can include a particular feature, structure, or characteristic, but every embodiment can include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment s). Further, when a particular feature, structure, or characteristic is described in connection knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

[0063] As used herein, "including" means including without limitation. As used herein, the terms "a" and "an", when modifying a noun, do not imply that only one of the noun exists. As used herein, unless the context clearly indicates otherwise, "or" means and/or. For example, A or B is true if A is true, or B is true, or both A and B are true. As used herein, "for example", "for instance", "e.g.", and "such as" refer to non-limiting examples that are not exclusive examples. The word “consists” (and variants thereof) are to be give the same meaning as the word “comprises” or “includes” (or variants thereof).

[0064] Use of ordinal terms such as “first,” “second,” “third,” etc., in the specification to modify an element does not by itself connote any priority, precedence, or order of one element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one element having a certain name from another element having a same name (but for use of the ordinal term) to distinguish the elements.

[0065] The disclosed subject matter is not limited in its application to the details of construction and to the arrangements of the components set forth in the following description or illustrated in the drawings. The disclosed subject matter is capable of other embodiments and of being practiced and carried out in various ways. As such, those skilled in the art will appreciate that the conception, upon which this disclosure is based, may readily be utilized as a basis for the designing of other structures, methods, and systems for carrying out the several purposes of the disclosed subject matter. Therefore, the claims should be regarded as including such equivalent constructions insofar as they do not depart from the spirit and scope of the disclosed subject matter.

[0066] Although the disclosed subject matter has been described and illustrated in the foregoing exemplary embodiments, it is understood that the present disclosure has been made only by way of example, and that numerous changes in the details of implementation of the disclosed subject matter may be made without departing from the spirit and scope of the disclosed subject matter.

[0067] All publications and references cited herein are expressly incorporated herein by reference in their entirety.