Title:
SCALABLE ELECTRICALLY ERASEABLE AND PROGRAMMABLE MEMORY
Document Type and Number:
WIPO Patent Application WO2008030796
Kind Code:
B1
Abstract:
A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor, a second non-volatile memory transistor and a source access transistor. The source access transistor includes: a first source region continuous with a source region of the first non-volatile memory transistor; a second source region continuous with a source region of the second non-volatile memory transistor, and a drain region that extends downward through a first well region to contact a second well region. The first, second and third semiconductor regions and the second well region have a first conductivity type, and the first well region has a second conductivity type, opposite the first conductivity type.
Inventors:
GEORGESCU SORIN S (US)
COSMIN PETER (US)
SMARANDOIU GEORGE (US)
COSMIN PETER (US)
SMARANDOIU GEORGE (US)
Application Number:
PCT/US2007/077514
Publication Date:
June 12, 2008
Filing Date:
September 04, 2007
Export Citation:
Assignee:
CATALYST SEMICONDUCTOR INC (US)
GEORGESCU SORIN S (US)
COSMIN PETER (US)
SMARANDOIU GEORGE (US)
GEORGESCU SORIN S (US)
COSMIN PETER (US)
SMARANDOIU GEORGE (US)
International Classes:
H01L29/788
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