Title:
SCALAR HARDWARE FOR PERFORMING SIMD OPERATIONS
Document Type and Number:
WIPO Patent Application WO2000022512
Kind Code:
A9
Abstract:
A system (100) for processing SIMD operands (260(a), 260(b)) in a packed data format (250) includes a scalar FMAC (140) and a vector FMAC (130) coupled to a register file through an operand delivery module (120). For vector operations, the operand delivery module (120) bit steers a SIMD Operand (260(a), 260(b)) of the packed operand (250) into an unpacked operand (200) for processing by the first execution unit (140). Another SIMD operand (260(a), 260(b)) is processed by the vector execution unit (130).
Inventors:
MAKINENI SIVAKUMAR (US)
KIMN SUNNHYUK (US)
DOSHI GAUTAM B (US)
GOLLIVER ROGER A (US)
KIMN SUNNHYUK (US)
DOSHI GAUTAM B (US)
GOLLIVER ROGER A (US)
Application Number:
PCT/US1999/023600
Publication Date:
September 21, 2000
Filing Date:
October 08, 1999
Export Citation:
Assignee:
INTEL CORP (US)
MAKINENI SIVAKUMAR (US)
KIMN SUNNHYUK (US)
DOSHI GAUTAM B (US)
GOLLIVER ROGER A (US)
MAKINENI SIVAKUMAR (US)
KIMN SUNNHYUK (US)
DOSHI GAUTAM B (US)
GOLLIVER ROGER A (US)
International Classes:
G06F9/302; G06F9/38; (IPC1-7): G06F9/302; G06F17/16
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