Title:
SCAN SIGNAL LINE DRIVING CIRCUIT AND DISPLAY DEVICE PROVIDED THEREWITH
Document Type and Number:
WIPO Patent Application WO/2018/163897
Kind Code:
A1
Abstract:
The present invention has the purpose of implementing a gate driver (scan signal line driving circuit) which is capable of sufficiently securing a charging time with low power consumption. A reset signal (R) is provided to a control terminal of a thin film transistor (T02) for turning off a gate output, wherein a voltage level of the reset signal becomes a voltage level (Vgh2) of a high-level voltage of a gate clock signal (GCK), when the thin film transistor (T02) is to be turned on. Here, "a difference between the voltage level (Vgh2) of the high-level voltage of the gate clock signal (GCK) and a voltage level (Vg1) of a low-level voltage of the gate clock signal (GCK)" is made larger than "a difference between a voltage level (Vgh) of a DC power supply voltage (VDD) (given to a gate bus line (GL) being in a selection state) and the voltage level (Vg1) of the low-level voltage of the gate clock signal (GCK)".
Inventors:
IWASE YASUAKI
WATANABE TAKUYA
TAGAWA AKIRA
TAKEUCHI YOHEI
WATANABE TAKUYA
TAGAWA AKIRA
TAKEUCHI YOHEI
Application Number:
PCT/JP2018/007111
Publication Date:
September 13, 2018
Filing Date:
February 27, 2018
Export Citation:
Assignee:
SHARP KK (JP)
International Classes:
G09G3/36; G02F1/133; G09G3/20
Domestic Patent References:
| WO2011114569A1 | 2011-09-22 | |||
| WO2013125405A1 | 2013-08-29 | |||
| WO2009084267A1 | 2009-07-09 | |||
| WO2011162057A1 | 2011-12-29 | |||
| WO2013160941A1 | 2013-10-31 |
Foreign References:
| JP2011204343A | 2011-10-13 | |||
| US20160140922A1 | 2016-05-19 |
Attorney, Agent or Firm:
SHIMADA, Akihiro et al. (JP)
Download PDF:
Previous Patent: SOLID-STATE IMAGING DEVICE, AND CAMERA SYSTEM USING SAME
Next Patent: FREE VIEWPOINT MOVEMENT DISPLAY DEVICE
Next Patent: FREE VIEWPOINT MOVEMENT DISPLAY DEVICE