FIELD OF THE INVENTION The present invention relates to the field of electrical integrated circuit testing.

More particularly, the present invention relates to a system and method that facilitates manipulation of logic values during scan operations, that remain constant during normal operations.

BACKGROUND OF THE INVENTION Electronic systems and circuits have made a significant contribution towards the advancement of modern society and are utilized in a number of applications to achieve advantageous results. Numerous electronic technologies such as digital computers, calculators, audio devices, video equipment, and telephone systems have facilitated increased productivity and reduced costs in analyzing and communicating data, ideas and trends in most areas of business, science, education and entertainment. Usually the components or devices of an electronic system are tested to ensure the electronic system operates properly in order for the desired results to be realized. Digital electronic system testing procedures usually involve the manipulation of logic values applied to the components or devices of the electronic system. Frequently, digital electronic systems include logic gates tied to a particular logic value during normal operations. Manipulation of the normally constant logic values usually provides greater testing flexibility but it is typically very difficult to manipulate constant logic values.

The complexity of commonly used integrated circuits (IC) included in system- on-chip (SOC) designs has advanced dramatically and built in self test (BIST) diagnostics capability is essential for effective circuit testing, debugging, and maintenance. Modern BIST techniques typically include the insertion of a scan test architecture in an IC. Scan testing of complex electronic systems and circuits often includes the application of test vectors to stimulate certain aspects of a circuit (e. g., a functional logic component) and observation of the resulting output from the circuit. Usually, scan test architectures include scan test chains comprising scan test components or devices (e. g., scan test cells) coupled together. The scan test elements communicate test vectors to components of an IC and

interact with functional logic utilized to perform non-test or normal operations of the IC.

Typically, scan test cells are designed to scan or shift scan test information (e. g., test vectors) via the scan test chain to appropriate locations in a circuit, capture scan test information and then shift the information out via scan test cells.

Usually it is desirable to have significant scan test coverage, the greater the test coverage the greater the capacity of a scan test system and method to detect faults.

Boundary scan testing is a very common method of scan testing included in typical BIST schemes. International Electrical and Electronic Engineering (IEEE) Standard 1149. 1 (also referred to as Joint Task Action Group (JTAG)) boundary scan compliant architecture is one of the most prevalent boundary scan test schemes. It is also very important to have internal scan test capabilities to provide greater scan test coverage.

Typically, scan test participation by logic gates tied to a particular logic value is relatively limited. A traditional logic gate input tied to a particular logic value does not usually permit desired testing activities in which the tied input is manipulated by testing procedures. It can also block the scan testing of other logic components connected to it.

SUMMARY OF THE INVENTION What is required is a system and method that facilitates scan test manipulation of logic values tied to the input of logic gates and ensure the logic value the gate input is tied to remains constant during normal operations. Scan testing of integrated circuit components with an ATPG tool should be supported and the system and method should accommodate utilization of existing scan testing architectures.

The present invention is a system and method that facilitates scan test manipulation of logic values input to combinational logic (e. g., a logic gate) and ensures that the logic value v the combinational logic input is tied to remain constant during normal operations. In one embodiment of the present invention, scan testing of integrated circuit components with an ATPG tool is supported and the system and method accommodates utilization of existing scan testing architectures. In one embodiment the present invention is a constant logic value manipulation scan test chain that includes a combinational circuit, a constant logic value scan test manipulation circuit, and a scan test element. The combinational circuit performs functional operations during normal mode. The constant logic value scan test manipulation circuit provides a logic value output that remains constant during normal operations and changes in accordance with scan test input information during scan test operations. The scan test element communicates test vectors to functional

components and interacts with functional logic utilized to perform normal operations. In one exemplary implementation of the present invention the combinational circuit is a logic gate and the logic value output by the constant logic value scan test manipulation circuit is coupled to an input of the logic gate. The logic value input to the logic gate remains constant during normal operations and is manipulated in accordance with scan test input information during scan test operations.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram a traditional IC that includes logic gates tied to a particular logical input value.

Fig. 2 is a block diagram illustration of a constant logic value manipulation scan test chain, one embodiment of the present invention.

Fig. 3 is a block diagram of a constant logic value scan test manipulation circuit, one embodiment of the present invention.

Fig. 4 is a block diagram of a logic value production circuit include in one embodiment of a present invention logic value production circuit.

Fig. 5 is a block diagram illustrating one embodiment of a present invention scan test controllable tied gate input system.

Fig. 6 is a block diagram illustrating an embodiment of a present invention scan test controllable tied gate input system that provides granular control of logic values.

DETAILED DESCRIPTION OF THE INVENTION Reference will now be made in detail to the preferred embodiments of the invention, a scan test system and method for manipulating logic values that remain constant during normal operations, examples of which are illustrated in the accompanying drawings.

While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the scope of the invention as defined by the appended claims.

Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention.

However, it will be obvious to one ordinarily skilled in the art that the present invention may be practiced without these specific details. In other instances, well known methods,

procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the current invention.

One embodiment of the present invention includes a constant logic value scan test manipulation system and method. In one embodiment of the present invention, a constant logic value scan test manipulation system and method is compatible with normal scan testing methodologies. During testing operations the constant logic value scan test manipulation system and method permits manipulation of a logic value output tied to combinational logic inputs. During normal operations the constant logic value scan test manipulation system and method provides a constant logic value output. In one exemplary implementation of the present invention, the constant logic value scan test manipulation system and method is conFig. d in a manner that is compatible with a scan test architecture familiar to the ATPG tool and easily accessible by the ATPG tool.

Fig. 1 is a block diagram of a traditional IC 100, one example of a traditional IC that includes logic gates tied to a particular logical input value. Design circuit blocks 130, 140,140,170 include a logic gate circuit 181 through 184 respectively, each of which comprise one or more logic circuit gates. For example, design circuit block 130 includes AND gate 190. Gate input 192 and gate output 193 are coupled to other gates (not shown) in design circuit block 130. Gate input 191 is tied to logical 0 value source 110. Scan test input port 121 and scan test output port 122 are connected via scan test chain 128 to scan test flip flops 131,132 ; 141,142; 151,152; 171,172 included in design circuit block 130,140,150, 170 respectively. Gate inputs of logic gates included in logic gate circuit 181 through 184 are tied to logical 0 value source 110 or logical 1 value source 115 and are not manipulated during scan test operations by scan test vectors.

Fig. 2 is a block diagram illustration of constant logic value manipulation scan test chain 200, one embodiment of the present invention. Constant logic value manipulation scan test chain 200 comprises constant logic value scan test manipulation circuit 221, scan test element 225 and scan test element 227. Constant logic value scan test manipulation circuit 221 is coupled to scan test element 225 which is coupled to scan test element 227.

Constant logic value scan test manipulation circuit 221 provides a logic value output e. g., logic value output 233 or logic value output 235 that remains constant during normal operations and changes in accordance with scan test input information (e. g., a scan test vector) during scan test operations. Scan test elements 225 and 227 communicate test vectors e. g., scan test input signal 215 to functional components of an IC (not shown) and interact with functional logic utilized to perform non-test or normal operations of the IC. For

example, scan test elements 225 and 227 include scan test cells that scan or shift scan test information (e. g., test vectors) via the scan test chain to a normal function circuit, capture scan test information and then shift the information out e. g., scan test output signal 217.

In one embodiment of the present invention, scan test mode signal 210 directs the components of constant logic value manipulation scan test chain 200 to operate in normal function mode or scan test mode. When scan test mode signal 210 directs the components of constant logic value manipulation scan test chain 200 to operate in normal operation mode, constant logic value scan test manipulation circuit 221 maintains a logic value output e. g., logic value output 233 or logic value output 235 at a constant logic value. When scan test mode signal 210 directs the components of constant logic value manipulation scan test chain 200 to operate in scan test mode, constant logic value scan test manipulation circuit 221 manipulates the logic value output in accordance with scan test input signal 215.

In one exemplary implementation of the present invention, constant logic value scan test manipulation circuit 221 maintains or manipulates logic value output 233 and logic value output 235. When scan test input signal 215 is a logical 0 constant logic value scan test manipulation circuit 221 manipulates logic value output 233 to be a logic 0 value and logic value output 235 to be a logic 1 value. When scan test input signal 215 is a logical 1 value constant logic value scan test manipulation circuit 221 manipulates logic value output 233 to be a logic 1 value and logic value output 235 to be a logic 0 value. When operating in normal function mode, constant logic value scan test manipulation circuit 221 provides constant logic values on logic value output 233 and logic value output 235 that do not change, regardless of the value of scan test input signal 215. Logic value output 233 and logic value output 235 are coupled to the inputs of normal function combinational logic circuits (e. g., logic gate circuits not shown).

Fig. 3 is a block diagram of constant logic value scan test manipulation circuit 300, one embodiment of the present invention. Constant logic value scan test manipulation circuit 300 comprises scan flop 301, logic value production circuit 302, scan test mode input 303, scan test input 304, scan test output 305, logic value output 307 and logic value output 308. Scan flop 301 is coupled to scan test input 304, scan test output 305, and logic value production circuit 302 which is coupled to scan test mode input 303, logic value output 307 and logic value output 308. Scan-flop 301 stores a scan test input logic value communicated by scan test input 304. Scan test output 305 communicates a scan test output signal from scan flop 301. Logic value production circuit 302 ensures logic values communicated on logic value output 307 and 308 remain constant during normal operation mode and provides

manipulation of the logic value during scan test operation mode based upon the scan test input logic value stored in scan flop 301. Scan test mode input 303 communicates a scan test mode signal that directs logic value production circuit 302 when to operate in scan test operation mode and when to operate in normal operation mode. Logic value output 307 and 308 communicate logic values which are coupled (e. g., tied) to other devices (not shown).

Scan test mode signal 303 operates as a controlling signal for constant logic value scan test manipulation circuit 300. Scan test mode signal 303 is asserted (e. g., logic 1) during scan test operations. When scan test mode signal 303 is asserted the first logic value output and the second logic value are controlled by the logic value stored in scan flop 301.

When scan test mode signal 303 is de-asserted the logic value stored in scan-flop 301 does not impact the first logic value output and the second logic value output. In one exemplary implementation of the present invention, the first logic value output is a constant logical 0 value and the second logic value output is a constant logical 1 value during normal operations, irrespective of the logical value stored in scan-flop 301. During scan test operations, the first logic value output is a logical 0 value and the second logic value is a logical 1 if the logical value stored in scan-flop 301 is a logical 0 value. The first logic value output is a logical 1 value and the second logic value is a logical 0 value if the logical value stored in scan-flop 301 is a logical 1 when test mode signal 303 is asserted (e. g., during scan test operations).

Fig. 4 is a block diagram of logic value production circuit 400, one embodiment of logic value production circuit 302. Logic value production circuit 400 comprises AND gate 421, NOT gate 422, and OR gate 423. Scan-flop 301 is coupled to AND gate 421 which is coupled to NOT gate 422 and OR gate 323. AND gate 421 provides a constant first logic value (e. g., logic 0) on logic value output 307 when scan test mode signal 303 is not asserted (e. g., logical 0 value), irrespective of the logical value stored in scan-flop 301. AND gate 421 changes the logical value on logic value output 307 in accordance with the output of scan flop 301 during scan test operations (e. g., when scan test mode signal 303 is asserted). OR gate 423 provides a constant second logic value (e. g., logic 1) on logic value output 308 when scan test mode signal 303 is not asserted, irrespective of the logical value stored in scan-flop 301. OR gate 423 changes the logical value on logic value output 307 in accordance with the output of scan flop 301 during scan test operations.

NOT gate 422 assures that the second logic value is the opposite of the first logic value.

Fig. 5 is a block diagram of a scan test controllable tied gate input system 500, one embodiment of the present invention. Traditional IC 500 comprises design circuit block

530, design circuit block 540, design circuit block 550 and design circuit block 570, and constant logic value scan test manipulation circuit 510. Constant logic value scan test manipulation circuit 510 is coupled to design circuit block 530, design circuit block 540, design circuit block 550 and design circuit block 570. Design circuit blocks 530 through 570 include a logic gate circuit 581 through 584 respectively which comprise one or more logic circuit gates. For example, logic gate circuit 581 includes AND gate 590. Gate input 592 and gate output 593 are coupled to other gates (not shown) in design circuit block 530. Gate input 591 is tied to constant logic value scan test manipulation circuit 510.

In one exemplary implementation of the present invention, each of the design circuit blocks 530 through 570 comprise scan test elements such as scan test flip flops that are included in scan test chain 528. For example design circuit block 530 includes scan flip flop 531 and scan flip flop 532, design circuit block 540 includes scan flip flop 541 and scan flip flop 542, design circuit block 550 includes scan flip flop 551 and scan flip flop 552, and design circuit block 570 includes scan flip flop 571 and scan flip flop 572. The scan test flip flops are coupled to other components (not shown) of the design circuit blocks and perform scan test capture and shifting during scan test operations and register functions during normal operations. Gate inputs of logic gates included in logic gate circuit 581 through 584 tied to constant logic value scan test manipulation circuit 510 are held constant during normal operations and manipulated during test operations by test scan vectors in accordance with scan test input signal 521 under control of scan test output test mode signal 525. The values of these gates can be retrieved from scan test output signal 522.

Fig. 6 is a block diagram of a scan test controllable tied gate input system 600, one embodiment of the present invention. Scan test controllable tied gate input system 600 is similar to scan test controllable tied gate input system 500, except scan test controllable tied gate input system 600 provides greater granularity in the manipulation of tied logic values.

Scan test controllable tied gate input system 600 comprises design circuit block 630, design circuit block 640, design circuit block 650 and design circuit block 670. Similar to scan test controllable tied gate input system 500, design circuit blocks 630 through 670 include a logic gate circuit 681 through 684 respectively which comprise one or more logic circuit gates. In addition, design circuit blocks 630 through 670 include constant logic value scan test manipulation circuit 611 through 614 respectively.

Similar to scan test controllable tied gate input system 500, the design circuit blocks 630 through 670 include scan test elements such as scan test flip flops (e. g., scan flip flop 631,632,651,652,641,642,671, and 672) that are included in scan test chain 628. The

scan test flip flops are coupled to other components (not shown) of the design circuit blocks and perform scan test capture and shifting during scan test operations and register functions during normal operations. Scan test manipulation circuit 611 through 614 are included in scan test chain 628. For example, scan test manipulation circuit 611 is coupled to scan flip flop 631 and 633, scan test manipulation circuit 613 is coupled to scan flip flop 651 and 653, scan test manipulation circuit 612 is coupled to scan flip flop 641 and 643, and scan test manipulation circuit 614 is coupled to scan flip flop 671 and 673. Scan test input signal 621 is coupled to design circuit block 630 through 670 via scan test chain 628.

Scan test manipulation circuit 611 through 614 provide greater granularity in the manipulation of tied logic values. Scan test manipulation circuit 611 through 614 are coupled to gate inputs of logic gates included in design circuit block 630,640,650 and 670.

For example, scan test manipulation circuit 611 is coupled to logic gate circuit 681, scan test manipulation circuit 613 is coupled to logic gate circuit 683, scan test manipulation circuit 614 is coupled to logic gate circuit 684, and scan test manipulation circuit 612 is coupled to logic gate circuit 682. Scan test manipulation circuit 611 through 614 supply constant logic values to logic gate circuit 681 through 684 respectively during normal operations. Scan test manipulation circuit 611 through 614 manipulate the logic values they supply to logic gate circuit 681 through 684 individually during scan test operations. This takes place under control of scan test mode signal 625. Like in gate input system 500, the logic values are manipulated in accordance with scan test input signal 621 and outputted via scan test output signal 622.

A constant logic can be described as follows value scan test manipulation method, one embodiment of the present invention. Constant logic value scan test manipulation method is compatible with normal scan testing methodologies. During testing operations, constant logic value scan test manipulation method permits manipulation of a logic value output tied to combinational logic inputs. During normal operations constant logic value scan test manipulation method provides a constant logic value output.

In a first step, a scan test element coupled to a combinational logic is directed to operate in a normal function mode. In one embodiment of the present invention as can test mode signal is utilized to direct the scan test element to operate in a normal function mode.

In one exemplary implementation of constant logic value scan test manipulation method, the scan test element is a constant logic value scan test manipulation circuit (e. g., constant logic value scan test manipulation circuit 221)

In a second step, a logical value is provided to the input of combinational logic and held constant during normal operations. In one embodiment of present invention, the logic value is supplied to the input of a logic gate.

The scan test element coupled to the combinational logic is put in a scan test operating mode in a third step. In one embodiment of the present invention, the scan test element is put in scan test mode in accordance with a test mode instruction signal.

In a fourth step, the logical value provided to the input of the combinational logic is manipulated during test operations. In one embodiment of the present invention, the logical value provided to the input of the combinational logic (e. g., a gate) is manipulated in accordance with a scan test input signal. In one exemplary implementation of the present invention, the manipulation of the logic value input of the gate is utilized to facilitate control of an input of a logic gate tied to the logic value during test operations.

Thus, the present invention is a system and method that facilitates scan test manipulation of logic values input to combinational logic (e. g., a logic gate) and ensures the logic value of v the combinational logic input is tied to remain constant during normal operations. In one embodiment of the present invention, scan testing of integrated circuit components with an ATPG tool is supported and the system and method accommodates utilization of existing scan testing architectures.

The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the Claims appended hereto and their equivalents.