SCANNING DRIVING CIRCUIT, ARRAY SUBSTRATE, AND DISPLAY PANEL

WIPO Patent Application WO/2024/001053

A1

A scanning driving circuit (15), an array substrate (1), and a display panel. The scanning driving circuit (15) comprises N cascaded GDL circuits; an nth GDL circuit comprises: a pull-up control module (1511), an output module (1512), a first pull-down control module (1513), a second pull-down control module (1514), a pull-down module (1515), and a first node; the output module (1512) is used for outputting an nth-stage level transmission signal and an nth-stage scanning signal according to an inputted clock signal when the potential of the first node is a first potential, and stopping outputting the nth-stage level transmission signal and the nth-stage scanning signal when the potential of the first node is a second potential; a time period when the clock signal maintains a high potential comprises a first time period and a second time period; the clock signal maintains a first high potential in the first time period, and maintains a second high potential in the second time period, the second high potential being higher than the first high potential; thus, the stability of the GDL circuits can be improved.

LI YANG (CN)
LI RONGRONG (CN)

PCT/CN2022/137322

January 04, 2024

December 07, 2022

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HKC CORP LTD (CN)

G09G3/36

CN114974163A	2022-08-30
CN114333731A	2022-04-12
CN113570995A	2021-10-29
CN105513550A	2016-04-20
CN105702225A	2016-06-22
CN106128408A	2016-11-16
CN109801587A	2019-05-24
CN113380172A	2021-09-10
CN1783702A	2006-06-07
US20180144703A1	2018-05-24

CHINA WISPRO INTELLECTUAL PROPERTY LLP. (CN)

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