Title:
SCANNING LINE DRIVE CIRCUIT AND DISPLAY DEVICE EQUIPPED WITH SAME
Document Type and Number:
WIPO Patent Application WO/2018/163985
Kind Code:
A1
Abstract:
A scanning line drive circuit 10 constructed from a cascade of single circuits 11 operates in accordance with eight-phases of clock signals CK1 through CK8 that vary between a high-level voltage VGH and a low-level voltage VSS1. A single circuit 11 comprises: a transistor M10B that includes a drain terminal connected to a clock terminal CK, a gate terminal connected to a node Na, and a source terminal connected to a second output terminal Q for outputting a signal to single circuits in other blocks; a transistor M9 that applies a low-level voltage VSS2 to the node Na in accordance with the potential at a reset terminal R; and a transistor M14B that applies a low-level voltage VSS3 to the second output terminal Q in accordance with the potential at a Node Nb. The low-level voltage satisfies VSS1 > VSS2 > VSS3. Thereby, the present invention provides a scanning line drive circuit that can be controlled more easily using a depletion type transistor.
Inventors:
TAGAWA AKIRA
IWASE YASUAKI
TAKEUCHI YOHEI
WATANABE TAKUYA
IWASE YASUAKI
TAKEUCHI YOHEI
WATANABE TAKUYA
Application Number:
PCT/JP2018/007958
Publication Date:
September 13, 2018
Filing Date:
March 02, 2018
Export Citation:
Assignee:
SHARP KK (JP)
International Classes:
G09G3/36; G02F1/133; G09G3/20; G11C19/28
Domestic Patent References:
| WO2010067641A1 | 2010-06-17 |
Foreign References:
| US20140267214A1 | 2014-09-18 | |||
| JP2015033026A | 2015-02-16 | |||
| JP2012257211A | 2012-12-27 | |||
| JP2014026258A | 2014-02-06 |
Attorney, Agent or Firm:
SHIMADA, Akihiro et al. (JP)
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