Title:
SECOND-ORDER ΔΣ MODULATOR, RADIO, AND SIGNAL PROCESSING METHOD PERFORMED BY SECOND-ORDER ΔΣ MODULATOR
Document Type and Number:
WIPO Patent Application WO/2019/111884
Kind Code:
A1
Abstract:
A second-order ΔΣ modulator according to the present invention has a two-stage integrator, a first arithmetic operation unit, and a second arithmetic operation unit. The two-stage integrator includes a plurality of adder sequences each comprising a plurality of adders. The plurality of adder sequences include first to fourth adder sequences. The last-stage output of the second adder sequence is fed back as the first-stage input of the first adder sequence. The last-stage output of the fourth adder sequence is fed back as the first-stage input of the third adder sequence. A sum bit string obtained in the first adder sequence is input to the third adder sequence. A sum bit string obtained in the second adder sequence is input to the fourth adder sequence. The first arithmetic operation unit performs an arithmetic operation on the basis of inputs supplied to the plurality of adders of the first adder sequence and inputs the result of the arithmetic operation to the second adder sequence. The second arithmetic operation unit performs an arithmetic operation on the basis of inputs supplied to the plurality of adders of the first adder sequence and inputs supplied to the plurality of adders of the third adder sequence and inputs the result of the arithmetic operation to the fourth adder sequence.
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Inventors:
TANIO MASAAKI (JP)
Application Number:
PCT/JP2018/044534
Publication Date:
June 13, 2019
Filing Date:
December 04, 2018
Export Citation:
Assignee:
NEC CORP (JP)
International Classes:
H03M7/36
Domestic Patent References:
| WO2017037880A1 | 2017-03-09 | |||
| WO2018101467A1 | 2018-06-07 |
Foreign References:
| US20090109076A1 | 2009-04-30 | |||
| JP2011077741A | 2011-04-14 |
Other References:
TANIO, MASAAKI ET AL.: "An FPGA-based All-Digital Transmitter with 28-GHz Time-Interleaved Delta- Sigma Modulation", 2016 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM (IMS, May 2016 (2016-05-01), pages 1 - 4, XP032941166, Retrieved from the Internet [retrieved on 20190206], DOI: doi:10.1109/MWSYM.2016.7540142
TANIO, MASAAKI ET AL.: "An FPGA-based All-Digital Transmitter with 9.6-GHz 2nd order Time-Interleaved Delta-Sigma Modulation for 500-MHz bandwidth", 2017 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM (IMS, June 2017 (2017-06-01), pages 149 - 152, XP033160036, Retrieved from the Internet [retrieved on 20190206], DOI: doi:10.1109/MWSYM.2017.8058904
TANIO, MASAAKI ET AL.: "An FPGA-based 1-bit Digital Transmitter with 800-MHz Bandwidth for 5G Millimeter-wave Active Antenna Systems", 2018 IEEE /MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM- IMS, June 2018 (2018-06-01), pages 499 - 502, XP033388233, Retrieved from the Internet [retrieved on 20190206], DOI: doi:10.1109/MWSYM.2018.8439663
TANIO, MASAAKI ET AL.: "An FPGA-based All-Digital Transmitter with 9.6-GHz 2nd order Time-Interleaved Delta-Sigma Modulation for 500-MHz bandwidth", 2017 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM (IMS, June 2017 (2017-06-01), pages 149 - 152, XP033160036, Retrieved from the Internet
TANIO, MASAAKI ET AL.: "An FPGA-based 1-bit Digital Transmitter with 800-MHz Bandwidth for 5G Millimeter-wave Active Antenna Systems", 2018 IEEE /MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM- IMS, June 2018 (2018-06-01), pages 499 - 502, XP033388233, Retrieved from the Internet
Attorney, Agent or Firm:
TANAI Sumio et al. (JP)
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