CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63/281,001, filed on November 18, 2021, and U.S. Non-Provisional Patent Application No. 17/665,272, filed on February 4, 2022, which are incorporated herein by reference in their entirety.

TECHNICAL FIELD

[0002] The present disclosure relates generally to flyback converters, and more specifically to a flyback converter using a controller on the secondary winding side to facilitate zero-voltage switching and synchronous rectification.

BACKGROUND

[0003] Increased demand for high-efficiency flyback converters gave rise to various solutions using an active clamp to facilitate zero-voltage switching (ZVS) of the switching device. Some of these active clamp flyback converters maintain a complimentary drive of the clamp switch; others only activate the clamp switch for a brief period immediately before turning the controlled switching device on. Both types of solutions are intended to develop current in reverse direction in the power transformer windings and then provide a dead time to allow for discharging the parasitic capacitance of the switching node to substantially zero voltage.

[0004] FIG. 1 shows an active clamp flyback converter 100 using an active clamp at the primary winding of the transformer according to the prior art. The flyback converter 100 receives input voltage VIN from a voltage source 101 and delivers output voltage VO to a load 200. The flyback converter 100 includes a flyback transformer 102 having a primary winding PRI and a secondary winding SEC, a primary switch 103 activated by a first control circuit 112, a synchronous rectifier switch 104 activated by a second control circuit 108, an output smoothing capacitor 105, a clamp diode 194, and a clamp capacitor 110. The flyback converter 100 further includes an active clamp switch 193.  The active clamp switch 193 is coupled across the clamp diode 194 to provide a path for reverse current in the primary winding PRI of the transformer 102. The inductance 192 represents leakage inductance reflected to the primary winding PRI. The active clamp flyback converter 100 recirculates energy stored in the leakage inductance 192. However, it suffers added cost and complexity of driving the active clamp switch 193, which is activated by an active clamp control circuit 111. The reverse current of the primary winding PRI recirculates the energy stored in parasitic capacitance 109 back to the input voltage source 101 before the primary switch 103 turns on. [0005] Other types of converters use an auxiliary winding to generate the reverse current. An example of such a converter 180 is depicted in Figure 2. The converter 180 includes all elements of the converter 100 of Figure 1, with the exception of the clamp diode 194, clamp capacitor 110, active clamp switch 193, and active clamp control circuit 111. Instead, the flyback transformer 102 of the converter 180 further comprises an auxiliary winding AUX coupled in series with a clamp capacitor 107 and an active clamp switch 106, the active clamp switch activated by a control circuit 111a. The reverse current is developed in the auxiliary winding AUX by means of coupling it across the clamp capacitor 107 via the active clamp switch 106 for a brief period. Once the active clamp switch 106 turns off, the resulting negative magnetic flux induces reverse current in the primary winding PRI, recirculating the energy stored in the parasitic capacitance 109 back to the input voltage source 101. The converter 180 does not recirculate the leakage inductance energy, and it must be absorbed by some other means. However, the solution offers a lower overall cost. [0006] FIG.3 illustrates the operating principle of the converters of FIGs.1 and 2 with the active clamp switches 193 and 106, respectively, activated for a brief period preceding the turn on of the primary switch 103. The waveform 301 represents the voltage across the primary switch 103. The waveforms 302 and 303 represent the conductive states of the primary switch 103 and the synchronous rectifier device 104, respectively. The conductive state of the synchronous rectifier device 104 may be followed by post-conduction oscillation of the voltage across the primary switch 103 illustrated by the waveform 301. The oscillation period is determined primarily by the inductance of the primary winding PRI and the parasitic capacitance 109. The waveform 304 represents the ZVT Pulse activating the active clamp switches 193 and 106, respectively. The delay between the trailing edge of the ZVT Pulse and the rising edge of the waveform 302 represents the Dead Time allowing for discharging of the parasitic capacitance 109. [0007] Although the synchronous rectifier device 104 can also be utilized to allow for the reverse magnetic flux in the transformer 102, thus eliminating the need for an extra active clamp switch and an auxiliary winding and reducing the cost of the overall solution, driving the synchronous rectifier device 104 introduces excessive gate drive losses having an adverse effect on the converter efficiency. Therefore, a control method is needed to reduce the synchronous rectifier device 104 gate drive power losses when the synchronous rectifier device 104 is used for this dual purpose. Separately, an appropriate control algorithm is needed for generation of the ZVT Pulse for driving the synchronous rectifier device 104 when the synchronous rectifier device 104 is used for this dual purpose. SUMMARY   [0008] According to an aspect of one or more examples, there is provided a flyback converter to receive an input voltage and provide an output voltage. The flyback converter may include a transformer having a primary winding and secondary winding, a primary switch coupled to the primary winding, a synchronous rectifier device coupled to the secondary winding, and a secondary side control circuit to turn on the synchronous rectifier device by outputting a control signal at a first amplitude, subsequently modify the control signal to maintain substantially constant voltage across the synchronous rectifier device until a predicted time that precedes a current in the synchronous rectifier device reaching zero, subsequently turn off the synchronous rectifier device based on the voltage across the synchronous rectifier device reaching substantially zero, and subsequently turn on the synchronous rectifier device by outputting the control signal at a second amplitude, before the primary switch is turned on. The second amplitude may be less than the first amplitude.

[0009] The secondary side control circuit may include a synchronous rectifier control circuit that may predict the predicted time that precedes a time at which the current in the synchronous rectifier device reaches substantially zero. The synchronous rectifier control circuit may have a transconductance error amplifier, and the synchronous rectifier control circuit may store a voltage level at an output of the transconductance error amplifier sampled at the predicted time. The second amplitude may substantially equal the stored voltage level at the predicted time.

[0010] The synchronous rectifier control circuit may predict the predicted time that precedes the time at which the current in the synchronous rectifier device reaches substantially zero by integrating a difference between the voltage across the synchronous rectifier device and the output voltage. [0011] The synchronous rectifier control circuit may predict the predicted time that precedes the time at which the current in the synchronous rectifier device reaches substantially zero by integrating the voltage across the secondary winding.

[0012] The secondary side control circuit may turn on the synchronous rectifier device by outputting the control signal at the first amplitude in response to detecting that the voltage across the synchronous rectifier device is negative, and may reduce the control signal from the first amplitude as the current in the synchronous rectifier device decreases.

[0013] The secondary side control circuit may hold the control signal at a substantially constant level after the predicted time, before turning off the synchronous rectifier device based on the voltage across the synchronous rectifier device reaching substantially zero.

[0014] The voltage across the synchronous rectifier device may enter oscillation when the synchronous rectifier device is turned off. The secondary side control circuit may turn on the synchronous rectifier device at the last valley of the oscillation of the voltage across the synchronous rectifier device before the primary switch is turned on.

[0015] The secondary side control circuit may include a pulse generator circuit that may detect a period of the oscillation of the voltage across the synchronous rectifier device. The secondary side control circuit may turn on the synchronous rectifier device before the primary switch is turned on for a duration of time based on the detected period of oscillation of the voltage across the synchronous rectifier device.

[0016] The flyback converter may also include a primary switch control circuit that may turn on the primary switch after a dead time delay following the turn off of the synchronous rectifier device. [0017] According to an aspect of one or more examples, there is provided a method of controlling a flyback converter that includes a transformer having a primary winding and a secondary winding, a primary switch coupled to the primary winding, and a synchronous rectifier device coupled to the secondary winding. The method may include outputting a control signal at a first amplitude to turn on the synchronous rectifier device, subsequently modifying the control signal to maintain substantially constant voltage across the synchronous rectifier device until a predicted time that precedes a current in the synchronous rectifier device reaching substantially zero, subsequently turning off the synchronous rectifier device based on the voltage across the synchronous rectifier device reaching substantially zero, subsequently turning on the synchronous rectifier device by outputting the control signal at a second amplitude, before the primary switch is turned on. The second amplitude may be less than the first amplitude.

[0018] The method may also include predicting a predicted time that precedes a time at which a current in the synchronous rectifier device reaches substantially zero. The method may also include storing a voltage level of the output of a transconductance error amplifier at the predicted time. The output of the transconductance error amplifier may be based on a difference between the voltage across the synchronous rectifier device and a reference voltage. The second amplitude may substantially equal the stored voltage level at the predicted time.

[0019] Predicting the predicted time may include integrating a difference between the voltage across the synchronous rectifier device and an output voltage across the secondary winding.

[0020] Predicting the predicted time may include integrating a voltage across the secondary winding. [0021] The outputting of the control signal at the first amplitude to turn on the synchronous rectifier device may occur in response to detecting the voltage across the synchronous rectifier device is negative.

[0022] The method may include, after the outputting of the control signal at the first amplitude to turn on the synchronous rectifier device, reducing the control signal from the first amplitude as the current in the synchronous rectifier device decreases.

[0023] The method may include, at the predicted time, holding the control signal at a substantially constant level, before turning off the synchronous rectifier device based on the voltage across the synchronous rectifier device reaching substantially zero.

[0024] The voltage across the synchronous rectifier device may enter oscillation when the synchronous rectifier device is turned off, and the subsequent turning off of the synchronous rectifier device may occur at the last valley of the oscillation of the voltage across the synchronous rectifier device before the primary switch is turned on.

[0025] The method may include detecting a period of the oscillation of the voltage across the synchronous rectifier device. The subsequent turning on of the synchronous rectifier device may be for a duration based on the detected period of oscillation of the voltage across the synchronous rectifier device.

[0026] The method may include turning on the primary switch after a dead time delay following the turning off of the synchronous rectifier device.

[0027] According to an aspect of one or more examples, there is provided a method of generating an auxiliary pulse signal for controlling a synchronous rectifier device coupled to a secondary winding of a transformer in a flyback converter. The method may include outputting a control signal at a first amplitude, reducing the control signal from the first amplitude as the current in the synchronous rectifier device decreases, predicting a predicted time that precedes a time at which the current in the synchronous rectifier device reaches substantially zero, storing a voltage level of the output of a transconductance amplifier at the predicted time, wherein the output of the transconductance error amplifier is based on a difference between the voltage across the synchronous rectifier device and a reference voltage. The method may also include generating the auxiliary pulse signal so as to output the control signal to turn on the synchronous rectifier device before the primary switch is turned on, the control signal responsive to the auxiliary pulse signal at an amplitude substantially equal to the stored voltage level of the output of the transconductance error amplifier at the predicted time.

[0028] According to an aspect of one or more examples, there is provided a method of generating an auxiliary pulse signal for controlling a synchronous rectifier device coupled to a secondary winding of a transformer in a flyback converter. The method may include detecting a period of oscillation of a voltage across the synchronous rectifier device, detecting a peak voltage across the synchronous rectifier device, and generating the auxiliary pulse signal having a pulse width determined based on the detected period of oscillation of the voltage across the synchronous the rectifier device, and a difference between the peak voltage across the synchronous rectifier device and an output voltage of the flyback converter.

BRIEF DESCRIPTION OF DRAWINGS

[0029] FIG. 1 shows an active clamp flyback converter according to the prior art.

[0030] FIG. 2 shows a flyback converter having an auxiliary winding according to the prior art.

[0031] FIG. 3 shows a waveform diagram illustrating the operation of the flyback converters of FIGs. 1 and 2. [0032] FIG. 4 shows a circuit diagram of a flyback converter according to various examples of the present disclosure.

[0033] FIG. 5 shows a waveform diagram illustrating the operation of the flyback converter shown in FIG. 4.

[0034] FIG. 6 shows a waveform diagram illustration the operation of a pulse generator circuit according to various examples of the present disclosure.

[0035] FIG. 7 shows a circuit diagram of a pulse generator circuit according to various examples of the present disclosure.

[0036] FIG. 8 shows a circuit diagram of a synchronous rectifier control circuit according to various examples of the present disclosure.

[0037] FIG. 9 shows a circuit diagram of a zero current prediction circuit according to various examples of the present disclosure.

DETAILED DESCRIPTION OF VARIOUS EXAMPLES

[0038] Reference will now be made in detail to the following various examples, which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. The following examples may be embodied in various forms without being limited to the examples set forth herein. Descriptions of well-known parts are omitted for clarity.

[0039] FIG. 4 is a circuit schematic of a flyback converter 400 in accordance with various examples of the present disclosure. The example flyback converter 400 receives input voltage VIN from an input voltage source 101 and delivers galvanically isolated output voltage Vo to a load 200. The flyback converter 400 includes: a transformer 102 having a primary winding PRI and a secondary winding SEC; a primary switch 103; a primary switch control circuit 112; a synchronous rectifier device 104 coupled to the secondary winding SEC; a secondary side control circuit 199, which may include a synchronous rectifier control circuit 117 and a pulse generator circuit 116; and an output smoothing capacitor 105. The converter 400 also includes effective parasitic capacitance 109. FIG. 4 depicts the capacitance 109 reflected to the primary switch 103, while it needs to be understood as total parasitic capacitance distributed across all elements of the flyback converter 400 and its physical construction.

[0040] The primary switch control circuit 112 activates the primary switch 103 repetitively to couple the primary winding PRI to the input voltage source 101 for receiving electrical energy from the input voltage source 101 and storing it in the transformer 102. The secondary side control circuit 199 drives the synchronous rectifier device 104. According to one or more examples, the secondary side control circuit 199 may include the pulse generator circuit 116 that generates an auxiliary pulse signal in accordance with the output voltage Vo and the voltage VD across the synchronous rectifier device 104. The secondary side control circuit 199 may also include the synchronous rectifier control circuit 117 that controls the synchronous rectifier device 104 in accordance with the voltage VD across the synchronous rectifier device 104 and the auxiliary pulse signal received from the pulse generator circuit 116. The synchronous rectifier control circuit 117 may also control the synchronous rectifier device 104 based on the output voltage Vo, as represented by the dotted line in Fig. 4 connecting the output voltage Vo to the synchronous rectifier control circuit 117.

[0041] The operating principle of the flyback converter 400 is illustrated by FIG. 5.

Referring to FIGs. 4 and 5, the waveform 301 represents the voltage across the primary switch 103. The waveform 311 represents the voltage VD across the synchronous rectifier device 104, whereas its exploded portion in the vicinity of the common return voltage is shown by the waveform 311a. The waveform 399 represents the current in the synchronous rectifier device 104, which substantially equals the current in the secondary winding SEC of the transformer 102. The waveform 302 shows the primary control signal to the primary switch 103 generated by the primary switch control circuit 112, whereas the waveform 312 represents the control voltage to the synchronous rectifier device 104 generated by the synchronous rectifier control circuit 117.

[0042] As illustrated by the waveform 311a, following the turn-off of the primary switch 103, voltage VD across the synchronous rectifier device 104 becomes negative. The synchronous rectifier control circuit 117 detects this negative voltage VD and switches the synchronous rectifier device 104 fully on as illustrated by the waveform 312. Upon the turn-on of the synchronous rectifier device 104, the voltage VD across it is determined by the on resistance of the synchronous rectifier device 104. As the current in secondary winding SEC decreases, as shown by waveform 399, the corresponding voltage VD across the synchronous rectifier device 104 decreases proportionally until it reaches a level designated as Plateau in the waveform 311a. The synchronous rectifier control circuit 117 maintains this Plateau level of voltage VD across the synchronous rectifier device 104 by reducing the control voltage to the synchronous rectifier device 104 as shown by waveform 312 so as to increase the on resistance of the synchronous rectifier device 104 as the current through the synchronous rectifier device 104 (shown as waveform 399), i.e. the current through secondary winding SEC, falls towards zero. The synchronous rectifier control circuit 117 further predicts a predicted time that precedes the current in the synchronous rectifier device 104 reaching substantially zero by, for example, integrating the difference between voltage VD across the synchronous rectifier device 104 and the output voltage Vo. The synchronous rectifier control circuit 117 may alternatively predict a predicted time that precedes the current in the synchronous rectifier device 104 reaching substantially zero by integrating the voltage across the secondary winding SEC, i.e. Vo - VD. When this predicted time, designated on the waveform 312 as ZCP, is reached, the synchronous rectifier control circuit 117 changes its output to a high impedance, thus no longer driving the control voltage to the synchronous rectifier device 104 as shown by waveform 312. When the synchronous rectifier control circuit 117 changes its output to a high impedance, there is no discharge path for the gate of the synchronous rectifier device 104, so the control voltage to the synchronous rectifier device 104, shown by waveform 312, remains at a substantially constant level. This substantially constant voltage level of the gate of the synchronous rectifier device 104 dictates a substantially constant on resistance of the synchronous rectifier device 104. Accordingly, the voltage VD across the synchronous rectifier device 104 falls out of the regulated Plateau level and begins approaching zero, while its magnitude is now dictated by the product of the substantially constant on resistance of the synchronous rectifier device 104 held from ZCD and the current in the synchronous rectifier device 104. When the voltage VD across the synchronous rectifier device 104 reaches substantially zero level, designated as Common in the waveform 311a, the synchronous rectifier control circuit 117 turns the synchronous rectifier device 104 off by driving the control voltage to the synchronous rectifier device 104 as shown by waveform 312 to substantially zero voltage. The level of the control voltage to the synchronous rectifier device 104 as shown by waveform 312 to the synchronous rectifier device 104 is sampled at ZCD, and is stored to subsequently set the amplitude of the control signal based on an auxiliary pulse signal, having pulse width INEG, as illustrated by the waveform 312.

[0043] The auxiliary pulse signal, having pulse width INEG, may be generated by the pulse generator circuit 116 at the last peak of oscillation of the waveform 301, i.e. the last peak of oscillation of the voltage across the primary switch 103, or the last valley of oscillation of the waveform 311, i.e. the last valley of oscillation of the VD across the synchronous rectifier device 104, that precedes the next turn on of the primary switch 103, and further propagated by the synchronous rectifier control circuit 117 as the control signal to the synchronous rectifier device 104 at the stored amplitude. By reducing the amplitude of the control signal output by the synchronous rectifier control circuit 117, as compared to the amplitude of the control signal that initially switches the synchronous rectifier device 104 fully on as illustrated by the waveform 312, losses in the synchronous rectifier control circuit 117 may be reduced. The auxiliary pulse signal, having pulse width INEG, may reduce switching losses in the synchronous rectifier device 104, by activating the synchronous rectifier device 104 in the last valley of oscillation of the voltage VD across the synchronous rectifier device 104 that precedes the next turn on of the primary switch 103.

[0044] The principle of operation of the pulse generator circuit 116 according to various examples is illustrated by FIG 6. The waveform 311 represents the voltage VD across the synchronous rectifier device 104, referenced to the output voltage level Vo. The pulse width of the waveform 322 represents the half-cycle of the oscillation of the voltage VD across the synchronous rectifier device 104, which is measured by the pulse generator circuit 116. The waveform 323 is the auxiliary pulse signal having pulse width INEG generated by the pulse generator circuit 116.

[0045] The parasitic capacitance 109 may be non-linear since it includes the output capacitance of the primary switch 103, which increases substantially at a lower voltage across it. Therefore, the energy stored in the parasitic capacitance 109 is greater by a factor of k _e r>l as compared to one calculated as CV ² /2. The pulse generator circuit 116 according to various examples monitors the voltage VD across the synchronous rectifier device 104 and the output voltage Vo, and may generate a pulse width INEG of the auxiliary pulse signal based on the following equation: where VD(PK) is a sampled peak voltage at the synchronous rectifier device 104, and T/2 is the half-cycle of the oscillation of the voltage VD across the synchronous rectifier device 104 detected by the pulse generator circuit 116.

[0046] When generated in accordance with the above equation under the condition of ker(VD(PK)-Vo) ² /Vo ² »1, the auxiliary pulse signal may result in a reverse magnetic flux in the transformer 102 that discharges the parasitic capacitance 109 to substantially zero, and may reduce switching power losses. The pulse generator circuit 116, therefore, may generate the auxiliary pulse signal having a pulse width tNEG that is adaptive to the levels of the voltage VD across the synchronous rectifier device 104 and the output voltage Vo, as well as the parasitic capacitance 109 and inductance of the transformer 102.

[0047] The primary switch control circuit 112 provides a delay between the trailing edge of the control voltage, generated responsive to auxiliary pulse signal, to the synchronous rectifier device 104, as shown by waveform 312, and the leading edge of the primary control signal, as shown by waveform 302 of FIG. 5, designated as Dead Time in FIGs. 5 and 6. As one skilled in the art would understand, the primary switch control circuit 112 may be coupled to receive an indication of the control signal for the synchronous rectifier device 104 via magnetic, capacitive, or optical devices. The Dead Time delay may be a predetermined delay, and may allow for discharging the parasitic capacitance 109 to substantially zero. According to various examples, the Dead Time delay may be adaptively calculated as a function of the sampled period of oscillation T of the voltage VD across the synchronous rectifier device 104, as shown in waveform 322, which sampling may be done by the synchronous rectifier control circuit 117. For example, the Dead Time delay may be programmed to be T/4 from when the voltage VD across the synchronous rectifier device 104 exceeds the output voltage Vo.

[0048] A pulse generator circuit 116 according to various examples is depicted in FIG. 7. Referring to FIGs. 4 and 7, the pulse generator circuit 116 repetitively generates an auxiliary pulse signal based on the voltage VD across the synchronous rectifier device 104, and the output voltage Vo. The pulse generator circuit 116 may include a leading-edge blanking circuit 401, a peak detector 402, a subtractor circuit 405, a comparator 403, and a pulse width modulation (PWM) circuit 406. The peak detector 402 samples the peak voltage at the synchronous rectifier device 104 VD(PK) after a blanking delay generated by the leading-edge blanking circuit 401. The subtractor 405 further subtracts the output voltage Vo from the sampled peak voltage VD(PK). The comparator 403 compares the voltage VD across the synchronous rectifier device 104 with the output voltage Vo and outputs a pulse width equal to a half-cycle T/2 of the oscillation of the voltage VD across the synchronous rectifier device 104 responsive to the voltage VD across the synchronous rectifier device 104 exceeding the output voltage Vo. The PWM circuit 406 generates the auxiliary pulse signal having a pulse width INEG proportional to:

[0049] A synchronous rectifier control circuit 117 according to various examples is shown in FIG. 8. The synchronous rectifier control circuit 117 depicted in FIG. 8 generates a control signal SR Ctrl for driving the synchronous rectifier device 104 by monitoring the voltage VD across the synchronous rectifier device 104. The synchronous rectifier control circuit 117 may also monitor the output voltage Vo, and also propagates the auxiliary pulse signal having pulse width tNEG received from the pulse generator circuit 116 to its output, as the control signal SR Ctrl, at a controlled amplitude. The synchronous rectifier control circuit 117 includes: a first comparator 504 having a non-inverting terminal configured to receive a first reference threshold -VTHI and an inverting terminal configured to receive the voltage VD across the synchronous rectifier device 104, a second comparator 505 having an inverting terminal configured to receive a second reference threshold -VTH2 and a non-inverting terminal configured to receive the voltage VD across the synchronous rectifier device 104, a transconductance error amplifier 501 having a non-inverting terminal configured to receive a reference voltage -VREF, an inverting terminal configured to receive the voltage VD across the synchronous rectifier device 104, and a tri-state control input HI-Z, a zero current prediction circuit 509, a frequency compensator circuit 502, a voltage buffer 503, a latch circuit 506, an OR gate 507, and an output buffer 508. The magnitudes of the thresholds -VTHI, -VTH2 and the reference voltage -VTH2 are selected to fulfil the condition VTHI>VREF>VTH2.

[0050] In operation, the first comparator 504 detects negative voltage VD across the synchronous rectifier device 104 falling below the first threshold -VTHI and sets the latch circuit 506. Transconductance amplifier 501 receives voltage VD across the synchronous rectifier device 104 at its inverting input, a reference voltage -VREF at its non-inverting input, and outputs an amplified error voltage as a function of the difference between VD and -VREF. According to an example, the frequency compensator circuit 502 may be an RC network having an impedance Z(s). While the negative voltage drop across the synchronous rectifier device 104 is significantly greater than -VREF, the output voltage of the transconductance amplifier 104 takes the highest magnitude, as dictated by the output voltage range of the transconductance amplifier 104. The output of the latch circuit 506 then propagates via the gate 507 and the output buffer 508 at the highest output magnitude of the transconductance error amplifier 501, as buffered by voltage buffer 503. The magnitude of the voltage VD across the synchronous rectifier device 104 begins falling until it reaches substantially the reference level -VREF. When the magnitude of the voltage VD across the synchronous rectifier device 104 reaches substantially the reference level -VREF, the voltage at the output of the transconductance error amplifier 501 decreases. The decreasing voltage at the output of the transconductance error amplifier 501, which is buffered by voltage buffer 503, reduces the magnitude of the control signal SR Ctrl to maintain a substantially constant voltage VD across the synchronous rectifier device 104. As the energy stored in the transformer 102 is gradually depleted, the zero current prediction circuit 509 seeks to predict a predicted time that precedes the time at which the current in the synchronous rectifier device 104 reaches zero.

[0051] When this predicted time is reached, the zero current prediction circuit 509 outputs a signal to the high-impedance state input of the error amplifier 501, placing the output of transconductance error amplifier 501 into a high impedance state. The frequency compensator circuit 502 stores the voltage at the output of the transconductance error amplifier 501 at a substantially constant level, i.e. substantially at the voltage level appearing at the output of the transconductance error amplifier 501 when the predicted time is reached. Since the voltage VD across the synchronous rectifier device 104 is no longer regulated, it begins falling. The second comparator 505 detects the voltage VD across the synchronous rectifier device reaching the second threshold -VTH2 and resets the latch circuit 506, terminating the control signal SR Ctrl through OR gate 507.

[0052] When the synchronous rectifier control circuit 117 receives the auxiliary pulse signal having a pulse width INEG, it propagates the auxiliary pulse signal to the control signal SR Ctrl output via the OR gate 507 and the output buffer 508 at the magnitude of the voltage VD across the synchronous rectifier device 104 held by the frequency compensator circuit 502 and buffered by the voltage buffer 503.

[0053] FIG. 9 depicts a zero current prediction circuit 509 according to various examples. The zero current prediction circuit 509 depicted in FIG. 9, by monitoring the output voltage Vo and the voltage VD across the synchronous rectifier device 104, generates a HI-Z command for putting the error amplifier 501 of FIG. 8 into a high-impedance output state. The zero current prediction circuit 509 of FIG. 9 includes: a subtractor 601; an integrator 602 having a reset input; a first comparator 603 with a first threshold voltage V _TH3 ; and a latch 605. The integrator 602 integrates over time the difference between the voltage VD across the synchronous rectifier device 104 and the output voltage Vo derived by the subtraction node 601. The output of the integrator 602 is monitored by the first comparator 603 and compared to the first reference voltage V _TH3 to predict demagnetization of the transformer 102. The first comparator 603 sets the latch 605 when the output of the integrator 602 reaches the first threshold V _TH3 . The latch 605 can be reset at any arbitrary moment following the auxiliary pulse signal. For clarity, the zero current prediction circuit 509 of FIG. 9 shows a second comparator 604 with a second threshold voltage -VTH4. The second comparator 604 detects the voltage VD across the synchronous rectifier device 104 falling below the second reference voltage -Vth4 and resets the latch 605, terminating the HI-Z command.

[0054] Various examples have been disclosed herein, in connection with the above description and the drawings. It will be understood that it would be unduly repetitious to literally describe and illustrate every combination and subcombination of these examples. Accordingly, all examples can be combined in any way and/or combination, and the present specification, including the drawings, shall be construed to constitute a complete written description of all combinations and subcombinations of the examples described herein, and of the manner and process of making and using them, and shall support claims to any such combination or subcombination.

[0055] It will be appreciated by persons skilled in the art that the examples described herein are not limited to what has been particularly shown and described herein above. In addition, unless mention was made above to the contrary, it should be noted that all of the accompanying drawings are not to scale. A variety of modifications and variations are possible in light of the above teachings.