Title:
SELECTABLE DELAY PULSE GENERATOR
Document Type and Number:
WIPO Patent Application WO2005036747
Kind Code:
A3
Abstract:
A programmable pulse generator (100) having a clock signal delay chain (10), multiplexer (20), and reduced voltage charge circuit (60). The clock delay chain (10) comprises a plurality of propagated delays, coupled to the multiplexer (20). The multiplexer (20) selects a particular clock delay signal from a plurality of delay chain taps (12). The multiplexer (20) is driven by a tap select register (30) coupled to a state machine (40). The state machine (40) controls the programmable pulse output, encoding the data by varying the pulse width and delay between pulses. The delay of pulse outputs from the multiplexer (20) are reduced by coupling a reduced voltage pre-charge circuit to the multiplexer (20).
Inventors:
FAGAN JOHN L (US)
BOSSARD MARK A (US)
BOSSARD MARK A (US)
Application Number:
PCT/US2004/033341
Publication Date:
February 23, 2006
Filing Date:
October 08, 2004
Export Citation:
Assignee:
ATMEL CORP (US)
International Classes:
H03H11/26; H03K5/13; H03K7/08; H03K5/00; H03K; (IPC1-7): H03H11/26; G06F1/04
Foreign References:
US5144174A | 1992-09-01 | |||
US5594690A | 1997-01-14 | |||
US4797586A | 1989-01-10 |
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