Title:
SELECTABLE ERROR HANDLING MODES IN MEMORY SYSTEMS
Document Type and Number:
WIPO Patent Application WO/2024/036473
Kind Code:
A1
Abstract:
Aspects of the present disclosure configure a system component, such as memory sub-system controller, to capture debugging information in memory sub-system operations in response to a critical event. The memory sub-system controller receives critical event trigger data and determines whether the critical event trigger data corresponds to a fatal condition. The memory sub-system controller selects an error handling mode from a plurality of error handling modes based on determining whether the critical event trigger data corresponds to the fatal condition. A first of the plurality of error handling modes corresponds to storing a first set of debugging information associated with a memory sub-system. A second of the plurality of error handling modes corresponds to storing a second set of debugging information associated with the memory sub-system without interrupting a host. The second set can be a subset of the first set of debugging information.
Inventors:
PAN YONG HUA (CN)
KOLONOV VITALY (US)
FALLONE ROBERT (US)
TIAN JIANPING (CN)
KOLONOV VITALY (US)
FALLONE ROBERT (US)
TIAN JIANPING (CN)
Application Number:
PCT/CN2022/112747
Publication Date:
February 22, 2024
Filing Date:
August 16, 2022
Export Citation:
Assignee:
MICRON TECHNOLOGY INC (US)
International Classes:
G06F11/14
Foreign References:
| US20210389956A1 | 2021-12-16 | |||
| CN112231128A | 2021-01-15 | |||
| CN111090400A | 2020-05-01 | |||
| CN114706714A | 2022-07-05 |
Attorney, Agent or Firm:
LEE AND LI-LEAVEN IPR AGENCY LTD. (CN)
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