RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Application No. 62/487,734, filed April 20, 2017, the disclosure of which is hereby incorporated by reference in its entirety for all purposes.

TECHNICAL FIELD

[0002] The present technology relates to semiconductor systems, processes, and equipment. More specifically, the present technology relates to systems and methods for selectively etching and selectively depositing material layers on a semiconductor device.

BACKGROUND

[0003] Integrated circuits are made possible by processes which produce intricately patterned material layers on substrate surfaces. Producing patterned material on a substrate requires controlled methods for removal of exposed material. Chemical etching is used for a variety of purposes including transferring a pattern in photoresist into underlying layers, thinning layers, or thinning lateral dimensions of features already present on the surface. Often it is desirable to have an etch process that etches one material faster than another facilitating, for example, a pattern transfer process or individual material removal. Such an etch process is said to be selective to the first material. As a result of the diversity of materials, circuits, and processes, etch processes have been developed with a selectivity towards a variety of materials. Deposition processes, however, continue to be performed across substrates generally utilizing a blanket coat or a conformal fill.

[0004] As device sizes continue to shrink in next-generation devices, selectivity may play a larger role when only a few nanometers of material are formed in a particular layer, especially when the material is critical in the transistor formation Many different etch process selectivities have been developed between various materials, although standard selectivities may no longer be suitable at current and future device scale. Additionally, queue times for processes continue to rise based on the number of masking, formation, and removal operations neeaea to torm and protect the various critical dimensions of features across a device while patterning and formation are performed elsewhere on a substrate.

[0005] Thus, there is a need for improved systems and methods that can be used to produce high quality devices and structures. These and other needs are addressed by the present technology.

SUMMARY

[0006] Processing methods may be performed to form semiconductor structures that may include nanowire structures. The methods may include forming a plasma of a fluorine- containing precursor in a remote plasma region of a processing chamber. The methods may include contacting a semiconductor substrate with effluents of the plasma, and the semiconductor substrate may be housed in a processing region of the processing chamber. The methods may include laterally recessing a silicon-containing material selectively from the semiconductor substrate. The methods may further include subsequently depositing a spacer material adjacent the silicon-containing material. The spacer material may be selectively deposited on the silicon- containing material relative to exposed regions of a gate formation and a nanowire material exposed on the substrate.

[0007] In some embodiments, the etching may be performed in a first processing chamber, and the depositing may be performed in a second processing chamber. The methods may include transferring the semiconductor substrate from the first processing chamber to the second processing chamber, and the transferring may be performed without breaking vacuum. The silicon-containing material may include silicon germanium. The gate formation may include an exposed dielectric material, and the nanowire material may include silicon. The spacer material may include a metal nitride or a metal oxide. The method may be performed without conducting a reactive ion etching operation. The etching may be performed with a selectivity towards the silicon-containing material relative to the gate formation and the nanowire material greater than or about 10: 1. The deposition may be performed with a selectivity towards the silicon- containing material relative to the gate formation and the nanowire material greater than or about 2: 1. Selectively depositing the spacer material may include forming a self-assembled monolayer over the silicon-containing material. The self-assembled monolayer may interact witn one or more precursors used to form the spacer material.

[0008] The present technology may also include methods of forming a semiconductor substrate. The methods may include laterally etching a first silicon-containing material relative to a second silicon-containing material. The first silicon-containing material and the second silicon-containing material may be disposed vertically from one another, and the first silicon- containing material may be positioned vertically between two regions of the second silicon- containing material. The methods may include forming a spacer material within a recess defined by the lateral etching between the two regions of the second silicon-containing material. The methods may also include selectively recessing the spacer material to separate individual spacers.

[0009] In some embodiments, the second silicon-containing material comprises silicon. The spacer material may be selected from the group consisting of a carbon-containing material, a nitrogen-containing material, and an oxygen-containing material. The first silicon-containing material may be partially recessed from two sides of a gate formation. The first silicon- containing material may include silicon germanium. The etching may be performed in a first processing chamber, and the depositing may be performed in a second processing chamber. The methods may also include transferring the semiconductor substrate from the first processing chamber to the second processing chamber, and the transferring may be performed without breaking vacuum. The method may be performed without conducting a reactive ion etching operation. The etching may be performed with a selectivity towards the first silicon-containing material relative to the second silicon-containing material greater than or about 10: 1. The deposition may be performed with a selectivity towards the first silicon-containing material relative to the second silicon-containing material greater than or about 2: 1. [0010] Such technology may provide numerous benefits over conventional systems and techniques. For example, the processes may protect critical dimensions by utilizing techniques that do not include a reactive ion etch, and provide improved selectivity. Additionally, by performing selective operations, fewer masking and removal operations may be performed, which may reduce fabrication queue times dramatically. These and other embodiments, along with many of their advantages and features, are described in more aetau in conjunction witn tne below description and attached figures.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] A further understanding of the nature and advantages of the disclosed technology may be realized by reference to the remaining portions of the specification and the drawings.

[0012] FIG. 1 shows a top plan view of an exemplary processing system according to embodiments of the present technology.

[0013] FIG. 2A shows a schematic cross-sectional view of an exemplary processing chamber according to embodiments of the present technology.

[0014] FIG. 2B shows a detailed view of an exemplary showerhead according to embodiments of the present technology.

[0015] FIG. 3 shows a bottom plan view of an exemplary showerhead according to

embodiments of the present technology. [0016] FIG. 4 shows a schematic cross-sectional view of an exemplary processing chamber according to embodiments of the present technology.

[0017] FIG. 5 shows selected operations in a method of forming a semiconductor structure according to embodiments of the present technology.

[0018] FIGS. 6A-6C show schematic cross-sectional views of exemplary substrates according to embodiments of the present technology.

[0019] Several of the figures are included as schematics. It is to be understood that the figures are for illustrative purposes, and are not to be considered of scale unless specifically stated to be of scale. Additionally, as schematics, the figures are provided to aid comprehension and may not include all aspects or information compared to realistic representations, and may include exaggerated material for illustrative purposes.

[0020] In the appended figures, similar components and/or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a letter that distinguishes among tne similar components, it only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the letter.

DETAILED DESCRIPTION

[0021] The present technology includes systems and components for semiconductor processing of small pitch features. In traditional gate all around and other transistor structures, materials on a substrate may be formed and etched next to structures having similar or different materials that are to be maintained. Because cap layers and spacers may be formed of similar materials, such as silicon nitride, for example, the etching processes to remove these layers may not provide enough selectivity relative to other critical features. During various recessing processes, the multiple critical dimension sizes may cause a loading effect to etch beyond budget availability of material. For example, traditional processes may include a mask layer followed by a reactive-ion etch ("RIE") process that allows opening of the structure for a gap fill layer. Despite being a relatively anisotropic process, the RIE etch may still have selectivity causing sidewall losses. Although budgeting for this loss may be considered during formation, such as with over- formation of material, because regions within the structure being etched have different dimensions, calculating for the amount of loss in one area may not be suitable for the amount of loss in a larger area. Accordingly, although 5 nm of loss may occur in one section that is budgeted, loss in a larger section of 6-7 nm may still occur, causing mismatches during fabrication that can extend during subsequent operations.

[0022] Additionally, RIE processes produce an etch byproduct or polymer residue that is generally removed with ashing and a wet etching process. The ashing process can affect carbon- containing materials, and thus if materials being recessed with the RIE include carbon themselves, the ashing process may scavenge carbon from the material to be maintained.

Moreover, the wet etch often over-etches sidewall protection layers beyond critical dimensions, which can cause problems with formation and spacing of adjacent transistor layers, and further etches low-k nitride spacers and inter-layer dielectric oxide. The removal of metal materials and dielectrics is often performed with an anisotropic etch that may further reduce exposed regions of cap materials and spacer materials in other regions, unless additional masking or protective layers are formed. Because the selectivity of such RIE removal may De in tne range or iu: i, tne amount of masking required may be substantial.

[0023] Deposition of both masking material and other material layers may be performed in conventional technologies that utilizes either a blanket coating of material or a conformal development of material across all exposed areas on a semiconductor substrate. These types of deposition may require further patterning and removal operations that can substantially increase queue times for the device fabrication. Between the additional operations and deficiencies of RIE removal, and the multiple operations utilized in conventional deposition, queue times may be increased by hours for individual device layers. [0024] The present technology overcomes these issues by modifying the processes for removal and formation. By utilizing selective etch processes performed in particular equipment, the processes may be utilized to etch at higher selectivity than conventional RIE, which may allow additional patterning operations that may not previously have been capable, and may provide additional protection to critical feature dimensions. Additionally, by performing selective deposition operations in particular equipment, reduced masking, patterning, and removal may be utilized in the structure formation. These processes may save hours over conventional processes utilizing RIE and standard deposition, and may protect deposited materials from RIE scavenging to produce improved structures.

[0025] Although the remaining disclosure will routinely identify specific etching and deposition processes utilizing the disclosed technology, it will be readily understood that the systems and methods are equally applicable to a variety of other etching, deposition, and cleaning processes as may occur in the described chambers. Accordingly, the technology should not be considered to be so limited as for use with the described etching and deposition processes alone. The disclosure will discuss one possible system and chambers that can be used with the present technology to perform certain of the removal and deposition operations before describing operations of an exemplary process sequence according to the present technology.

[0026] FIG. 1 shows a top plan view of one embodiment of a processing system 100 of deposition, etching, baking, and curing chambers according to embodiments. In the figure, a pair of front opening unified pods (FOUPs) 102 supply substrates of a variety of sizes that are received by robotic arms 104 and placed into a low pressure holding area 106 before being placed into one of the substrate processing chambers 108a-f, positioned in tanoem sections iuya- c. A second robotic arm 110 may be used to transport the substrate wafers from the holding area 106 to the substrate processing chambers 108a-f and back. Each substrate processing chamber 108a-f, can be outfitted to perform a number of substrate processing operations including the dry etch processes and selective deposition described herein in addition to cyclical layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), wet etch, pre-clean, degas, orientation, and other substrate processes.

[0027] The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing and/or etching a dielectric film on the substrate wafer. In one configuration, two pairs of the processing chambers, e.g., 108c-d and 108e-f, may be used to deposit dielectric material or metal-containing material on the substrate, and the third pair of processing chambers, e.g., 108a-b, may be used to etch the deposited dielectric. In another configuration, all three pairs of chambers, e.g., 108a-f, may be configured to etch a dielectric film on the substrate. Any one or more of the processes described may be carried out in chamber(s) separated from the fabrication system shown in different embodiments.

[0028] In some embodiments the chambers specifically include at least one etching chamber as described below as well as at least one deposition chamber as described below. By including these chambers in combination on the processing side of the factory interface, all etching and deposition processes discussed below may be performed in a controlled environment. For example, a vacuum environment may be maintained on the processing side of holding area 106, so that all chambers and transfers are maintained under vacuum in embodiments. This may also limit water vapor and other air components from contacting the substrates being processed. It will be appreciated that additional configurations of deposition, etching, annealing, and curing chambers for dielectric films are contemplated by system 100. [0029] FIG. 2A shows a cross-sectional view of an exemplary process chamber system 200 with partitioned plasma generation regions within the processing chamber. During film etching, e.g., titanium nitride, tantalum nitride, tungsten, cobalt, aluminum oxide, tungsten oxide, silicon, poly silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon oxy carbide, etc., a process gas may be flowed into the first plasma region 215 through a gas inlet assembly 205. A remote plasma system (RPS) 201 may optionally be included in the system, and may process a first gas which then travels through gas inlet assembly 205. The inlet assemoiy ZU5 may include two or more distinct gas supply channels where the second channel (not shown) may bypass the RPS 201, if included.

[0030] A cooling plate 203, faceplate 217, ion suppressor 223, showerhead 225, and a substrate support 265, having a substrate 255 disposed thereon, are shown and may each be included according to embodiments. The pedestal 265 may have a heat exchange channel through which a heat exchange fluid flows to control the temperature of the substrate, which may be operated to heat and/or cool the substrate or wafer during processing operations. The wafer support platter of the pedestal 265, which may comprise aluminum, ceramic, or a combination thereof, may also be resistively heated in order to achieve relatively high temperatures, such as from up to or about 100°C to above or about 1 100°C, using an embedded resistive heater element.

[0031] The faceplate 217 may be pyramidal, conical, or of another similar structure with a narrow top portion expanding to a wide bottom portion. The faceplate 217 may additionally be flat as shown and include a plurality of through-channels used to distribute process gases.

Plasma generating gases and/or plasma excited species, depending on use of the RPS 201, may pass through a plurality of holes, shown in FIG. 2B, in faceplate 217 for a more uniform delivery into the first plasma region 215.

[0032] Exemplary configurations may include having the gas inlet assembly 205 open into a gas supply region 258 partitioned from the first plasma region 215 by faceplate 217 so that the gases/species flow through the holes in the faceplate 217 into the first plasma region 215.

Structural and operational features may be selected to prevent significant backflow of plasma from the first plasma region 215 back into the supply region 258, gas inlet assembly 205, and fluid supply system 210. The faceplate 217, or a conductive top portion of the chamber, and showerhead 225 are shown with an insulating ring 220 located between the features, which allows an AC potential to be applied to the faceplate 217 relative to showerhead 225 and/or ion suppressor 223. The insulating ring 220 may be positioned between the faceplate 217 and the showerhead 225 and/or ion suppressor 223 enabling a capacitively coupled plasma (CCP) to be formed in the first plasma region. A baffle (not shown) may additionally be located in the first plasma region 215, or otherwise coupled with gas inlet assembly zi , to airect tne now or riui into the region through gas inlet assembly 205.

[0033] The ion suppressor 223 may comprise a plate or other geometry that defines a plurality of apertures throughout the structure that are configured to suppress the migration of ionically- charged species out of the first plasma region 215 while allowing uncharged neutral or radical species to pass through the ion suppressor 223 into an activated gas delivery region between the suppressor and the showerhead. In embodiments, the ion suppressor 223 may comprise a perforated plate with a variety of aperture configurations. These uncharged species may include highly reactive species that are transported with less reactive carrier gas through the apertures. As noted above, the migration of ionic species through the holes may be reduced, and in some instances completely suppressed. Controlling the amount of ionic species passing through the ion suppressor 223 may advantageously provide increased control over the gas mixture brought into contact with the underlying wafer substrate, which in turn may increase control of the deposition and/or etch characteristics of the gas mixture. For example, adjustments in the ion concentration of the gas mixture can significantly alter its etch selectivity, e.g., SiNx:SiOx etch ratios, Si:SiOx etch ratios, etc. In alternative embodiments in which deposition is performed, it can also shift the balance of conformal-to-flowable style depositions for dielectric materials.

[0034] The plurality of apertures in the ion suppressor 223 may be configured to control the passage of the activated gas, i.e., the ionic, radical, and/or neutral species, through the ion suppressor 223. For example, the aspect ratio of the holes, or the hole diameter to length, and/or the geometry of the holes may be controlled so that the flow of ionically-charged species in the activated gas passing through the ion suppressor 223 is reduced. The holes in the ion suppressor 223 may include a tapered portion that faces the plasma excitation region 215, and a cylindrical portion that faces the showerhead 225. The cylindrical portion may be shaped and dimensioned to control the flow of ionic species passing to the showerhead 225. An adjustable electrical bias may also be applied to the ion suppressor 223 as an additional means to control the flow of ionic species through the suppressor.

[0035] The ion suppressor 223 may function to reduce or eliminate the amount of ionically charged species traveling from the plasma generation region to the substrate. Uncharged neutral and radical species may still pass through the openings in the ion suppressor to react with the substrate. It should be noted that the complete elimination of ionicaiiy cnargea species in tne reaction region surrounding the substrate may not be performed in embodiments. In certain instances, ionic species are intended to reach the substrate in order to perform the etch and/or deposition process. In these instances, the ion suppressor may help to control the concentration of ionic species in the reaction region at a level that assists the process.

[0036] Showerhead 225 in combination with ion suppressor 223 may allow a plasma present in first plasma region 215 to avoid directly exciting gases in substrate processing region 233, while still allowing excited species to travel from chamber plasma region 215 into substrate processing region 233. In this way, the chamber may be configured to prevent the plasma from contacting a substrate 255 being etched. This may advantageously protect a variety of intricate structures and films patterned on the substrate, which may be damaged, dislocated, or otherwise warped if directly contacted by a generated plasma. Additionally, when plasma is allowed to contact the substrate or approach the substrate level, the rate at which oxide species etch may increase. Accordingly, if an exposed region of material is oxide, this material may be further protected by maintaining the plasma remotely from the substrate.

[0037] The processing system may further include a power supply 240 electrically coupled with the processing chamber to provide electric power to the faceplate 217, ion suppressor 223, showerhead 225, and/or pedestal 265 to generate a plasma in the first plasma region 215 or processing region 233. The power supply may be configured to deliver an adjustable amount of power to the chamber depending on the process performed. Such a configuration may allow for a tunable plasma to be used in the processes being performed. Unlike a remote plasma unit, which is often presented with on or off functionality, a tunable plasma may be configured to deliver a specific amount of power to the plasma region 215. This in turn may allow

development of particular plasma characteristics such that precursors may be dissociated in specific ways to enhance the etching profiles produced by these precursors.

[0038] A plasma may be ignited either in chamber plasma region 215 above showerhead 225 or substrate processing region 233 below showerhead 225. In embodiments, the plasma formed in substrate processing region 233 may be a DC biased plasma formed with the pedestal acting as an electrode. Plasma may be present in chamber plasma region 215 to produce the radical precursors from an inflow of, for example, a fluorine-containing precursor or other precursor. An AC voltage typically in the radio frequency (RF) range may be applied Between tne conductive top portion of the processing chamber, such as faceplate 217, and showerhead 225 and/or ion suppressor 223 to ignite a plasma in chamber plasma region 215 during deposition. An RF power supply may generate a high RF frequency of 13.56 MHz but may also generate other frequencies alone or in combination with the 13.56 MHz frequency.

[0039] FIG. 2B shows a detailed view 253 of the features affecting the processing gas distribution through faceplate 217. As shown in FIGS. 2A and 2B, faceplate 217, cooling plate 203, and gas inlet assembly 205 intersect to define a gas supply region 258 into which process gases may be delivered from gas inlet 205. The gases may fill the gas supply region 258 and flow to first plasma region 215 through apertures 259 in faceplate 217. The apertures 259 may be configured to direct flow in a substantially unidirectional manner such that process gases may flow into processing region 233, but may be partially or fully prevented from backflow into the gas supply region 258 after traversing the faceplate 217.

[0040] The gas distribution assemblies such as showerhead 225 for use in the processing chamber section 200 may be referred to as dual channel showerheads (DCSH) and are additionally detailed in the embodiments described in FIG. 3. The dual channel showerhead may provide for etching processes that allow for separation of etchants outside of the processing region 233 to provide limited interaction with chamber components and each other prior to being delivered into the processing region. [0041] The showerhead 225 may comprise an upper plate 214 and a lower plate 216. The plates may be coupled with one another to define a volume 218 between the plates. The coupling of the plates may be so as to provide first fluid channels 219 through the upper and lower plates, and second fluid channels 221 through the lower plate 216. The formed channels may be configured to provide fluid access from the volume 218 through the lower plate 216 via second fluid channels 221 alone, and the first fluid channels 219 may be fluidly isolated from the volume 218 between the plates and the second fluid channels 221. The volume 218 may be fluidly accessible through a side of the gas distribution assembly 225.

[0042] FIG. 3 is a bottom view of a showerhead 325 for use with a processing chamber according to embodiments. Showerhead 325 may correspond with the showerhead 225 shown in FIG. 2A. Through-holes 365, which show a view of first fluid channels 219, may have a plurality of shapes and configurations in order to control and affect tne now or precursors through the showerhead 225. Small holes 375, which show a view of second fluid channels 221, may be distributed substantially evenly over the surface of the showerhead, even amongst the through-holes 365, and may help to provide more even mixing of the precursors as they exit the showerhead than other configurations.

[0043] Turning to FIG. 4 is shown a schematic cross-sectional view of an atomic layer deposition system 400 or reactor in accordance with one or more embodiments of the present technology. The system 400 may include a load lock chamber 10 and a processing chamber 20. The processing chamber 20 may be generally a sealable enclosure, which may be operated under vacuum, or at least low pressure. The processing chamber 20 may be isolated from the load lock chamber 10 by an isolation valve 15. The isolation valve 15 may seal the processing chamber 20 from the load lock chamber 10 in a closed position and may allow a substrate 60 to be transferred from the load lock chamber 10 through the valve to the processing chamber 20 and vice versa in an open position. [0044] The system 400 may include a gas distribution plate 30 capable of distributing one or more gases across a substrate 60. The gas distribution plate 30 may be any suitable distribution plate known to those skilled in the art, and specific gas distribution plates described should not be taken as limiting the scope of the technology. The output face of the gas distribution plate 30 may face the first surface 61 of the substrate 60. [0045] The gas distribution plate 30 may include a plurality of gas ports configured to transmit one or more gas streams to the substrate 60 and a plurality of vacuum ports disposed between each gas port and configured to transmit the gas streams out of the processing chamber 20. As illustrated in FIG. 4, the gas distribution plate 30 may include a first precursor injector 420, a second precursor injector 430 and a purge gas injector 440. The injectors 420, 430, 440 may be controlled by a system computer (not shown), such as a mainframe, or by a chamber-specific controller, such as a programmable logic controller. The precursor injector 420 may be configured to inject a continuous or pulse stream of a reactive precursor of compound A into the processing chamber 20 through a plurality of gas ports 425. The precursor injector 430 may be configured to inject a continuous or pulse stream of a reactive precursor of compound B into the processing chamber 20 through a plurality of gas ports 435. The purge gas injector 440 may be configured to inject a continuous or pulse stream of a non-reactive or purge gas into tne processing chamber 20 through a plurality of gas ports 445. The purge gas may be configured to remove reactive material and reactive by-products from the processing chamber 20. The purge gas may typically be an inert gas, such as nitrogen, argon or helium. Gas ports 445 may be disposed in between gas ports 425 and gas ports 435 so as to separate the precursor of compound A from the precursor of compound B, thereby avoiding cross-contamination between the precursors.

[0046] In another aspect, a remote plasma source (not shown) may be connected to the precursor injector 420 and the precursor injector 430 prior to injecting the precursors into the processing chamber 20. The plasma of reactive species may be generated by applying an electric field to a compound within the remote plasma source. Any power source that is capable of activating the intended compounds may be used. For example, power sources using DC, radio frequency, and microwave based discharge techniques may be used. If an RF power source is used, it can be either capacitively or inductively coupled. The activation may also be generated by a thermally based technique, a gas breakdown technique, a high intensity light source, such as ultraviolet light, or exposure to an x-ray source.

[0047] The system 400 may further include a pumping system 450 connected to the processing chamber 20. The pumping system 450 may be generally configured to evacuate the gas streams out of the processing chamber 20 through one or more vacuum ports 455. The vacuum ports 455 may be disposed between each gas port so as to evacuate the gas streams out of the processing chamber 20 after the gas streams react with the substrate surface and to further limit cross- contamination between the precursors.

[0048] The system 400 may include a plurality of partitions 460 disposed on the processing chamber 20 between each port. A lower portion of each partition may extend close to the first surface 61 of substrate 60, such as, for example, about 0.5 mm or greater from the first surface 61. In this manner, the lower portions of the partitions 460 may be separated from the substrate surface by a distance sufficient to allow the gas streams to flow around the lower portions toward the vacuum ports 455 after the gas streams react with the substrate surface. Arrows 498 indicate the direction of the gas streams. Since the partitions 460 may operate as a physical barrier to the gas streams, they may also limit cross contamination between the precursors The arrangement shown is merely illustrative and should not be taken as limiting the scope oi tne tecnnoiogy. it will be understood by those skilled in the art that the gas distribution system shown is merely one possible distribution system and that other types of showerheads may be employed.

[0049] In operation, a substrate 60 may be delivered, such as by a robot, to the load lock chamber 10 and may be placed on a shuttle 65. After the isolation valve 15 is opened, the shuttle 65 may be moved along the track 70. Once the shuttle 65 enters in the processing chamber 20, the isolation valve 15 may close, sealing the processing chamber 20. The shuttle 65 may then be moved through the processing chamber 20 for processing. In one embodiment, the shuttle 65 may be moved in a linear path through the chamber. [0050] As the substrate 60 moves through the processing chamber 20, the first surface 61 of substrate 60 may be repeatedly exposed to the precursor of compound A coming from gas ports 425 and the precursor of compound B coming from gas ports 435, with the purge gas coming from gas ports 445 in between. Injection of the purge gas may be designed to remove unreacted material from the previous precursor prior to exposing the substrate surface 61 to the next precursor. After each exposure to the various gas streams, the gas streams may be evacuated through the vacuum ports 455 by the pumping system 450. Since a vacuum port may be disposed on both sides of each gas port, the gas streams may be evacuated through the vacuum ports 455 on both sides. Thus, the gas streams may flow from the respective gas ports vertically downward toward the first surface 61 of the substrate 60, across the first surface 410 and around the lower portions of the partitions 460, and finally upward toward the vacuum ports 455. In this manner, each gas may be uniformly distributed across the substrate surface 61. Substrate 60 may also be rotated while being exposed to the various gas streams. Rotation of the substrate may be useful in preventing the formation of strips in the formed layers. Rotation of the substrate may be continuous or in discreet steps. [0051] The extent to which the substrate surface 61 is exposed to each gas may be determined by, for example, the flow rates of each gas coming out of the gas port and the rate of movement of the substrate 60. In one embodiment, the flow rates of each gas may be configured so as not to remove adsorbed precursors from the substrate surface 61. The width between each partition, the number of gas ports disposed on the processing chamber 20, and the number of times the substrate may be passed back and forth may also determine the extent to which the substrate surface 61 is exposed to the various gases. Consequently, the quantity ana quality ot a deposited film may be optimized by varying the above-referenced factors.

[0052] In another embodiment, the system 400 may include a precursor injector 420 and a precursor injector 430, without a purge gas injector 440. Consequently, as the substrate 60 moves through the processing chamber 20, the substrate surface 61 may be alternately exposed to the precursor of compound A and the precursor of compound B, without being exposed to purge gas in between.

[0053] The embodiment shown in FIG. 4 has the gas distribution plate 30 above the substrate. While the embodiments have been described and shown with respect to this upright orientation, it will be understood that the inverted orientation is also possible. In that situation, the first surface 61 of the substrate 60 may face downward, while the gas flows toward the substrate may be directed upward. In one or more embodiments, at least one radiant heat source 90 may be positioned to heat the second side of the substrate.

[0054] In some embodiments, the shuttle 65 may be susceptor 66 for carrying the substrate 60. Generally, the susceptor 66 may be a carrier which helps to form a uniform temperature across the substrate. The susceptor 66 may be movable in both directions left-to-right and right-to-left, relative to the arrangement of FIG. 4, between the load lock chamber 10 and the processing chamber 20. The susceptor 66 may have a top surface 67 for carrying the substrate 60. The susceptor 66 may be a heated susceptor so that the substrate 60 may be heated for processing. As an example, the susceptor 66 may be heated by radiant heat source 90, a heating plate, resistive coils, or other heating devices, disposed underneath the susceptor 66. Although illustrated as a lateral transition, embodiments of system 400 may also be utilized in a rotationally based system in which a wheel may rotate clockwise or counter-clockwise to successively treat one or more substrates positioned under the gas distribution system illustrated. Additional modifications are similarly understood to be encompassed by the present technology.

[0055] FIG. 5 illustrates a method 500 of forming a semiconductor structure, many operations of which may be performed, for example, in the chamber 200 and 400 as previously described. Method 500 may include one or more operations prior to the initiation of the method, including front end processing, deposition, etching, polishing, cleaning, or any other operations that may be performed prior to the described operations. The method may include a number of optional operations as denoted in the figure, which may or may not be specmcaiiy associated witn tne method according to the present technology. For example, many of the operations are described in order to provide a broader scope of the structural formation, but are not critical to the technology, or may be performed by alternative methodology as will be discussed further below. Method 500 describes the operations shown schematically in FIGS. 6A-6C, the illustrations of which will be described in conjunction with the operations of method 500. It is to be understood that FIG. 6 illustrates only partial schematic views, and a substrate may contain any number of transistor sections having aspects as illustrated in the figures.

[0056] Method 500 may involve optional operations to develop the semiconductor structure to a particular fabrication operation. As illustrated in FIG. 6A, the semiconductor structure may represent a device after certain transistor formation operations have occurred. The materials may have been formed in prior operations, and may have been polished to a specific height exposing each of the materials on a top and side surface of the substrate. The operations of method 500 may be performed to limit or eliminate masking operations, RTE processes including ashing and cleaning, and may reduce process queue times for forming nanowire structures.

[0057] As illustrated, structure 600 may include a substrate 601 made of or containing silicon or some other semiconductor substrate material. Structure 600 may have a number of transistor structures formed overlaying the substrate 601. For example, a dummy gate material 605 may be formed over the substrate 601, which may be removed later in processing to produce a metal gate. Dummy gate 605 may have a cap material 607 formed overlying the dummy gate 605. Additionally, a dielectric material 609 may be formed about the dummy gate 605. The dielectric material 609 may be blanketed over the structure and then patterned into the structure illustrated, or dielectric material 609 may be selectively deposited about the cap material 607 and dummy gate 605.

[0058] In some embodiments, the dummy gate may be polysilicon or a silicon-containing material. Cap material 607 may be a dielectric material, and for example, may be silicon nitride. Dielectric material 609 may also be silicon-nitride or may be an oxide, such as silicon oxide. As illustrated, structure 600 may be an N-MOS region, and a similar i'-MUS region may also De associated with the structure, although not illustrated. Several of the operations discussed below may be performed on one side of the structure while the other side remains masked, or may be performed selectively without masking. If masking is used over the two regions, the masking may then be switched with a removal and re-formation, and then similar operations may be performed on the other structure, which may be selective within the exposed region. These options will be described further below, although it is to be understood that either region may be processed before the other region, and the methods are not limited by the examples described.

[0059] Multiple layers of material may be vertically formed over source/drain regions of the substrate 601 for developing nanowires according to the present technology. The layers may include at least one layer of a first silicon-containing material 611, and at least one layer of a second silicon-containing material 613, and may include alternating layers of the materials. As illustrated in FIG. 6A, there are three layers of each portion over the source and drain, although it will be readily appreciated that there may be less than three, such as two or one layer of each, as well as more than three, such as 4, 5, 6, 7, 10, or more layers of each. As illustrated, layer 613 may be or include the same material as the substrate material 601 in embodiments.

[0060] Depending on whether the described operations are included in the N-MOS region or the P-MOS region, the first silicon-containing material and the second silicon-containing material may be different depending on the particular nanowire structure being formed. For example, on the N-MOS side of the structure as illustrated, the nanowires may be formed from silicon, and thus the second silicon-containing material 613 may be or include silicon, while the first silicon-containing material 611 may be, for example, silicon germanium having a first germanium content. However, on the P-MOS side of the structure, which is not illustrated, but may be similar, the nanowires may be formed from or include silicon germanium, for example, and thus the second silicon-containing material may be silicon germanium having a second germanium content higher than the first, while the first silicon-containing material may be, for example, silicon.

[0061] A lateral etching operation may be performed on the first silicon-containing material as illustrated in FIG. 6B. The lateral etch may be performed isotropically to remove first silicon- containing material from both sides of the gate structure, such as on both sides of dummy gate 605, and may not fully remove the first silicon-containing material, ine lateral etcn may oe performed in chamber 200 as previously described, or in a different chamber capable of performing similar etch operations. Once positioned within a processing region of the semiconductor processing chamber, the method may include forming a plasma of a fluorine- containing precursor in a remote plasma region of the processing chamber at operation 505. The remote plasma region may be fluidly coupled with the processing region, although it may be physically partitioned to limit plasma at the substrate level, which may damage exposed structures or materials. Effluents of the plasma may be flowed into the processing region, where they may contact the semiconductor substrate at operation 510. [0062] The lateral etch may then be performed at operation 515 to form a recess 617 defined between the layers of material. For example, recess 617 may be formed between each layer of second silicon-containing material 613, as well as above substrate 601. Recess 617 may also be formed on each side of the gate structure or on each side of a residual portion of first silicon- containing material 611. The recesses may be less than or about 10 nm in length in

embodiments, and may be less than or about 8 nm, less than or about 6 nm, less than or about 4 nm, between about 3 nm and about 8 nm, or between about 5 nm and about 7 nm in

embodiments. The process may maintain a certain amount of first silicon-containing material that may be located in vertical alignment with the dummy gate material, and may be characterized by dimensions similar to the dummy gate material, or slightly larger. [0063] For example, the first silicon-containing material may be maintained equivalent to a width of the dummy gate, which may be greater than or about 10 nm, greater than or about 20 nm, greater than or about 30 nm, greater than or about 40 nm, greater than or about 50 nm, greater than or about 60 nm, greater than or about 70 nm, greater than or about 80 nm, greater than or about 90 nm, or more. Additionally, the width of the first silicon-containing material may be slightly greater than the width of the dummy gate, and may be up to or about 0.5 nm more on each side of the dummy gate, and may be up to or about 1 nm more on each side, up to or about 2 nm more on each side, up to or about 3 nm more on each side, up to or about 4 nm more on each side, up to or about 5 nm more on each side, up to or about 6 nm more on each side, up to or about 7 nm more on each side, or more. [0064] The lateral etch process may selectively remove first silicon-containing matenal on, which may be silicon germanium, relative to second silicon-containing material 613, which may be silicon. The operation may have a selectivity of the first silicon-containing material relative to the second silicon-containing material greater than or about 50: 1 in embodiments, which may allow recessing of the first silicon-containing material while substantially maintaining or essentially maintaining the second silicon-containing material. In some embodiments, the second silicon-containing material may be etched less than or about 1 nm during the lateral etch operation 515, and may be etched less than or about 0.8 nm, less than or about 0.6 nm, less than or about 0.4 nm, less than or about 0.2 nm, less than or about 0.1 nm, or less. [0065] At optional operation 520, the substrate may be transferred from the etching chamber to a deposition chamber. The transfer may occur under vacuum, and the two chambers may both reside on the same cluster tool to allow the transfer to occur in a controlled environment. For example, vacuum conditions may be maintained during the transfer, and the transfer can occur without breaking vacuum. Once in the deposition chamber, such as chamber 400 described above, a spacer material may be formed or deposited adjacent the recessed silicon-containing material 61 1 at operation 525. As illustrated in FIG. 6C, spacer material 620 may be formed directly on or contacting recessed silicon-containing material 61 1. This lateral deposition may be a timed deposition to form the spacer material 620 within the recesses 617, while limiting formation on other exposed surfaces. Spacer material 620 may be formed about the silicon- containing materials, as well as within the recesses 617 previously formed. The spacer material 620 may be layered between regions of second silicon-containing material and may completely fill recesses 617 to contact remaining portions of first silicon-containing material defined between layers of the second silicon-containing material.

[0066] Spacer material 620 may be a silicon-containing material in embodiments, and may be or include silicon nitride, silicon carbide, silicon oxycarbide, or low-k materials including carbon-doped silicon oxide, porous materials, or other materials characterized by a low dielectric constant. The deposition operation may be a selective deposition in which the spacer material is formed preferentially on the silicon-containing material 611 relative to exposed second silicon- containing material 613, cap material 607, and dielectric material 609. As opposed to conventional technologies that may include additional masking operations, operation 323 may De performed directly subsequent etching operation 515.

[0067] Although transfer of the substrate may occur, no other substrate processing may be performed between the selective etching and the selective deposition. As will be explained in further detail below, the selective deposition may include multiple operations, but the entire deposition process may be performed directly after the etching set of operations, although substrate transfer in between the operations may be performed in embodiments. By performing a selective etch and a selective deposition according to the method 500, queue times may be substantially reduced over conventional technology that may require additional masking and removal techniques due to blanket deposition or formation of the spacer material 620. Method 500 may not utilize any RIE operations, which may reduce polymer buildup and the necessary ashing and cleaning operations associated with RIE. Additionally, as further explained below, the etching may be performed at higher or much higher selectivities than RIE, which may reduce critical dimension loss on the gate spacers, and may reduce or eliminate masking of the gate spacers and contact dielectrics.

[0068] While conventional technologies may blanket coat the spacer material and then perform an RIE operation, such a process having relatively low selectivity may etch sidewalls, underlying substrate, and deposited materials. Additionally, when carbon-containing materials are utilized within the spacer material, the ashing performed with RIE may scavenge the carbon from the formed dielectric, which will increase the dielectric constant of the material, undermining the purpose of formation. By not performing an RIE subsequent deposition of the spacer material, a carbon-content of the spacer material may be preserved, which may maintain a lower dielectric constant of the material. In some embodiments, a slight etch back operation may be performed subsequent the deposition by transferring the substrate back to the etching chamber. A subsequent dry etch may clean the sidewalls of the spacer to ensure adequate separation at operation 530, and the selectivities of the etch may be any of those described elsewhere to ensure that all other exposed materials are substantially maintained.

[0069] A variety of materials may be utilized in the processing, and the etching and deposition may be selective to multiple components. Accordingly, the present technology may not be limited to a single set of materials. For example, first silicon-containing material 61 1 may be several species as described above, and in embodiments may include a caroon-containing material. Dielectric material 609 may include an insulative material, and may include a silicon- containing material, an oxygen-containing material, a carbon-containing material, or some combination of these materials, such as silicon oxide or silicon nitride. Cap material 607 may also include an insulative material, and may also include silicon-containing material, an oxygen- containing material, a carbon-containing material, or some combination of these materials, such as silicon oxide or silicon nitride.

[0070] Other insulative materials may similarly be used in other embodiments, although the selective etching and deposition operations may be adjusted depending on what materials are used relative to other materials being formed or removed. In embodiments the cap material 607 and the dielectric material 609 may be the same material or may be different materials. For example, in one embodiment the dielectric material may be or include silicon oxide, and the cap material may be or include silicon nitride.

[0071] The etching operations may involve additional precursors along with particular fluorine-containing precursors. Nitrogen trifluoride may be utilized to generate plasma effluents in some embodiments. Additional or alternative fluorine-containing precursors may also be utilized. For example, a fluorine-containing precursor may be flowed into the remote plasma region and the fluorine-containing precursor may include at least one precursor selected from the group consisting of atomic fluorine, diatomic fluorine, carbon tetrafluoride, bromine trifluoride, chlorine trifluoride, nitrogen trifluoride, hydrogen fluoride, sulfur hexafluoride, and xenon difluoride. The remote plasma region may be within a distinct module from the processing chamber or a compartment within the processing chamber. As illustrated in FIG. 2, both RPS unit 201 and first plasma region 215 may be utilized as the remote plasma region. An RPS may allow dissociation of plasma effluents without damage to other chamber components, while first plasma region 215 may provide a shorter path length to the substrate during which recombination may occur. Additional precursors may also be delivered to the remote plasma region to augment the fluorine-containing precursor, such as other carbon-containing precursors, hydrogen- containing precursors, or oxygen-containing precursors.

[0072] The etching operations may be performed below about 10 Torr in embodiments, and may be performed below or about 5 Torr in embodiments. The process may also be performed at a temperature below about 100° C in embodiments, and may be perrormea Deiow aoout sir u. As performed in chamber 200, or a variation on this chamber, or in a different chamber capable of performing similar operations, the process may remove portions of first silicon-containing material 61 1 selective to second silicon containing material 613, cap material 607, and dielectric material 609.

[0073] The etch selectivity of the first silicon-containing material relative to other components exposed on the surface of the substrate when the present methods are performed may be greater than or about 10: 1, greater than or about 20: 1, greater than or about 50: 1, or greater than or about 100: 1, or more, for a variety of materials formed on the substrate, and which may be exposed to plasma effluents. Accordingly, depending on the feature sizes, the first silicon-containing material may be removed from the surface of the substrate while the other exposed materials may be reduced by less than 1 nm. For example, the feature width from one gate section to a second gate section may be between about 50 nm and about 70 nm, and may extend down to between about 20 nm and about 30 nm. The depth of the lateral recess for the first silicon- containing material 611 may be less than or about 50 nm, and may be less than or about 40 nm, less than or about 30 nm, less than or about 20 nm, less than or about 10 nm, or less in embodiments as noted above. Because of this depth of etching, a minimal amount of other exposed materials may be removed, which may be less than or about 3 nm, less than or about 1 nm, less than or about 0.5 nm, or the materials may be substantially or essentially maintained. Accordingly, the first silicon-containing material etch relative to the other exposed materials may be characterized by any of the selectivities discussed above for the materials that may be utilized for each structure.

[0074] The selective deposition may be performed in a chamber capable of deposition, and which may be capable of atomic layer deposition, including chamber 400 as described above. The deposition may be premised on selectively depositing an insulative material on a semiconductor material relative to another insulative material or semiconductor material. For example, the spacer material 620 may be formed substantially on first silicon-containing material 611, while being minimally formed or limited from second silicon-containing material 613, or exposed cap material 607 or dielectric material 609. The selective deposition may be performed by multiple operations, which may include formation of a self-assembled monolayer to facilitate selective deposition, or may include actively inhibiting formation or oieiectric on otner aieiectric materials.

[0075] Self-assembled monolayers may be formed on regions of the structure to tune deposition. For example, a first self-assembled monolayer may be formed over the structure, and then removed from first silicon-containing material 611. The monolayer may be maintained over second silicon-containing material 613 and the exposed top surfaces. The monolayer may have termination moieties that may repel or fail to interact with later delivered precursors. For example, the termination moieties may be hydrophobic in embodiments, and may terminate with hydrogen-containing moieties, such as methyl groups, which may not interact with additional precursors. A second self-assembled monolayer may be formed over the first silicon-containing material 61 1, which may be hydrophilic or reactive with one or more precursors utilized to produce spacer material 620. The second self-assembled monolayer may be formed selectively over the first silicon-containing material 61 1, as the material may be repelled from the first self- assembled monolayer, or may be drawn selectively to the material. The second self-assembled monolayer may terminate with hydroxyl or other hydrophilic moieties, or with moieties that interact specifically with additional precursors used to form spacer material 620.

[0076] An atomic layer deposition may then be performed utilizing two or more precursors to develop spacer material 620. The precursors of the deposition may include multiple precursors, including a silicon-containing precursor and a precursor configured to interact with the moieties terminating the second self-assembled monolayer, but not the first self-assembled monolayer. For example, when hydrophilic and hydrophobic terminating monolayers are utilized, one of the atomic layer deposition precursors may include water. In this way, the deposition may not form over the first self-assembled monolayer, which may be hydrophobic. If the spacer material includes an oxide, such as silicon oxide or silicon oxycarbide, the precursors used in the atomic layer deposition may include a silicon-containing precursor as well as water. The water may then fail to interact with the first self-assembled monolayer formed over the second silicon- containing material, and dielectric materials during the half reaction with water, and thus the deposition will not form over the first self-assembled monolayer. In this way, the spacer material 620 may be selectively formed over the first silicon-containing material 611 without a mask layer being formed that may be chemically etched. [0077] After spacer material 620 has been formed to a suitable tnicKness, tne rirst sen- assembled monolayer may be exposed to UV light and removed from the substrate.

Accordingly, the first self-assembled monolayer may be formed directly subsequent the selective etch of the silicon-containing, or after transfer to an additional chamber but before additional process operations, and an additional masking layer that requires chemical removal or etching may not be utilized on the structure. Similarly an etch of spacer material 620, which may also require additional masking, may not be necessary subsequent the selective deposition to ensure the spacer material 620 is formed selectively over the silicon-containing material. In this way, multiple operations utilized in conventional formation may be obviated, which may reduce queue times significantly, such as by hours.

[0078] Embodiments may also utilize an inhibitor to form spacer material 620 selectively over first silicon-containing material 611, while not forming spacer material 620 over cap material 607 and dielectric material 609. For example, a sprayed inhibitor may be applied across a surface of the substrate, which may apply along a top surface of the substrate, but which may not penetrate within recessed portions of the substrate. The inhibitor may be any number of materials that may be characterized by a siloxane backbone, such as silicone, or a

tetrafluoroethylene backbone, such as PTFE, along with other oil or surfactant materials. The material may be applied across the surface of the substrate to cover exposed portions of cap material 607 and dielectric material 609. By use of a spray or coating application, the material may not be applied within recessed portions of the substrate, and may not contact first silicon- containing material 611. Spacer material 620 may then be formed, such as by atomic layer deposition or other vapor deposition or physical deposition mechanisms.

[0079] The inhibitor material may prevent adhesion or adsorption of the material, which may form or deposit normally on first silicon-containing material 611. Subsequent formation of spacer material 620, a removal agent may be applied to the substrate to remove the inhibitor material. The removal agent may be a wet etchant, reactant, or surfactant cleanser that may remove residual inhibitor material exposing the underlying gate structure. Accordingly, the inhibitor may be applied directly subsequent the selective etch, or subsequent transfer of the substrate, but prior to other process operations affecting the substrate. Utilizing an inhibitor may allow formation of the spacer material in a defined region that need not be defined via subsequent patterning and/or etching of a blanket film. By removing prior ana suosequent patterning operations, the processes may further reduce queue times over conventional processes.

[0080] The inhibitor may also be a product of a plasma application that may neutralize or render inert a surface of the substrate. For example, a modifying plasma may be formed from one or more precursors, which may include inert precursors. The plasma may be applied to a surface of the substrate, which may alter a top surface of a substrate, but which may not penetrate within recessed portions of the substrate. For example, a nitrogen-containing precursor, which may be nitrogen, may be delivered to a plasma processing region of a processing chamber, where a plasma is generated. The plasma effluents, which may include nitrogen-containing plasma effluents, may be delivered to a substrate, and may form a nitrogenized surface along the exposed portions of the substrate along a top surface, which may include cap material 607 and dielectric material 609.

[0081] The plasma effluents may not be delivered, or may not flow, within recessed portions of the substrate, which may maintain a neat or unreacted surface of first silicon-containing material 61 1. Spacer material 620 may then be formed with one or more deposition techniques, which may include atomic layer deposition or other vapor or physical deposition. For example, an atomic layer deposition technique may be utilized subsequent processing with the plasma effluents. After each cycle of the deposition, a nitrogen-containing plasma may be reapplied to a surface region of the substrate, such as over cap material 607 and dielectric material 609. In this way, the surface of cap material 607 and dielectric material 609 may be passivated to prevent or limit formation of spacer material 620 over those regions. Utilizing these plasma effluents on non-recessed portions of the substrate may allow formation of the spacer material in a defined region that need not be defined via subsequent patterning and/or etching of a blanket film. By removing prior and subsequent patterning operations, the processes may further reduce queue times over conventional processes. Additionally, the deposition may occur on both first and second silicon-containing materials, but may occur at a faster rate on first silicon-containing material, which may allow a subsequent etch similar to previously described to then remove excess spacer material from the exterior of second silicon-containing material.

[0082] Any of these techniques may selectively deposit or form dielectric or insulative materials over a semiconductor-containing region relative to one or more other semiconductor, dielectric, or insulative regions. The selectivity may be complete in mat tne spacer material forms only over first silicon-containing material 61 1, or an intervening layer, and spacer material may not form at all over cap material 607 and dielectric material 609 regions. In other embodiments the selectivity may not be complete, and may be in a ratio of deposition on semiconductor-containing materials relative to dielectric or insulative materials greater than about 2: 1. The selectivity may also be greater than or about 5: 1, greater than or about 10: 1, greater than or about 15: 1, greater than or about 20 : 1 , greater than or about 25 : 1, greater than or about 30: 1, greater than or about 35: 1, greater than or about 40: 1, greater than or about 45: 1, greater than or about 50: 1, greater than or about 75 : 1, greater than or about 100: 1, greater than or about 200: 1, or more. The spacer material may be formed to a thickness described previously, which may be less than or about 50 nm, and may be less than or about 40 nm, less than or about 30 nm, less than or about 20 nm, less than or about 10 nm, less than or about 5 nm, or less. Accordingly, selectivities below 50: 1 may be acceptable to fully deposit spacer material 620 while forming a limited amount or essentially not forming material over the cap material 607 and dielectric material 609.

[0083] The deposition operations may be performed at any of the temperature or pressures previously described, and may be performed at temperatures greater than or about 50° C, and may be performed greater than or about 100° C, greater than or about 150° C, greater than or about 200° C, greater than or about 250° C, greater than or about 300° C, greater than or about 350° C, greater than or about 400° C, greater than or about 450° C, greater than or about 500° C, greater than or about 600° C, greater than or about 700° C, greater than or about 800° C, or higher. For example, temperatures greater than or about 400° C may be utilized during atomic layer deposition operations in order to activate precursors to interact with one another as layers of material are being formed. [0084] Method 500 may be performed without any RJE processes or associated processes, which may better maintain components of the spacer material and preserve the low-k of the spacer material. Similarly the method may reduce queue times by removing many patterning and removal operations that may be performed prior to, during, or subsequent to formation in conventional processes. By utilizing the present technology, fabrication may be performed with more selective formation and removal over conventional techniques, wnicn may protect materials being formed and may reduce queue times by hours over conventional processes.

[0085] In the preceding description, for the purposes of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. It will be apparent to one skilled in the art, however, that certain embodiments may be practiced without some of these details, or with additional details.

[0086] Having disclosed several embodiments, it will be recognized by those of skill in the art that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the embodiments. Additionally, a number of well-known processes and elements have not been described in order to avoid unnecessarily obscuring the present technology. Accordingly, the above description should not be taken as limiting the scope of the technology.

[0087] Where a range of values is provided, it is understood that each intervening value, to the smallest fraction of the unit of the lower limit, unless the context clearly dictates otherwise, between the upper and lower limits of that range is also specifically disclosed. Any narrower range between any stated values or unstated intervening values in a stated range and any other stated or intervening value in that stated range is encompassed. The upper and lower limits of those smaller ranges may independently be included or excluded in the range, and each range where either, neither, or both limits are included in the smaller ranges is also encompassed within the technology, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.

[0088] As used herein and in the appended claims, the singular forms "a", "an", and "the" include plural references unless the context clearly dictates otherwise. Thus, for example, reference to "a layer" includes a plurality of such layers, and reference to "the precursor" includes reference to one or more precursors and equivalents thereof known to those skilled in the art, and so forth.

[0089] Also, the words "comprise(s)", "comprising", "contain(s)", "containing", "include(s)", and "including", when used in this specification and in the following claims, are intended to specify the presence of stated features, integers, components, or operations, out tney ao not preclude the presence or addition of one or more other features, integers, components, operations, acts, or groups.