RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Application No. 62/487,723, filed April 20, 2017, the disclosure of which is hereby incorporated by reference in its entirety for all purposes.

TECHNICAL FIELD

[0002] The present technology relates to semiconductor systems, processes, and equipment. More specifically, the present technology relates to systems and methods for selectively etching and selectively depositing material layers on a semiconductor device.

BACKGROUND

[0003] Integrated circuits are made possible by processes which produce intricately patterned material layers on substrate surfaces. Producing patterned material on a substrate requires controlled methods for removal of exposed material. Chemical etching is used for a variety of purposes including transferring a pattern in photoresist into underlying layers, thinning layers, or thinning lateral dimensions of features already present on the surface. Often it is desirable to have an etch process that etches one material faster than another facilitating, for example, a pattern transfer process or individual material removal. Such an etch process is said to be selective to the first material. As a result of the diversity of materials, circuits, and processes, etch processes have been developed with a selectivity towards a variety of materials. Deposition processes, however, continue to be performed across substrates generally utilizing a blanket coat or a conformal fill.

[0004] As device sizes continue to shrink in next-generation devices, selectivity may play a larger role when only a few nanometers of material are formed in a particular layer, especially when the material is critical in the transistor formation. Many different etch process selectivities have been developed between various materials, although standard selectivities may no longer be suitable at current and future device scale. Additionally, queue times for processes continue to rise based on the number of masking, formation, and removal operations needed to form and protect the various critical dimensions of features across a device while patterning and formation are performed elsewhere on a substrate.

[0005] Thus, there is a need for improved systems and methods that can be used to produce high quality devices and structures. These and other needs are addressed by the present technology.

SUMMARY

[0006] Processing methods may be performed to form semiconductor structures that may include spacer materials on dielectric materials. The methods may include depositing a first dielectric material on a silicon element on a semiconductor substrate. The first dielectric material may be selectively deposited on the silicon element relative to exposed regions of a second dielectric material. The methods may also include selectively etching the silicon element from the semiconductor substrate.

[0007] In some embodiments, the first dielectric material may include silicon nitride. The depositing may include an atomic layer deposition process. The second dielectric material may be or include silicon oxide. The methods may also include selectively recessing the first dielectric material about the silicon element. The recessing may remove a top portion of the first dielectric material relative to the second dielectric material. Selectively etching the silicon element may be performed with a selectivity to the first dielectric material greater than or about 20: 1. Selectively etching the silicon element may be performed with a selectivity to the second dielectric material greater than or about 100: 1. The first dielectric material deposition may be performed with a selectivity towards the silicon element relative to the second dielectric material greater than or about 2: 1. The first dielectric material may include a spacer characterized by a width of less than 20 nm. [0008] The present technology may also include methods of forming a semiconductor structure. The methods may include exposing a surface of a silicon-containing element to an inhibitor. The methods may include depositing an oxygen-containing material on the silicon- containing element extending from a semiconductor substrate. The oxygen-containing material may be selectively deposited on the silicon-containing element relative to exposed regions of a mask layer on a substrate. The methods may also include selectively etching the oxygen- containing material from the silicon element.

[0009] In some embodiments, the inhibitor may reduce formation of the oxygen-containing material on the surface of the silicon-containing element. The surface of the silicon-containing element may be a top surface of the silicon-containing element. The mask layer may include silicon oxide or silicon nitride. The methods may also include selectively recessing the oxygen- containing material about the silicon-containing element. The recessing may remove a top portion of the oxygen-containing material relative to the mask layer. Selectively etching the silicon-containing element may be performed with a selectivity to the oxygen-containing material greater than or about 100: 1. Selectively etching the silicon-containing element may be performed with a selectivity to the mask layer greater than or about 20: 1. The oxygen-containing material deposition may be performed with a selectivity towards the silicon-containing element relative to the mask layer greater than or about 2: 1. The oxygen-containing material may include a spacer characterized by a width of less than 20 nm. [0010] Such technology may provide numerous benefits over conventional systems and techniques. For example, the processes may protect critical dimensions by utilizing techniques that do not include a reactive ion etch, and provide improved selectivity. Additionally, by performing selective operations, spacer characteristics may be more uniform between spacers, which may reduce pitch walking. These and other embodiments, along with many of their advantages and features, are described in more detail in conjunction with the below description and attached figures.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] A further understanding of the nature and advantages of the disclosed technology may be realized by reference to the remaining portions of the specification and the drawings.

[0012] FIG. 1 shows a top plan view of an exemplary processing system according to embodiments of the present technology.

[0013] FIG. 2A shows a schematic cross-sectional view of an exemplary processing chamber according to embodiments of the present technology. [0014] FIG. 2B shows a detailed view of an exemplary faceplate according to embodiments of the present technology.

[0015] FIG. 3 shows a bottom plan view of an exemplary showerhead according to

embodiments of the present technology. [0016] FIG. 4 shows a schematic cross-sectional view of an exemplary processing chamber according to embodiments of the present technology.

[0017] FIG. 5 shows selected operations in a method of forming a semiconductor structure according to embodiments of the present technology.

[0018] FIGS. 6A-6C show schematic cross-sectional views of exemplary substrates according to embodiments of the present technology.

[0019] Several of the figures are included as schematics. It is to be understood that the figures are for illustrative purposes, and are not to be considered of scale unless specifically stated to be of scale. Additionally, as schematics, the figures are provided to aid comprehension and may not include all aspects or information compared to realistic representations, and may include exaggerated material for illustrative purposes.

[0020] In the appended figures, similar components and/or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a letter that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the letter.

DETAILED DESCRIPTION

[0021] The present technology includes systems and components for semiconductor processing of small pitch features. As line pitch is reduced, standard lithography processes may be limited, and alternative mechanisms may be used in patterning. During one such patterning operation, nitride spacers may be formed over an oxide surface. In one formation scenario, the nitride layer is deposited over dummy polysilicon lines and over a pad oxide. To form the nitride spacers, an etching process is performed that may remove the continuity of the nitride layer as well as the polysilicon. To ensure that the nitride has been fully removed between the spacers, an overetch is often performed. However, such a process may sputter the underlying pad oxide, which may be re-deposited along the nitride spacers' sidewalls as a footing. If this footing is not removed, the line thickness between the cores and gaps may differ, which may cause pitch walking in later processes. The removal processes used conventionally include a reactive ion etching ("RTE"), which may have reduced selectivity to many of the components. This may also cause rounding and removal of the spacer material itself, which can further exacerbate pitch walking when the spacers may no longer have uniform height, width, or other characteristics. Moreover, when materials exposed to the RIE contain carbon, such as low-k dielectrics, the associated ashing process may scavenge carbon from the dielectrics, reducing the dielectric capabilities.

[0022] Conventional technologies have struggled with these issues, which may occur in many instances during fabrication. For example, mandrel and sidewall spacer formation may be produced in front end of line and back end of line processes including with passes of self-aligned patterning, fin spacers, dummy gate spacers, and metallization, to name a few. As each of these processes may further produce and contribute to spacer irregularities, improved processes are needed that include improved selectivity, and improved spacer profiles.

[0023] The present technology overcomes these issues by utilizing selective etch processes performed in particular equipment, and the processes may be utilized to etch at higher selectivity than conventional RIE, which may allow additional patterning operations that may not previously have been capable, and may provide additional protection to critical feature dimensions such as the thin spacer profiles. By performing selective deposition operations in particular equipment, protection of the surrounding features may be possible during spacer formation and mandrel removal. These processes may enable reduced processing, while producing more uniform structures across the substrate. [0024] Although the remaining disclosure will routinely identify specific etching and deposition processes utilizing the disclosed technology, it will be readily understood that the systems and methods are equally applicable to a variety of other etching, deposition, and cleaning processes as may occur in the described chambers. Accordingly, the technology should not be considered to be so limited as for use with the described etching and deposition processes alone. The disclosure will discuss one possible system and chambers that can be used with the present technology to perform certain of the removal and deposition operations before describing operations of an exemplary process sequence according to the present technology.

[0025] FIG. 1 shows a top plan view of one embodiment of a processing system 100 of deposition, etching, baking, and curing chambers according to embodiments. In the figure, a pair of front opening unified pods (FOUPs) 102 supply substrates of a variety of sizes that are received by robotic arms 104 and placed into a low pressure holding area 106 before being placed into one of the substrate processing chambers 108a-f, positioned in tandem sections 109a- c. A second robotic arm 1 10 may be used to transport the substrate wafers from the holding area 106 to the substrate processing chambers 108a-f and back. Each substrate processing chamber 108a-f, can be outfitted to perform a number of substrate processing operations including the dry etch processes and selective deposition described herein in addition to cyclical layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), wet etch, pre-clean, degas, orientation, and other substrate processes.

[0026] The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing and/or etching a dielectric film on the substrate wafer. In one configuration, two pairs of the processing chambers, e.g., 108c-d and 108e-f, may be used to deposit dielectric material or metal-containing material on the substrate, and the third pair of processing chambers, e.g., 108a-b, may be used to etch the deposited dielectric. In another configuration, all three pairs of chambers, e.g., 108a-f, may be configured to etch a dielectric film on the substrate. Any one or more of the processes described may be carried out in chamber(s) separated from the fabrication system shown in different embodiments.

[0027] In some embodiments the chambers specifically include at least one etching chamber as described below as well as at least one deposition chamber as described below. By including these chambers in combination on the processing side of the factory interface, all etching and deposition processes discussed below may be performed in a controlled environment. For example, a vacuum environment may be maintained on the processing side of holding area 106, so that all chambers and transfers are maintained under vacuum in embodiments. This may also limit water vapor and other air components from contacting the substrates being processed. It will be appreciated that additional configurations of deposition, etching, annealing, and curing chambers for dielectric films are contemplated by system 100. [0028] FIG. 2A shows a cross-sectional view of an exemplary process chamber system 200 with partitioned plasma generation regions within the processing chamber. During film etching, e.g., titanium nitride, tantalum nitride, tungsten, cobalt, aluminum oxide, tungsten oxide, silicon, poly silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon oxy carbide, etc., a process gas may be flowed into the first plasma region 215 through a gas inlet assembly 205. A remote plasma system (RPS) 201 may optionally be included in the system, and may process a first gas which then travels through gas inlet assembly 205. The inlet assembly 205 may include two or more distinct gas supply channels where the second channel (not shown) may bypass the RPS 201, if included. [0029] A cooling plate 203, faceplate 217, ion suppressor 223, showerhead 225, and a substrate support 265, having a substrate 255 disposed thereon, are shown and may each be included according to embodiments. The pedestal 265 may have a heat exchange channel through which a heat exchange fluid flows to control the temperature of the substrate, which may be operated to heat and/or cool the substrate or wafer during processing operations. The wafer support platter of the pedestal 265, which may comprise aluminum, ceramic, or a combination thereof, may also be resistively heated in order to achieve relatively high temperatures, such as from up to or about 100°C to above or about 1100°C, using an embedded resistive heater element.

[0030] The faceplate 217 may be pyramidal, conical, or of another similar structure with a narrow top portion expanding to a wide bottom portion. The faceplate 217 may additionally be flat as shown and include a plurality of through-channels used to distribute process gases.

Plasma generating gases and/or plasma excited species, depending on use of the RPS 201, may pass through a plurality of holes, shown in FIG. 2B, in faceplate 217 for a more uniform delivery into the first plasma region 215. [0031] Exemplary configurations may include having the gas inlet assembly 205 open into a gas supply region 258 partitioned from the first plasma region 215 by faceplate 217 so that the gases/species flow through the holes in the faceplate 217 into the first plasma region 215.

Structural and operational features may be selected to prevent significant backflow of plasma from the first plasma region 215 back into the supply region 258, gas inlet assembly 205, and fluid supply system 210. The faceplate 217, or a conductive top portion of the chamber, and showerhead 225 are shown with an insulating ring 220 located between the features, which allows an AC potential to be applied to the faceplate 217 relative to showerhead 225 and/or ion suppressor 223. The insulating ring 220 may be positioned between the faceplate 217 and the showerhead 225 and/or ion suppressor 223 enabling a capacitively coupled plasma (CCP) to be formed in the first plasma region. A baffle (not shown) may additionally be located in the first plasma region 215, or otherwise coupled with gas inlet assembly 205, to affect the flow of fluid into the region through gas inlet assembly 205.

[0032] The ion suppressor 223 may comprise a plate or other geometry that defines a plurality of apertures throughout the structure that are configured to suppress the migration of ionically- charged species out of the first plasma region 215 while allowing uncharged neutral or radical species to pass through the ion suppressor 223 into an activated gas delivery region between the suppressor and the showerhead. In embodiments, the ion suppressor 223 may comprise a perforated plate with a variety of aperture configurations. These uncharged species may include highly reactive species that are transported with less reactive carrier gas through the apertures. As noted above, the migration of ionic species through the holes may be reduced, and in some instances completely suppressed. Controlling the amount of ionic species passing through the ion suppressor 223 may advantageously provide increased control over the gas mixture brought into contact with the underlying wafer substrate, which in turn may increase control of the deposition and/or etch characteristics of the gas mixture. For example, adjustments in the ion concentration of the gas mixture can significantly alter its etch selectivity, e.g., SiNx:SiOx etch ratios, Si:SiOx etch ratios, etc. In alternative embodiments in which deposition is performed, it can also shift the balance of conformal-to-flowable style depositions for dielectric materials.

[0033] The plurality of apertures in the ion suppressor 223 may be configured to control the passage of the activated gas, i.e., the ionic, radical, and/or neutral species, through the ion suppressor 223. For example, the aspect ratio of the holes, or the hole diameter to length, and/or the geometry of the holes may be controlled so that the flow of ionically-charged species in the activated gas passing through the ion suppressor 223 is reduced. The holes in the ion suppressor 223 may include a tapered portion that faces the plasma excitation region 215, and a cylindrical portion that faces the showerhead 225. The cylindrical portion may be shaped and dimensioned to control the flow of ionic species passing to the showerhead 225. An adjustable electrical bias may also be applied to the ion suppressor 223 as an additional means to control the flow of ionic species through the suppressor.

[0034] The ion suppressor 223 may function to reduce or eliminate the amount of ionically charged species traveling from the plasma generation region to the substrate. Uncharged neutral and radical species may still pass through the openings in the ion suppressor to react with the substrate. It should be noted that the complete elimination of ionically charged species in the reaction region surrounding the substrate may not be performed in embodiments. In certain instances, ionic species are intended to reach the substrate in order to perform the etch and/or deposition process. In these instances, the ion suppressor may help to control the concentration of ionic species in the reaction region at a level that assists the process.

[0035] Showerhead 225 in combination with ion suppressor 223 may allow a plasma present in first plasma region 215 to avoid directly exciting gases in substrate processing region 233, while still allowing excited species to travel from chamber plasma region 215 into substrate processing region 233. In this way, the chamber may be configured to prevent the plasma from contacting a substrate 255 being etched. This may advantageously protect a variety of intricate structures and films patterned on the substrate, which may be damaged, dislocated, or otherwise warped if directly contacted by a generated plasma. Additionally, when plasma is allowed to contact the substrate or approach the substrate level, the rate at which oxide species etch may increase. Accordingly, if an exposed region of material is oxide, this material may be further protected by maintaining the plasma remotely from the substrate.

[0036] The processing system may further include a power supply 240 electrically coupled with the processing chamber to provide electric power to the faceplate 217, ion suppressor 223, showerhead 225, and/or pedestal 265 to generate a plasma in the first plasma region 215 or processing region 233. The power supply may be configured to deliver an adjustable amount of power to the chamber depending on the process performed. Such a configuration may allow for a tunable plasma to be used in the processes being performed. Unlike a remote plasma unit, which is often presented with on or off functionality, a tunable plasma may be configured to deliver a specific amount of power to the plasma region 215. This in turn may allow

development of particular plasma characteristics such that precursors may be dissociated in specific ways to enhance the etching profiles produced by these precursors. [0037] A plasma may be ignited either in chamber plasma region 215 above showerhead 225 or substrate processing region 233 below showerhead 225. In embodiments, the plasma formed in substrate processing region 233 may be a DC biased plasma formed with the pedestal acting as an electrode. Plasma may be present in chamber plasma region 215 to produce the radical precursors from an inflow of, for example, a fluorine-containing precursor or other precursor. An AC voltage typically in the radio frequency (RF) range may be applied between the conductive top portion of the processing chamber, such as faceplate 217, and showerhead 225 and/or ion suppressor 223 to ignite a plasma in chamber plasma region 215 during deposition. An RF power supply may generate a high RF frequency of 13.56 MHz but may also generate other frequencies alone or in combination with the 13.56 MHz frequency.

[0038] FIG. 2B shows a detailed view 253 of the features affecting the processing gas distribution through faceplate 217. As shown in FIGS. 2A and 2B, faceplate 217, cooling plate 203, and gas inlet assembly 205 intersect to define a gas supply region 258 into which process gases may be delivered from gas inlet 205. The gases may fill the gas supply region 258 and flow to first plasma region 215 through apertures 259 in faceplate 217. The apertures 259 may be configured to direct flow in a substantially unidirectional manner such that process gases may flow into processing region 233, but may be partially or fully prevented from backflow into the gas supply region 258 after traversing the faceplate 217.

[0039] The gas distribution assemblies such as showerhead 225 for use in the processing chamber section 200 may be referred to as dual channel showerheads (DCSH) and are additionally detailed in the embodiments described in FIG. 3. The dual channel showerhead may provide for etching processes that allow for separation of etchants outside of the processing region 233 to provide limited interaction with chamber components and each other prior to being delivered into the processing region. [0040] The showerhead 225 may comprise an upper plate 214 and a lower plate 216. The plates may be coupled with one another to define a volume 218 between the plates. The coupling of the plates may be so as to provide first fluid channels 219 through the upper and lower plates, and second fluid channels 221 through the lower plate 216. The formed channels may be configured to provide fluid access from the volume 218 through the lower plate 216 via second fluid channels 221 alone, and the first fluid channels 219 may be fiuidly isolated from the volume 218 between the plates and the second fluid channels 221. The volume 218 may be fluidly accessible through a side of the gas distribution assembly 225.

[0041] FIG. 3 is a bottom view of a showerhead 325 for use with a processing chamber according to embodiments. Showerhead 325 may correspond with the showerhead 225 shown in FIG. 2A. Through-holes 365, which show a view of first fluid channels 219, may have a plurality of shapes and configurations in order to control and affect the flow of precursors through the showerhead 225. Small holes 375, which show a view of second fluid channels 221, may be distributed substantially evenly over the surface of the showerhead, even amongst the through-holes 365, and may help to provide more even mixing of the precursors as they exit the showerhead than other configurations.

[0042] Turning to FIG. 4 is shown a schematic cross-sectional view of an atomic layer deposition system 400 or reactor in accordance with one or more embodiments of the present technology. The system 400 may include a load lock chamber 10 and a processing chamber 20. The processing chamber 20 may be generally a sealable enclosure, which may be operated under vacuum, or at least low pressure. The processing chamber 20 may be isolated from the load lock chamber 10 by an isolation valve 15. The isolation valve 15 may seal the processing chamber 20 from the load lock chamber 10 in a closed position and may allow a substrate 60 to be transferred from the load lock chamber 10 through the valve to the processing chamber 20 and vice versa in an open position. [0043] The system 400 may include a gas distribution plate 30 capable of distributing one or more gases across a substrate 60. The gas distribution plate 30 may be any suitable distribution plate known to those skilled in the art, and specific gas distribution plates described should not be taken as limiting the scope of the technology. The output face of the gas distribution plate 30 may face the first surface 61 of the substrate 60. [0044] The gas distribution plate 30 may include a plurality of gas ports configured to transmit one or more gas streams to the substrate 60 and a plurality of vacuum ports disposed between each gas port and configured to transmit the gas streams out of the processing chamber 20. As illustrated in FIG. 4, the gas distribution plate 30 may include a first precursor injector 420, a second precursor injector 430 and a purge gas injector 440. The injectors 420, 430, 440 may be controlled by a system computer (not shown), such as a mainframe, or by a chamber-specific controller, such as a programmable logic controller. The precursor injector 420 may be configured to inject a continuous or pulse stream of a reactive precursor of compound A into the processing chamber 20 through a plurality of gas ports 425. The precursor injector 430 may be configured to inject a continuous or pulse stream of a reactive precursor of compound B into the processing chamber 20 through a plurality of gas ports 435. The purge gas injector 440 may be configured to inject a continuous or pulse stream of a non-reactive or purge gas into the processing chamber 20 through a plurality of gas ports 445. The purge gas may be configured to remove reactive material and reactive by-products from the processing chamber 20. The purge gas may typically be an inert gas, such as nitrogen, argon or helium. Gas ports 445 may be disposed in between gas ports 425 and gas ports 435 so as to separate the precursor of compound A from the precursor of compound B, thereby avoiding cross-contamination between the precursors.

[0045] In another aspect, a remote plasma source (not shown) may be connected to the precursor injector 420 and the precursor injector 430 prior to injecting the precursors into the processing chamber 20. The plasma of reactive species may be generated by applying an electric field to a compound within the remote plasma source. Any power source that is capable of activating the intended compounds may be used. For example, power sources using DC, radio frequency, and microwave based discharge techniques may be used. If an RF power source is used, it can be either capacitively or inductively coupled. The activation may also be generated by a thermally based technique, a gas breakdown technique, a high intensity light source, such as ultraviolet light, or exposure to an x-ray source.

[0046] The system 400 may further include a pumping system 450 connected to the processing chamber 20. The pumping system 450 may be generally configured to evacuate the gas streams out of the processing chamber 20 through one or more vacuum ports 455. The vacuum ports 455 may be disposed between each gas port so as to evacuate the gas streams out of the processing chamber 20 after the gas streams react with the substrate surface and to further limit cross- contamination between the precursors.

[0047] The system 400 may include a plurality of partitions 460 disposed on the processing chamber 20 between each port. A lower portion of each partition may extend close to the first surface 61 of substrate 60, such as, for example, about 0.5 mm or greater from the first surface 61. In this manner, the lower portions of the partitions 460 may be separated from the substrate surface by a distance sufficient to allow the gas streams to flow around the lower portions toward the vacuum ports 455 after the gas streams react with the substrate surface. Arrows 498 indicate the direction of the gas streams. Since the partitions 460 may operate as a physical barrier to the gas streams, they may also limit cross contamination between the precursors. The arrangement shown is merely illustrative and should not be taken as limiting the scope of the technology. It will be understood by those skilled in the art that the gas distribution system shown is merely one possible distribution system and that other types of showerheads may be employed.

[0048] In operation, a substrate 60 may be delivered, such as by a robot, to the load lock chamber 10 and may be placed on a shuttle 65. After the isolation valve 15 is opened, the shuttle 65 may be moved along the track 70. Once the shuttle 65 enters in the processing chamber 20, the isolation valve 15 may close, sealing the processing chamber 20. The shuttle 65 may then be moved through the processing chamber 20 for processing. In one embodiment, the shuttle 65 may be moved in a linear path through the chamber. [0049] As the substrate 60 moves through the processing chamber 20, the first surface 61 of substrate 60 may be repeatedly exposed to the precursor of compound A coming from gas ports 425 and the precursor of compound B coming from gas ports 435, with the purge gas coming from gas ports 445 in between. Injection of the purge gas may be designed to remove unreacted material from the previous precursor prior to exposing the substrate surface 61 to the next precursor. After each exposure to the various gas streams, the gas streams may be evacuated through the vacuum ports 455 by the pumping system 450. Since a vacuum port may be disposed on both sides of each gas port, the gas streams may be evacuated through the vacuum ports 455 on both sides. Thus, the gas streams may flow from the respective gas ports vertically downward toward the first surface 61 of the substrate 60, across the first surface 410 and around the lower portions of the partitions 460, and finally upward toward the vacuum ports 455. In this manner, each gas may be uniformly distributed across the substrate surface 61. Substrate 60 may also be rotated while being exposed to the various gas streams. Rotation of the substrate may be useful in preventing the formation of strips in the formed layers. Rotation of the substrate may be continuous or in discreet steps. [0050] The extent to which the substrate surface 61 is exposed to each gas may be determined by, for example, the flow rates of each gas coming out of the gas port and the rate of movement of the substrate 60. In one embodiment, the flow rates of each gas may be configured so as not to remove adsorbed precursors from the substrate surface 61. The width between each partition, the number of gas ports disposed on the processing chamber 20, and the number of times the substrate may be passed back and forth may also determine the extent to which the substrate surface 61 is exposed to the various gases. Consequently, the quantity and quality of a deposited film may be optimized by varying the above-referenced factors.

[0051] In another embodiment, the system 400 may include a precursor injector 420 and a precursor injector 430, without a purge gas injector 440. Consequently, as the substrate 60 moves through the processing chamber 20, the substrate surface 61 may be alternately exposed to the precursor of compound A and the precursor of compound B, without being exposed to purge gas in between.

[0052] The embodiment shown in FIG. 4 has the gas distribution plate 30 above the substrate. While the embodiments have been described and shown with respect to this upright orientation, it will be understood that the inverted orientation is also possible. In that situation, the first surface 61 of the substrate 60 may face downward, while the gas flows toward the substrate may be directed upward. In one or more embodiments, at least one radiant heat source 90 may be positioned to heat the second side of the substrate. [0053] In some embodiments, the shuttle 65 may be susceptor 66 for carrying the substrate 60. Generally, the susceptor 66 may be a carrier which helps to form a uniform temperature across the substrate. The susceptor 66 may be movable in both directions left-to-right and right-to-left, relative to the arrangement of FIG. 4, between the load lock chamber 10 and the processing chamber 20. The susceptor 66 may have a top surface 67 for carrying the substrate 60. The susceptor 66 may be a heated susceptor so that the substrate 60 may be heated for processing. As an example, the susceptor 66 may be heated by radiant heat source 90, a heating plate, resistive coils, or other heating devices, disposed underneath the susceptor 66. Although illustrated as a lateral transition, embodiments of system 400 may also be utilized in a rotationally based system in which a wheel may rotate clockwise or counter-clockwise to successively treat one or more substrates positioned under the gas distribution system illustrated. Additional modifications are similarly understood to be encompassed by the present technology.

[0054] FIG. 5 illustrates a method 500 of forming a semiconductor structure, many operations of which may be performed, for example, in the chambers 200 and 400 as previously described. Method 500 may include one or more operations prior to the initiation of the method, including front end processing, deposition, etching, polishing, cleaning, or any other operations that may be performed prior to the described operations. The method may include a number of optional operations as denoted in the figure, which may or may not specifically be associated with the method according to the present technology. For example, many of the operations are described in order to provide a broader scope of the structural formation, but are not critical to the technology, or may be performed by alternative methodology as will be discussed further below. Method 500 describes the operations shown schematically in FIGS. 6A-6C, the illustrations of which will be described in conjunction with the operations of method 500. It is to be understood that FIG. 6 illustrates only partial schematic views, and a substrate may contain any number of transistor sections having aspects as illustrated in the figures.

[0055] Method 500 may involve operations performed on a substrate having multiple exposed regions, such as on a substrate including regions to be further developed in producing a variety of structures as previously described. As illustrated in FIG. 6A, a portion of a processed substrate 600 is shown including a dielectric material 605 and silicon-containing materials 610. The silicon-containing materials 610 may include a variety of elements that may include placeholder or dummy elements, including mandrels or backbones, for later metal filling. The silicon-containing materials may have been previously formed, such as by depositing and etching mandrels of material. The recessing may have been performed in chamber 200, for example. Silicon-containing materials 610 may have been formed over previously deposited dielectric material 605. Dielectric material 605 may be a substrate material, or may be a layer overlying a substrate, such as a mask layer or etch stop layer.

[0056] The silicon-containing materials 610 may be characterized by a height above dielectric material 605, as well as a thickness of the elements. For example, the silicon-containing materials 610 may extend above dielectric material 605 greater than or about 5 nm, and may extend above dielectric material 605 up to or about 10 nm, up to or about 25 nm, up to or about 50 nm, up to or about 75 nm, up to or about 100 nm, up to or about 125 nm, up to or about 150 nm, up to or about 175 nm, up to or about 200 nm, up to or about 225 nm, up to or about 250 nm, or higher in various examples. The height may also be any range encompassed within any of these ranges. The silicon-containing materials 610 may also be less than or about 100 nm in width across each element, and in embodiments may be less than or about less than or about 90 nm, less than or about 80 nm, less than or about 70 nm, less than or about 60 nm, less than or about 50 nm, 40 nm, less than or about 30 nm, less than or about 25 nm, less than or about 20 nm, less than or about 15 nm, less than or about 10 nm, less than or about 5 nm, or less.

[0057] Method 500 may initially include forming a first dielectric material 615 about silicon- containing materials 610 at operation 505. As illustrated in FIG. 6B, first dielectric material 615 may be formed in a selective deposition in which the first dielectric material 615 may be formed preferentially on the silicon-containing materials 610 relative to exposed dielectric material 605, which may be a second dielectric material. The deposition may be performed in a chamber similar to chamber 400 described above. [0058] At optional operation 510, an etch back or removal of first dielectric material 615 may be performed along a top surface of the silicon-containing materials 610. The etch back may be a chemical mechanical polishing operation, or may involve a chemical etching, such as a plasma enhanced etching process in order to expose the silicon-containing materials 610. At operation 515, the silicon-containing materials 610 may be selectively removed from about first dielectric material 615. As illustrated in FIG. 6C, silicon-containing materials 610 may be removed from second dielectric material 605 and between successive first dielectric material 615. The resulting structure may provide successive spacer elements across the surface of the second dielectric material 605. By utilizing the methods discussed further below, the present technology may produce more uniform spacers, while minimizing damage to underlying second dielectric material 605.

[0059] Several of the deposition and etching operations may be performed within a single environment, such as shared on a cluster tool between chambers. For example, along with one or more etching chambers 200 and deposition chambers 400, may be additional deposition chambers, such as may be used for the fill of second dielectric material 605, for example. Each transfer may occur under vacuum, and the chambers may each reside on the same cluster tool to allow the transfer to occur in a controlled environment. For example, vacuum conditions may be maintained during the transfer, and the transfer can occur without breaking vacuum. As opposed to conventional technologies that may include additional masking operations, lithography, and other operations that may require transfer among many tools, method 500 may be performed on a single tool in which vacuum conditions are not broken in embodiments. Additionally, method 500 may not utilize any RIE operations, which may reduce polymer buildup and the necessary ashing and cleaning operations associated with RIE. RIE operations may also over etch the silicon-containing materials 610 because of reduced selectivity, which may gouge the second dielectric material 605. [0060] The present technology may also produce a flatter profile of first dielectric material 615 compared to previous technologies as well. Because of the low selectivity of RIE, the exposed top portion of first dielectric material 615 may be rounded or etched as well, which may produce dissimilar profiles of first dielectric materials. By utilizing a polishing or etching according to the present technology, a more flat and consistent profile may be produced spacer to spacer. This etch may maintain the height across the spacer for each individual spacer, and may produce a height variation of less than 10 nm across the spacer or between spacers. The height variation may also be limited to less than or about 9 nm, less than or about 8 nm, less than or about 7 nm, less than or about 6 nm, less than or about 5 nm, less than or about 4 nm, less than or about 3 nm, less than or about 2 nm, less than or about 1 nm, or may essentially produce a flat profile across the top of each spacer.

[0061] A variety of materials may be utilized in the processing, and the etching and deposition may be selective to multiple components. Accordingly, the present technology may not be limited to a single set of materials. For example, silicon-containing materials 610 may be silicon, such as polysilicon, and may also be other silicon-containing materials, including silicon nitride, and other nonmetals that may operate in the final structures, such as a placeholder for subsequent materials. Second dielectric material 605 may be or include silicon oxide, silicon nitride, titanium nitride, although other insulative materials and masking materials may be used. For example, other oxygen-containing, nitrogen-containing, or carbon-containing materials may be used. Second dielectric material 605 may be a high quality dielectric, such as a thermal oxide, for example, which may provide a relatively dense layer between other layers and materials. First dielectric material 615 may also include an insulative material, and may include a silicon- containing material, a nitrogen containing material, an oxygen-containing material, a carbon- containing material, or some combination of these materials, such as silicon nitride, silicon oxycarbide, titanium oxide, or other materials. [0062] When first dielectric material 615 includes carbon, such as with silicon oxycarbide or other low-k dielectrics, for example with dummy gate spacers, the present technology may include further benefits over conventional techniques. RIE processes subsequently perform ashing and cleaning to remove polymer residue from etched structures. When exposed materials also include carbon, or other materials sensitive to the operations, the ashing operations will scavenge carbon from the exposed materials as well. This may remove carbon doping, such as in low-k dielectrics, which can increase the dielectric constant of the material, rendering the material less suitable for its intended purpose, which may also affect device performance and resistance.

[0063] Because the second dielectric material 605 may be exposed during the selective deposition of the first dielectric material 615, the second dielectric material 605 may be a different material than the first dielectric material in embodiments, although the two materials may be similar in additional embodiments. Although being different materials, both first dielectric material 615 and second dielectric material 605 may be one or more materials selected from the group of materials including a carbon-containing material, a nitrogen-containing material, and an oxygen-containing material, and may be any of the materials noted above. However, the first dielectric material 615 may be a different material from that utilized for second dielectric material 605.

[0064] The selective deposition of first dielectric material 615 may be performed in a chamber capable of deposition, and which may be capable of atomic layer deposition, including chamber 400 as described above. The deposition may be premised on selectively depositing an insulative material on silicon-containing materials 610 relative to dielectric material 605. For example, the first dielectric material 615, which may be silicon nitride, silicon oxide, or some other oxide- containing material in some embodiments, may be formed substantially on silicon-containing materials 610, which may be silicon, while being minimally formed or limited from second dielectric material 605. The selective deposition may be performed by multiple operations, which may include formation of a self-assembled monolayer to facilitate selective deposition, or may include actively inhibiting formation of dielectric on other dielectric or semiconductor materials.

[0065] Self-assembled monolayers may be formed on regions of the structure to tune deposition. For example, a first self-assembled monolayer may be formed over the structure, and then exposed to a lithographic mask to remove the monolayer from silicon-containing materials 610. The monolayer may be maintained over second dielectric material 605. The monolayer may have termination moieties that may repel or fail to interact with later delivered precursors. For example, the termination moieties may be hydrophobic in embodiments, and may terminate with hydrogen-containing moieties, such as methyl groups, which may not interact with additional precursors. A second self-assembled monolayer may be formed over the silicon- containing materials 610, which may be hydrophilic or reactive with one or more precursors utilized to produce first dielectric material 615. The second self-assembled monolayer may be formed selectively over the silicon-containing materials 610, as the material may be repelled from the first self-assembled monolayer, or may be drawn selectively to the elements. The second self-assembled monolayer may terminate with hydroxyl or other hydrophilic moieties, or with moieties that interact specifically with additional precursors used to form first dielectric material 615.

[0066] An atomic layer deposition may then be performed utilizing two or more precursors to develop first dielectric material 615. The precursors of the deposition may include a metal- containing or silicon-containing precursor and a precursor configured to interact with the moieties terminating the second self-assembled monolayer, but not the first self-assembled monolayer. For example, when hydrophilic and hydrophobic terminating monolayers are utilized, one of the atomic layer deposition precursors may include water. In this way, the deposition may not form over the first self-assembled monolayer, which may be hydrophobic. If the first dielectric material includes a metal oxide, such as titanium oxide, the precursors used in the atomic layer deposition may include a titanium-containing precursor or some other metal- containing material, as well as water. In other embodiments silicon-containing precursors may be used instead of metal-containing material. The water may then fail to interact with the first self-assembled monolayer formed over the second dielectric material 605 during the half reaction with water, and thus the deposition may not form over the first self-assembled monolayer. In this way, the first dielectric material 615 may be selectively formed over the silicon-containing materials 610.

[0067] After first dielectric material 615 has been formed to a suitable height, the first self- assembled monolayer may be exposed to UV light and removed from the substrate, or some other removal may be performed. Accordingly, the first self-assembled monolayer may be formed directly subsequent the selective etch of the silicon-containing materials 610, or after transfer to an additional chamber but before additional process operations. In this way, multiple operations utilized in conventional formation may be obviated, which may reduce queue times significantly, such as by hours. In other embodiments a slight recess may be performed subsequent the selective deposition to remove residual material from second dielectric material 605, depending on the operations performed. It is to be understood that this is just an example of utilizing self-assembled monolayers based on one set of deposition materials. Additional materials which may be attributable to alternative precursors are discussed further below. [0068] Embodiments may also utilize an inhibitor to form first dielectric material 615 selectively over silicon-containing materials 610, while not forming first dielectric material 615 over second dielectric material 605, or forming limited amounts on dielectric material 605. For example, an inhibitor may be applied across a surface of the dielectric material, which may not be applied, or may be removed from silicon-containing materials 610. The inhibitor may also be applied across longitudinal surfaces, while maintaining vertical surfaces neat, which may allow material formation selective to vertical surfaces alone. The inhibitor may be any number of materials that may be characterized by a siloxane backbone, such as silicone, or a

tetrafluoroethylene backbone, such as PTFE, along with other oil or surfactant materials. The material may be applied across the surface of the substrate to cover exposed portions of dielectric material 605.

[0069] The inhibitor material may prevent adhesion or adsorption of the material, which may form or deposit normally on silicon-containing materials 610. Subsequent formation of first dielectric material 615, a removal agent may be applied to the substrate to remove the inhibitor material. The removal agent may be a wet etchant, reactant, or surfactant cleanser that may remove residual inhibitor material exposing the underlying dielectric material 605 or the top surface of silicon-containing materials 610. Utilizing an inhibitor may allow formation of the first dielectric material in a defined region that need not be defined via subsequent patterning and/or etching of a blanket film. By removing prior and subsequent patterning operations, the processes may further reduce queue times over conventional processes. [0070] The inhibitor may also be a product of a plasma application that may neutralize or render inert a surface of the substrate. For example, a modifying plasma may be formed from one or more precursors, which may include inert precursors. The plasma may be applied to a surface of the substrate, which may alter a top surface of silicon-containing materials 610 or second dielectric material 605, but which may not affect vertical surfaces of the silicon- containing materials 610. For example, a nitrogen-containing precursor, which may be nitrogen, may be delivered to a plasma processing region of a processing chamber, where a plasma is generated. The plasma effluents, which may include nitrogen-containing plasma effluents, may be delivered to a substrate, and may form a nitrogenized surface along the exposed portions of the silicon-containing materials 610 along a top surface. [0071] The plasma effluents may not be delivered, or may not flow, down to the level of second dielectric material 605. First dielectric material 615 may then be formed with one or more deposition techniques, which may include atomic layer deposition or other vapor or physical deposition. An additional blocking mechanism may also be applied to the second dielectric material relative to the sidewalls of silicon-containing materials 610, which may enable deposition only or predominantly along the sidewalls of silicon-containing materials 610. For example, an atomic layer deposition technique may be utilized subsequent processing with the plasma effluents. After each cycle of the deposition, a nitrogen-containing plasma may be reapplied to a surface region of the substrate, such as over silicon-containing materials 610. In this way, the surface of silicon-containing materials 610 may be passivated to prevent or limit formation of first dielectric material 615 over those regions. Utilizing these plasma effluents on non-recessed portions of the substrate may allow formation of the cap material in a defined region that need not be defined via subsequent patterning and/or etching of a blanket film. By removing prior and subsequent patterning operations, the processes may further reduce queue times over conventional processes. [0072] Additional selective deposition techniques may also be utilized that may include alternative mechanisms for selectively depositing a dielectric material such as a nitrogen- containing material. For example, a nitrogen-containing material may be utilized as one of the self-assembled monolayers on a material for which deposition is to occur, such as in one of the termination moieties of the monolayers, which may allow attraction of particular precursors used in the formation of one or more of the materials previously described. Still other techniques may utilize temperature differentials to enhance deposition on silicon relative to silicon oxide. For example, an atomic layer deposition utilizing a silicon-containing precursor and a nitrogen- containing precursor may be performed at temperatures above or about 500° C, and may be performed at temperatures above or about 750° C, above or about 900° C, above or about 1000° C, or up to, above, or about 1100° C.

[0073] As temperature is increased within this range, the deposition may occur on silicon at a higher rate than on silicon oxide. A selective etch of nitrogen may then be performed to remove the first dielectric material from the silicon oxide surface. Although the first dielectric material may also be reduced on the silicon surface, because the thickness may be many times greater than that on the silicon oxide, full removal from the silicon oxide may be performed while maintaining a thickness on the silicon-containing materials 610 greater than or about 1 nm, greater than or about 2 nm, greater than or about 3 nm, greater than or about 4 nm, greater than or about 5 nm, greater than or about 6 nm, greater than or about 7 nm, greater than or about 8 nm, greater than or about 9 nm, greater than or about 10 nm, or more. This effect may enable the present technology in ways that conventional technologies are limited. During normal conformal or blanket depositions, the thickness on some portions of the fin element would be equivalent to the thickness on the oxide layer. Accordingly, an etch back process may expose at least a portion of the fin element even with a directional etch. [0074] Any of these techniques may selectively deposit or form dielectric or insulative materials over silicon-containing materials 610 relative to one or more non-metal, dielectric, or insulative regions. Additionally, combinations may be utilized to adjust formation as well. For example, an inhibitor may be applied to a top surface of silicon-containing materials 610, or the top surfaces may be rendered inert, and then self-assembled monolayers may be utilized for the sidewalls of silicon-containing materials 610 and the second dielectric material 605. Other combinations of the described techniques may also be utilized and are encompassed by the present technology as well. The selectivity may be complete in that the first dielectric material forms only over silicon-containing materials 610, or an intervening layer, and first dielectric material 615 may not form at all over second dielectric material 605. [0075] In other embodiments the selectivity may not be complete, and may be in a ratio of deposition on silicon-containing materials 610 relative to dielectric material 605 greater than about 2: 1. The selectivity may also be greater than or about 5: 1, greater than or about 10: 1, greater than or about 15: 1, greater than or about 20: 1, greater than or about 25: 1, greater than or about 30: 1, greater than or about 35: 1, greater than or about 40: 1, greater than or about 45: 1, greater than or about 50: 1, greater than or about 75: 1, greater than or about 100: 1, greater than or about 200: 1, or more. As previously stated, the thickness of deposition on the silicon-containing materials 610 may be less than or about 20 nm, less than or about 10 nm, less than or about 5 nm, or less depending on the structure being produced. Accordingly, selectivities below 20: 1 may be acceptable to fully deposit first dielectric material 615 while forming a limited amount or essentially not forming material over the second dielectric material 605.

[0076] The deposition operations may be performed at any of the temperature or pressures previously described, and may be performed at temperatures greater than or about 300° C, and may be performed greater than or about 400° C, greater than or about 450° C, greater than or about 500° C, greater than or about 600° C, greater than or about 700° C, greater than or about 800° C, greater than or about 900° C, greater than or about 1,000° C, or higher. For example, temperatures greater than or about 500° C may be utilized during atomic layer deposition operations in order to activate precursors to interact with one another as layers of material are being formed.

[0077] The etching or recessing operations 510 and 515 may be selective etching operations as previously described, although operation 510 may not be performed depending on the selectivity of the deposition or the deposition technique performed. Additionally, polishing may be performed, such as a chemical mechanical polishing, to expose a top surface of silicon- containing materials 610. The dielectric materials and silicon-containing materials or mandrels may be recessed in an etching chamber similar to chamber 200 previously described. Once positioned within a processing region of the semiconductor processing chamber, the method may include forming a plasma of a fluorine-containing precursor in a remote plasma region of the processing chamber. The remote plasma region may be fluidly coupled with the processing region, although it may be physically partitioned to limit plasma at the substrate level, which may damage exposed structures or materials. Effluents of the plasma may be flowed into the processing region, where they may contact the semiconductor substrate and selectively etch the materials.

[0078] Both etching operations may involve additional precursors along with particular fluorine-containing precursors. Nitrogen trifluoride may be utilized to generate plasma effluents in some embodiments. Additional or alternative fluorine-containing precursors may also be utilized. For example, a fluorine-containing precursor may be flowed into the remote plasma region and the fluorine-containing precursor may include at least one precursor selected from the group consisting of atomic fluorine, diatomic fluorine, bromine trifluoride, carbon tetrafluoride, chlorine trifluoride, nitrogen trifluoride, hydrogen fluoride, sulfur hexafluoride, and xenon difluoride. The remote plasma region may be within a distinct module from the processing chamber or a compartment within the processing chamber. As illustrated in FIG. 2, both RPS unit 201 and first plasma region 215 may be utilized as the remote plasma region. An RPS may allow dissociation of plasma effluents without damage to other chamber components, while first plasma region 215 may provide a shorter path length to the substrate during which recombination may occur. [0079] An additional precursor may also be delivered to the remote plasma region to augment the fluorine-containing precursor. For example, during the etch of silicon-containing materials, an etch may be performed selective to silicon relative to silicon oxide, which may be second dielectric material 605. For example, a carbon-and-hydrogen-containing precursor or a hydrogen precursor may be delivered with the fluorine-containing precursor. The additional precursor may also be a fluorine-containing precursor, such as methyl fluoride, for example. The hydrogen- containing or carbon-and-hydrogen-containing precursor may be included to maintain a particular H:F atomic ratio for the plasma effluents. In embodiments the etching may be performed with an H:F ratio greater than 1, which may provide increased selectivity towards silicon relative to dielectric materials discussed above. The H:F atomic flow ratio may be maintained greater than or about 25: 1, and may be maintained greater than or about 30: 1, or greater than or about 40: 1 in embodiments, which may be controlled by adjusting relative flow rates of the fluorine-containing precursor and the hydrogen-containing precursor.

[0080] This process may selectively etch silicon relative to silicon oxide and silicon nitride by a ratio of greater than or about 70: 1. The etch selectivity may also be greater than or about 100: 1, greater than or about 150: 1, greater than or about 200: 1, greater than or about 250: 1 or greater than or about 300: 1 in disclosed embodiments, which may allow substantially or essentially maintaining first dielectric material 615 and second dielectric material 605 during the removal operation. In embodiments where either first dielectric material 615 or second dielectric material 605 includes titanium nitride or titanium oxide, the etch selectivity of silicon relative to the exposed metal-containing material may be greater than or about 100: 1, greater than or about 150: 1, greater than or about 200: 1, greater than or about 250: 1, greater than or about 500: 1, greater than or about 1000: 1, greater than or about 2000: 1 or greater than or about 3000: 1 in disclosed embodiments. In this way, the silicon mandrel or other silicon-containing material 610 may be completely removed with limited or essentially no removal of the other exposed materials on the substrate.

[0081] The selective etching of first dielectric material 615 may be performed relative to dielectric material 605 in order to remove residual first dielectric material 615, if present, and may use similar or different precursors from those used elsewhere. For example, although the materials may be any as described previously, first dielectric material 615 may be or include silicon nitride in an embodiment and dielectric material 605 may be or include silicon oxide. The selective etch of silicon nitride relative to silicon oxide may utilize a fluorine-containing precursor as previously described, and may also include an oxygen-containing precursor. The oxygen-containing precursor may be delivered to the remote plasma region with the fluorine- containing precursor, or the oxygen-containing precursor may bypass the remote plasma region and be delivered directly into the processing region.

[0082] In some embodiments, the first dielectric material etching operation may not include a hydrogen-containing precursor during the etch, and may be performed in a hydrogen-free environment. The operation may selectively etch silicon nitride relative to silicon oxide at a selectivity greater than or about 20: 1, and may etch silicon nitride at a selectivity greater than or about 30: 1. Because the amount of residual first dielectric material 615 that may be removed may be less than or about 10 nm, less than or about 5 nm, or less, etch rates below or about 20: 1 may still sufficiently remove the first dielectric material without substantial damage to the dielectric material 605. The etching may also be selective to silicon nitride relative to silicon, which may be the underlying silicon-containing materials 610. The selectivity may be greater than or about 10: 1, which may allow all residual first dielectric material 615 to be removed without substantially damaging silicon-containing materials 610, although etching of these materials may be acceptable when the subsequent operation involves removing the silicon- containing materials 610.

[0083] The etching operations may be performed below about 10 Torr in embodiments, and may be performed below or about 5 Torr in embodiments. The processes may also be performed at a temperature below about 100° C in embodiments, and may be performed below about 50° C. As performed in chamber 200, or a variation on this chamber, or in a different chamber capable of performing similar operations, the process may remove portions of first dielectric material 615 selective to second dielectric material 605. The operations may also remove portions of silicon- containing material 610 selective to first dielectric material 615 and second dielectric material 605.

[0084] Although the present technology in some embodiments may perform an etch back of the deposited silicon nitride to remove any residual nitride from the surface of dielectric material 605 and/or a top surface of silicon-containing materials 610, the thickness of first dielectric material 615 on sidewalls of silicon-containing materials 610 may be at least twice the thickness of the thickness of first dielectric material 615 on dielectric material 605 and/or a top surface of silicon-containing materials 610. Accordingly, the etch back process may fully remove residual first dielectric material 615 on dielectric material 605 while maintaining a complete coat on the sidewalls of silicon-containing materials 610 to any of the thicknesses previously described. In this way, the present technology may produce substantially or essentially uniform spacers over a dielectric material that has minimal or no removal from the formation processes. Additionally, for processes for which first dielectric material 615 includes carbon, the described processes may produce superior structures to conventional technologies that use RIE, and may scavenge carbon during the processing operations. [0085] In the preceding description, for the purposes of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. It will be apparent to one skilled in the art, however, that certain embodiments may be practiced without some of these details, or with additional details. [0086] Having disclosed several embodiments, it will be recognized by those of skill in the art that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the embodiments. Additionally, a number of well-known processes and elements have not been described in order to avoid unnecessarily obscuring the present technology. Accordingly, the above description should not be taken as limiting the scope of the technology.

[0087] Where a range of values is provided, it is understood that each intervening value, to the smallest fraction of the unit of the lower limit, unless the context clearly dictates otherwise, between the upper and lower limits of that range is also specifically disclosed. Any narrower range between any stated values or unstated intervening values in a stated range and any other stated or intervening value in that stated range is encompassed. The upper and lower limits of those smaller ranges may independently be included or excluded in the range, and each range where either, neither, or both limits are included in the smaller ranges is also encompassed within the technology, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.

[0088] As used herein and in the appended claims, the singular forms "a", "an", and "the" include plural references unless the context clearly dictates otherwise. Thus, for example, reference to "a layer" includes a plurality of such layers, and reference to "the precursor" includes reference to one or more precursors and equivalents thereof known to those skilled in the art, and so forth.

[0089] Also, the words "comprise(s)", "comprising", "contain(s)", "containing", "include(s)", and "including", when used in this specification and in the following claims, are intended to specify the presence of stated features, integers, components, or operations, but they do not preclude the presence or addition of one or more other features, integers, components, operations, acts, or groups.