TECHNICAL FIELD

[0001] This disclosure generally relates to integrated circuit structures, such as selectors for memory devices.

BACKGROUND

[0002] Modem electronics devices, such as non-volatile memories, may make use of various devices for the storage of bits of information. The memory devices can be distributed in arrays, for example, on the surface of the chip. One-bit memory cells can be grouped in small units called words which can be accessed together as a single memory address. Memory can be manufactured in a word length that is usually a power of two, for example, 1, 2, 4 or 8 bits.

BRIEF DESCRIPTION OF THE FIGURES

[0003] Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and wherein:

[0004] FIG. 1 shows a diagram of a selector, in accordance with one or more example embodiments of the disclosure.

[0005] FIG. 2 shows a memory element, in accordance with one or more example embodiments of the disclosure.

[0006] FIG. 3 shows an example plot of the current-voltage characteristics of a selector, in accordance with example embodiments of the disclosure.

[0007] FIG. 4 shows an example flow diagram for the fabrication of a selector, in accordance with one or more example embodiments of the disclosure.

[0008] FIG. 5 depicts an example of a system, in accordance with one or more example embodiments of the disclosure.

DETAILED DESCRIPTION

[0009] Embodiments of the disclosure are described more fully hereinafter with reference to the accompanying drawings, in which example embodiments of the disclosure are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like, but not necessarily the same or identical, elements throughout.

[0010] The following embodiments are described in sufficient detail to enable at least those skilled in the art to understand and use the disclosure. It is to be understood that other embodiments would be evident based on the present disclosure and that process, mechanical, material, dimensional, process equipment, and parametric changes may be made without departing from the scope of the present disclosure.

[0011] In the following description, numerous specific details are given to provide a thorough understanding of various embodiments of the disclosure. However, it will be apparent that the disclosure may be practiced without these specific details. In order to avoid obscuring the present disclosure, some well-known system configurations and process steps may not be disclosed in full detail. Likewise, the drawings showing embodiments of the disclosure are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and may be exaggerated in the drawings. In addition, where multiple embodiments are disclosed and described as having some features in common, for clarity and ease of illustration, description, and comprehension thereof, similar and like features will ordinarily be described with like reference numerals even if the features are not identical.

[0012] The term“horizontal” as used herein may be defined as a direction parallel to a plane or surface (for example, surface of a substrate), regardless of its orientation. The term “vertical,” as used herein, may refer to a direction orthogonal to the horizontal direction as just described. Terms, such as“on,”“above,”“below,”“bottom,”“top,”� �side” (as in“sidewall”), “higher,” “lower,” “upper,” “over,” and“under,” may be referenced with respect to a horizontal plane, where the horizontal plane can include an x-y plane, a x-z plane, or a y-z plane, as the case may be. The term“processing” as used herein includes deposition of material or photoresist, patterning, exposure, development, etching, cleaning, ablating, polishing, and/or removal of the material or photoresist as required in formation a described structure. The terms“perpendicular” and“parallel” can mean substantially perpendicular and parallel, respectively.

[0013]“An embodiment,”“various embodiments,” and the like indicate embodiment(s) so described may include particular features, structures, or characteristics, but not every embodiment necessarily includes the particular features, structures, or characteristics. Some embodiments may have some, all, or none of the features described for other embodiments. “First,”“second,”“third,” and the like describe a common object and indicate different instances of like objects are being referred to. Such adjectives do not imply objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner. “Connected” may indicate elements are in direct physical or electrical contact with each other and“coupled” may indicate elements co-operate or interact with each other, but they may or may not be in direct physical or electrical contact. Also, while similar or same numbers may be used to designate same or similar parts in different figures, doing so does not mean all figures including similar or same numbers constitute a single or same embodiment.

[0014] In various embodiments, disclosed herein are systems, methods, and apparatuses that generally relate to semiconductor devices. More particularly, some embodiments relate to memory devices, such as non-volatile memory (NVM) devices. Such memory devices, for example, can be incorporated into standalone memory devices, such as universal serial bus (USB) or other types of portable storage units, or integrated circuits (ICs), chips, such as microcontrollers or system on chips (SoCs). The devices or ICs can be incorporated into or used with, for example, consumer electronic products, or relate to other types of devices.

[0015] In various embodiments, disclosed herein are systems, methods, and apparatuses that are directed to a selector for use in connection with memory devices. In an embodiment, the selector can comprise a device that has current- voltage characteristics that are symmetric under opposing voltage biases. In an embodiment, selectors can be used in connection with a portion of a memory array, for example, in connection with wordlines and bitlines used in the memory array, and in connection with memory devices associated with the memory array. In an embodiment, the selector can turn a memory device, for example, an resistive memory device such as a spin-transfer torque memory (STTM) device, on or off. In an embodiment, one or more selector and memory devices can be used in a first portion between a wordline and bitline of a portion of a memory array referred to as a first deck, and one or more second selector and memory devices can be used in a second portion of the memory array between second wordline and bitline referred to as a second deck.

[0016] In an embodiment, the selector described herein can enable multideck stacking in a memory array, to be described further herein. In an embodiment, the selector can include an active layer, for example, an active layer comprising an insulator that can undergo a formation process in both positive and negative voltage polarizations, in a symmetric fashion. In an embodiment, the selector can have a device structure that includes a first electrode, a doping material, an active layer that can include an insulator comprising a dielectric, a second doping material, and a second electrode. [0017] In an embodiment, the first electrode can include an inert metal or a doped semiconductor. In an embodiment, the first electrode can include a platinum, gold, or similar material. Further examples of the conductive materials that may be used for first electrode include, but are not limited to, metals, for example, copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof, and the like.

[0018] In an embodiment, the first doping material can include a metal based layer, for example, a layer that include silver, gold, copper, titanium, or other metal. In an embodiment, the second doping material can include a metal based layer, for example, a layer that include silver, gold, copper, titanium, or other metal.

[0019] In an embodiment, the second electrode can include an inert metal or a doped semiconductor. In an embodiment, the second electrode can include a platinum, gold, or similar material. Further examples of the conductive materials that may be used for second electrode include, but are not limited to, metals, for example, copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof, and the like. In an embodiment, the first electrode and the second electrode can include substantially the same material, and can be fabricated using the same fabrication technique. In an embodiment, the first doping material and the second doping material can include substantially the same material, and can be fabricated using the same fabrication technique.

[0020] In an embodiment, the active layer can include an insulator. In an embodiment, the active layer can include a dielectric. In an embodiment, the active layer can include an oxide, for example, a hafnium oxide material. In one embodiment, the active layer can include a thin film transistor material. In an embodiment, the active layer can include an amorphous oxide semiconductor (AOS) film, a polycrystalline silicon film, an amorphous silicon film, a polycrystalline III-V semiconductor film, a polycrystalline germanium, an amorphous germanium, an organic film, a transition metal dichalcogenide (TMD) film, or any combination thereof. In another embodiment, the active layer can include an oxide film, for example, a binary oxide (for example, ruthenium oxide, titanium oxide, tantalum oxide), a ternary oxide (e.g., InZnGaO). [0021] In an embodiment, the first electrode and/or the second electrode can include more than one layer, for example, a first layer comprising a first metal, a second layer comprising a second metal, and so on. In an embodiment, the first doping material and/or the second doping material can include more than one layer, for example, a first layer including a first metal, a second layer including a second metal, and so on. In an embodiment, the active layer can include more than one layer, for example, a first layer including a first oxide, a second layer including a second oxide, and so on.

[0022] In an embodiment, the selector can be fabricated using back-end-of-line (BEOL) processing and fabrication techniques. In an embodiment, the first electrode of the selector can be fabricated using chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE) and the like. In an embodiment, the second electrode of the selector can be fabricated using CVD, PVD, PEVCD, ALD, MBE, and the like. In an embodiment, the first doping material of the selector can be fabricated using CVD, PVD, PEVCD, ALD, MBE, and the like. In an embodiment, the second doping material of the selector can be fabricated using CVD, PVD, PEVCD, ALD, MBE, and the like. In an embodiment, the active layer can be fabricated using CVD, PVD, PEVCD, ALD, MBE, and the like.

[0023] In an embodiment, the first electrode can have a thickness of approximately 10 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 200 nm. In an embodiment, the second electrode can have a thickness of approximately 10 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 200 nm. In an embodiment, the first doping material can have a thickness of approximately 1 nm to approximately 100 nm, with an example thickness of approximately 5 nm to approximately 25 nm. In an embodiment, the second doping material can have a thickness of approximately 1 nm to approximately 100 nm, with an example thickness of approximately 5 nm to approximately 25 nm. In an embodiment, the active layer can have a thickness of approximately 20 nm to approximately 400 nm, with an example thickness of approximately 30 nm to approximately 100 nm.

[0024] FIG. 1 shows a diagram of a selector 100 in accordance with one or more example embodiments of the disclosure. In one embodiment the selector 100 can include a first electrode 102. In an embodiment, the first electrode 102 can be similar, but not necessarily identical to, to a second electrode 110 (to be discussed further below), for example, in composition, thickness, and/or fabrication technique. In an embodiment, the first electrode 102 can include a metallic material. In an embodiment, the first electrode 102 can include an inert metal. In an embodiment, the metallic material can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the first electrode 102 can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the first electrode can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the first electrode 102 can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the first electrode 102 may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0025] In an embodiment the selector 100 can include a first doping material 104. In an embodiment, the first doping material 104 can include a metal, such as silver. In another embodiment, the first doping material 104 can include a thin layer of material which can at least partially dope a subsequently formed layer, such as an insulator 106, to be discussed further below. In an embodiment, the first doping material 104 can be similar, but not necessarily identical to, to a second doping material 108 (to be discussed further below), for example, in composition, thickness, and/or fabrication technique. In an embodiment, the first doping material 104 can include a metallic material, for example, gold, copper, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the first doping material 104 can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the first doping material 104 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the first doping material 104 can have a thickness of approximately 0.1 nm to approximately 100 nm, with an example thickness of approximately 1 nm to approximately 10 nm. In an embodiment, the first doping material 104 may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0026] In an embodiment the selector 100 can include an active layer 106 also referred to as an insulator 106. In another embodiment the insulator 106 can include an oxide. In one embodiment the insulator 106 can include a dielectric. In an embodiment, the insulator 106 can include a hafnium oxide, a silicon dioxide (SiO ₂ ), or a low-K material. In one embodiment, the insulator can be deposited using PVD, CVD, MOCVD, and/or ALD, and the like. In one embodiment, insulating layer comprises one or more oxide layers, e.g., a silicon oxide layer, a doped porous silicon oxide, an aluminum oxide, a carbon doped silicon oxide, other electrically insulating layer. In alternate embodiments, insulating layer 106 comprises organic materials, inorganic materials, or both. In one embodiment, the thickness of the insulating layer 106 is determined by an integrated circuit design. In an embodiment, the insulating layer 106 can have a thickness of approximately x nm to approximately y nm, with an example thickness of approximately x nm to approximately y nm.

[0027] In one embodiment the selector 100 can include a second doping material 108. In an embodiment, the second doping material 108 can include a metal, such as silver. In another embodiment, the second doping material 108 can include a thin layer of material which can at least partially dope a previously formed layer, such as an insulator 106, discussed above. In an embodiment, the second doping material 108 can be similar, but not necessarily identical to, to a first doping material 104 (discussed above), for example, in composition, thickness, and/or fabrication technique. In an embodiment, the second doping material 108 can include a metallic material, for example, gold, copper, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the second doping material 108 can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a- tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the second doping material 108 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the second doping material 108 can have a thickness of approximately 0.1 nm to approximately 100 nm, with an example thickness of approximately 1 nm to approximately 10 nm. In an embodiment, the second doping material 108 may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0028] In one embodiment the selector 100 can include a second electrode 110. In an embodiment, the second electrode 110 can be similar, but not necessarily identical to, to the first electrode 102 (discussed above), for example, in composition, thickness, and/or fabrication technique. In an embodiment, the second electrode 110 can include a metallic material. In an embodiment, the second electrode 110 can include an inert metal. In an embodiment, the metallic material can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the second electrode 110 can comprise a semi-metallic material. Non limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the second electrode 110 can comprise an intermetallic material. Non limiting examples include gold and aluminum intermetallic s, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the second electrode 110 can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the second electrode 110 may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0029] In an embodiment, the first electrode 102 and/or the second electrode 110 can include more than one layer, for example, a first layer comprising a first metal, a second layer comprising a second metal, and so on. In an embodiment, the first doping material 104 and/or the second doping material 108 can include more than one layer, for example, a first layer including a first metal, a second layer including a second metal, and so on. In an embodiment, the active layer 106 can include more than one layer, for example, a first layer including a first oxide, a second layer including a second oxide, and so on.

[0030] In an embodiment, the various layers, for example, the first electrode 102, the first doping layer 104, the active layer 106, the second electrode 108, and/or the second electrode 110 can be fabricated on a substrate (not shown). In one embodiment, the substrate can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres. In another embodiment, the substrate can include a silicon substrate. In one embodiment, the substrate can include a doped silicon substrate. In one embodiment, the substrate can be a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like. In one embodiment, the substrate can include a semiconductor material (e.g., monocrystalline silicon, germanium, silicon germanium, SiGe, and/or a TTT-V materials based material (e.g., gallium arsenide, GaAs), or any combination thereof).

[0031] In an embodiment, the substrate can include a flexible substrate. In various embodiments, the substrate can include a polymer based substrate, glass, or any other bendable substrate including 2D materials e.g., graphene and M0S2, organic materials e.g., pentacene, transparent oxides e.g., indium gallium zinc oxide (IGZO), polycrystalline III-V materials, polycrystalline Ge, polycrystalline Si, amorphous III-V materials, amorphous Ge, amorphous Si, or any combination thereof. In an embodiment, the amorphous III-V materials can have a deposition temperature lower than that of the polycrystalline III-V materials. In an embodiment, substrate can be, for example, an organic, a ceramic, a glass, or a semiconductor substrate. In one embodiment, the substrate comprises a semiconductor material, e.g., silicon (Si). In one embodiment, the substrate is a monocrystalline Si substrate.

[0032] In one embodiment, the substrate, for example, a silicon wafer can include a memory array periphery devices, for example, input/output devices. In an embodiment, placing the memory array periphery devices under the substrate can increase the memory array efficiency while reducing the memory array area consumption. In an embodiment, the substrate can include electronic devices, for example, transistors, memories, capacitors, resistors, optoelectronic devices, switches, any other active and passive electronic devices that are separated by electrically insulating layers, for example, interlayer dielectric layers, trench insulation layers, or any other insulating layers known to one of ordinary skill in the art of the electronic device manufacturing. In at least some embodiments, the substrate can include metal interconnects and vias configured to connect the metallization layers. In an embodiment, the substrate can be a semiconductor-on-isolator (SOI) substrate including a bulk lower substrate, a middle insulation layer, and a top monocrystalline layer. The top monocrystalline layer may comprise, for example, silicon.

[0033] FIG. 2 shows a memory element 200 in accordance with one or more example embodiments of the disclosure. In an embodiment the memory element 200 can be part of an array for memory. In another embodiment the memory element can be part of a chip or a plurality of chips.

[0034] In an embodiment the memory element 200 can include a first line 202. In another embodiment the memory element 200 can include a second line 204. In another embodiment the second line 204 can be substantially perpendicular to the first line 202. In one embodiment the memory element can include a third line 206. In another embodiment the third line 206 can be substantially perpendicular to the second line 204 and/or substantially parallel to the first line 202. In one embodiment the second line 204 can have an operating voltage of approximately 0 volts while the first line 202 and/or the third line 206 can have a positive applied voltage during operation. In such a configuration the memory element 200 can be in write state.

[0035] In an embodiment, the first line 202, the second line 204, and/or the third line 206 can include a conductive material. In an embodiment, the conductive materials used for the first line 202, the second line 204, and/or the third line 206can include, but are not limited to, metals, for example, copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof, and the like. In an embodiment, the first line 202, the second line 204, and/or the third line 206 can include a metallic material. In an embodiment, the first line 202, the second line 204, and/or the third line 206 can include an inert metal. In an embodiment, the metallic material can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the first line 202, the second line 204, and/or the third line 206 can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the first line 202, the second line 204, and/or the third line 206 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallic s, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the first line 202, the second line 204, and/or the third line 206 can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the first line 202, the second line 204, and/or the third line 206 may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0036] In one embodiment the memory element 200 can include a first selector 208. In another embodiment the first selector 208 can be a back-end selector, that is a selector that is fabricated using back-end-of-line (BEOL) processing. In one embodiment the memory element 200 can include a first memory device 210. In another embodiment the first memory device 210 can include a random-access memory, for example, a spin-transfer torque memory (STTM). In one embodiment the first selector 208 and the first memory device 210 can include a portion of the memory element 200 referred to as a first deck. In one embodiment the memory element 200 can include a second selector 212. In another embodiment the second selector 212 can be a back-end selector.

[0037] In one embodiment the memory element 200 can include a second memory device 214. In another embodiment the second memory device 214 can include a random-access memory, for example, an STTM. In one embodiment the second selector 212 and the second memory device 214 of the memory element 200 can include what is referred to as a second deck of the memory element 200.

[0038] In one embodiment the memory element 200 can include a substrate 220. In one embodiment, the substrate 220 can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres. In another embodiment, the substrate 220 can include a silicon substrate. In one embodiment, the substrate 220 can include a doped silicon substrate. In one embodiment, the substrate 220 can be a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like. In one embodiment, the substrate 220 can include a semiconductor material (e.g., monocrystalline silicon, germanium, silicon germanium, SiGe, and/or a III-V materials based material (e.g., gallium arsenide, GaAs), or any combination thereof).

[0039] In an embodiment, the substrate 220 can include a flexible substrate. In various embodiments, substrate 220 can include a polymer based substrate, glass, or any other bendable substrate including 2D materials e.g., graphene and M0S2, organic materials e.g., pentacene, transparent oxides e.g., indium gallium zinc oxide (IGZO), polycrystalline III-V materials, polycrystalline Ge, polycrystalline Si, amorphous III-V materials, amorphous Ge, amorphous Si, or any combination thereof. In an embodiment, the amorphous III-V materials can have a deposition temperature lower than that of the polycrystalline III-V materials. In an embodiment, substrate 220 can be, for example, an organic, a ceramic, a glass, or a semiconductor substrate. In one embodiment, substrate 220 comprises a semiconductor material, e.g., silicon (Si). In one embodiment, substrate 220 is a monocrystalline Si substrate.

[0040] In one embodiment, substrate 220, for example, a silicon wafer can include a memory array periphery devices, for example, input/output devices. In an embodiment, placing the memory array periphery devices under the substrate can increase the memory array efficiency while reducing the memory array area consumption. In an embodiment, the substrate 220 can include electronic devices, for example, transistors, memories, capacitors, resistors, optoelectronic devices, switches, any other active and passive electronic devices that are separated by electrically insulating layers, for example, interlayer dielectric layers, trench insulation layers, or any other insulating layers known to one of ordinary skill in the art of the electronic device manufacturing. In at least some embodiments, the substrate 220 can include metal interconnects and vias configured to connect the metallization layers. In an embodiment, substrate 220 can be a semiconductor-on-isolator (SOI) substrate including a bulk lower substrate, a middle insulation layer, and a top monocrystalline layer. The top monocrystalline layer may comprise, for example, silicon.

[0041] In one embodiment the memory element 200 can include a first electrode 222. In an embodiment, the first electrode 222 can be similar, but not necessarily identical to, to a second electrode 222 (to be discussed further below), for example, in composition, thickness, and/or fabrication technique. In an embodiment, the first electrode 222 can include a metallic material. In an embodiment, the first electrode 222 can include an inert metal. In an embodiment, the metallic material can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the first electrode 222 can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi- metallic materials may also be any mixtures of such materials. In various embodiments, the first electrode 222 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the first electrode 222 can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the first electrode 222 may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0042] In one embodiment the memory element 200 can include doped material 224. In an embodiment, the first doping material 224 can include a metal, such as silver. In another embodiment, the first doping material 224 can include a thin layer of material which can at least partially dope a subsequently formed layer, such as an insulator 226, to be discussed further. In an embodiment, the first doping material 224 can be similar, but not necessarily identical to, to a second doping material 228 (to be discussed further below), for example, in composition, thickness, and/or fabrication technique. In an embodiment, the metallic material can include gold, copper, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the first doping material 224 can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the first doping material 224 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallic s, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the first doping material 224 can have a thickness of approximately 0.1 nm to approximately 100 nm, with an example thickness of approximately 1 nm to approximately 10 nm. In an embodiment, the first doping material 224 may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0043] In one embodiment the memory element 200 can include an insulator 226. In another embodiment the insulator 226 can include an oxide. In one embodiment the insulator 226 can include a dielectric. In an embodiment, the insulator 226 can include a silicon dioxide (SiCk), or a low-K material. In an embodiment, the insulator 226 can have a thickness of approximately x nm to approximately y nm, with an example thickness of approximately x nm to approximately y nm. In one embodiment, the insulator can be deposited using PVD, CVD, MOCVD, and/or ALD, and the like.

[0044] In one embodiment the memory element 200 can include a doped material 228. In an embodiment, the second doping material 228 can include a metal, such as silver. In another embodiment, the second doping material 228 can include a thin layer of material which can at least partially dope a previously formed layer, such as an insulator 226, discussed above. In an embodiment, the second doping material 228 can be similar, but not necessarily identical to, to a first doping material 224 (discussed above), for example, in composition, thickness, and/or fabrication technique. In an embodiment, the metallic material can include gold, copper, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the second doping material 228 can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the second doping material 228 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallic s, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the second doping material 228 can have a thickness of approximately 0.1 nm to approximately 100 nm, with an example thickness of approximately 1 nm to approximately 10 nm. In an embodiment, the second doping material 228 may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0045] In one embodiment the memory element 200 can include a second electrode 230. In an embodiment, the second electrode 230 can be similar, but not necessarily identical to, to the first electrode 222 (discussed above), for example, in composition, thickness, and/or fabrication technique. In an embodiment, the second electrode 230 can include a metallic material. In an embodiment, the second electrode 230 can include an inert metal. In an embodiment, the metallic material can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the second electrode 230 can comprise a semi-metallic material. Non limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the second electrode 230 can comprise an intermetallic material. Non limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the second electrode 230 can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the second electrode 230 may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0046] In an embodiment, the First electrode 222 and/or the second electrode 230 can include more than one layer, for example, a first layer comprising a first metal, a second layer comprising a second metal, and so on. In an embodiment, the first doping material 224 and/or the second doping material 228 can include more than one layer, for example, a first layer including a first metal, a second layer including a second metal, and so on. In an embodiment, the active layer 226 can include more than one layer, for example, a first layer including a first oxide, a second layer including a second oxide, and so on.

[0047] In one embodiment the substrate 220, the first electrode 222, the first doping material 224, the active layer 226 (or insulator 226) and the second doping material 228 and the second electrode 230 can be part of the first selector 208 or the second selector 212, in the first deck or the second deck, respectively. In one embodiment the above layers can be substantially similar in order to generate a symmetric bipolar selector part of the memory element 200.

[0048] In one embodiment the memory element 200 can include a first memory electrode 232. In an embodiment, the first memory electrode 232 can be similar, but not necessarily identical to, to a second memory electrode 236 (discussed below), for example, in composition, thickness, and/or fabrication technique. In an embodiment, the first memory electrode 232 can include a metallic material. In an embodiment, the first memory electrode 232 can include an inert metal. In an embodiment, the metallic material can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the first memory electrode 232 can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the first memory electrode 232 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallic s, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the first memory electrode 232 can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the first memory electrode 232 may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0049] In one embodiment the memory element 200 can include a memory layer 234. In an embodiment, the memory layer 234 can include two or more layers (not shown). In one embodiment, each of the memory layer 234 can be an amorphous oxide semiconductor (AOS) film, a polycrystalline silicon film, an amorphous silicon film, a polycrystalline TTT-V semiconductor film, a polycrystalline germanium, an amorphous germanium, an organic film, a transition metal dichalcogenide (TMD) film, or any combination thereof. In one embodiment, each of the the memory layer 234 can be an oxide film, e.g., a binary oxide (e.g., ruthenium oxide, titanium oxide, tantalum oxide ), a ternary oxide (e.g., InZnGaO).

[0050] In one embodiment the memory element 200 can include a second memory electrode 236. In one embodiment the first memory electrode 232, the memory layer 234 and the second memory electrode 236 can be part of the first memory device 210 and the second memory device 214 respectively, as part of the memory element 200. In an embodiment, the second memory electrode 236 can be similar, but not necessarily identical to, to the first memory electrode 232 (discussed above), for example, in composition, thickness, and/or fabrication technique. In an embodiment, the second memory electrode 236 can include a metallic material. In an embodiment, the second memory electrode 236 can include an inert metal. In an embodiment, the metallic material can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the second memory electrode 236 can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the second memory electrode 236 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the second memory electrode 236 can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the second memory electrode 236 may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like. [0051] FIG. 3 shows an example plot 300 of the current-voltage characteristics of a selector, in accordance with example embodiments of the disclosure. In an embodiment, the plot 300 is merely a representative plot of an example selector device, and does not represent idealized curves for the current-voltage (IV) characteristics 306 of such a device. In an embodiment, plot 300 shows a generally symmetric current-voltage characteristic for the example selector device. In an embodiment, a small level of asymmetry may exist in the current-voltage characteristics 306 when comparing the plot of current-voltage characteristics of the selector in forward bias versus the current-voltage characteristics of the selector in reverse bias, but the small asymmetry may vary from batch to batch and may not exist at all in some example devices. In an embodiment, the small asymmetry may be due to imperfect fabrication methods, for example, impurity levels in various deposition techniques.

[0052] In an embodiment, the selector can be similar to the selector device shown and described in connection with FIG. 1. In an embodiment, the plot 300 can include a y-axis 302 that represents the current flowing through the device in units of amperes. In an embodiment, the plot 300 can include an x-axis 304 that represents the voltage across the terminals of the selector in units of volts. In an embodiment, the plot 300 can include the current-voltage characteristics 306 (also referred to herein as curve 306) of a selector under different voltage biases. In an embodiment, section 310 of the curve 306 represents the forward-bias regime before the active layer of the selector switches states at approximately 0.6 volts. In an embodiment, in section 310 the selector in the forward-bias regime and is in an off state and a low current state (between approximately 10 ^-11 amps and approximately 10 ^-10 amps. In an embodiment, section 312 of the curve 306 represents the transition state of the selector from an off-state (high resistance state) to an on-state (low-resistance state), where it can conduct a high current level. In an embodiment, section 314 of the curve 306 represents the on-state or the high current conduction state of the selector operating in the forward-bias regime and at a low-resistance state, where it can conduct a high current level on the order of approximately 10 ^-6 amps. In an embodiment, section 328 of the curve 306 represents another transition state of the selector from the on-state (low resistance state) to the off-state (high-resistance state), where it can conduct a low current level.

[0053] In an embodiment, section 320 of the curve 306 represents the reverse-bias regime before the active layer of the selector switches states at approximately -0.5 volts. In an embodiment, in section 320 the selector is in the reverse-bias regime and at an off state and a low current state at approximately 10 ^-11 amps. In an embodiment, section 324 of the curve 306 represents the transition state of the selector from an off-state (high resistance state) to an on- state (low-resistance state), where it can conduct a high current level. In an embodiment, section 326 of the curve 306 represents the on- state or the high current conduction state of the selector operating in the reverse-bias regime and at a low-resistance state, where it can conduct a high current level on the order of approximately 10 ^-6 amps. In an embodiment, section 324 of the curve 306 represents another transition state of the selector from the on-state (low resistance state) to the off-state (high-resistance state), where it can conduct a low current level.

[0054] FIG. 4 shows an example flow diagram for the fabrication of a selector in accordance with one or more example embodiments of the disclosure. At block 402 a first electrode can be deposited, for example on a substrate. In an embodiment, the substrate can include a flexible substrate. In various embodiments, the substrate can include a polymer based substrate, glass, or any other bendable substrate including 2D materials e.g., graphene and M0S2, organic materials e.g., pentacene, transparent oxides e.g., indium gallium zinc oxide (IGZO), poly crystalline III-V materials, poly crystalline Ge, poly crystalline Si, amorphous TTT-V materials, amorphous Ge, amorphous Si, or any combination thereof. In an embodiment, the amorphous III-V materials can have a deposition temperature lower than that of the polycrystalline III-V materials. In an embodiment, substrate can be, for example, an organic, a ceramic, a glass, or a semiconductor substrate. In one embodiment, the substrate comprises a semiconductor material, e.g., silicon (Si). In one embodiment, the substrate is a monocrystalline Si substrate.

[0055] In one embodiment, the substrate, for example, a silicon wafer can include a memory array periphery devices, for example, input/output devices. In an embodiment, placing the memory array periphery devices under the substrate can increase the memory array efficiency while reducing the memory array area consumption. In an embodiment, the substrate can include electronic devices, for example, transistors, memories, capacitors, resistors, optoelectronic devices, switches, any other active and passive electronic devices that are separated by electrically insulating layers, for example, interlayer dielectric layers, trench insulation layers, or any other insulating layers known to one of ordinary skill in the art of the electronic device manufacturing. In at least some embodiments, the substrate can include metal interconnects and vias configured to connect the metallization layers. In an embodiment, the substrate can be a semiconductor-on-isolator (SOI) substrate including a bulk lower substrate, a middle insulation layer, and a top monocrystalline layer. The top monocrystalline layer may comprise, for example, silicon. [0056] In an embodiment, the first electrode can be similar, but not necessarily identical to, to a second electrode (to be discussed further below), for example, in composition, thickness, and/or fabrication technique. In an embodiment, the first electrode can include a metallic material. In an embodiment, the first electrode can include an inert metal. In an embodiment, the metallic material can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the first electrode can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the first electrode can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the first electrode can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the first electrode may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0057] At block 404 a first doping material can be deposited on a first electrode. In an embodiment, the first doping material can include a metal, such as silver. In another embodiment, the first doping material can include a thin layer of material which can at least partially dope a subsequently formed layer, such as an insulator, to be discussed further. In an embodiment, the first doping material can be similar, but not necessarily identical to, to a second doping material (to be discussed further below), for example, in composition, thickness, and/or fabrication technique. In an embodiment, the metallic material can include gold, copper, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the first doping material can comprise a semi- metallic material. Non- limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the first doping material can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the first doping material can have a thickness of approximately 0.1 nm to approximately 100 nm, with an example thickness of approximately 1 nm to approximately 10 nm. In an embodiment, the first doping material may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0058] At block 406, an insulator can be deposited on a doped material. In another embodiment the insulator can include an oxide. In one embodiment the insulator can include a dielectric. In an embodiment, the insulator can include a silicon dioxide (S1O2), or a low-K material. In an embodiment, the insulator can include hafnium oxide. In one embodiment, the insulator can be deposited using PVD, CVD, MOCVD, and/or ALD, and the like. In an embodiment, the thickness of the insulator can be approximately x nm to approximately y nm, with an example thickness of approximately x nm to approximately y nm.

[0059] At block 408, a second doping material can be deposited on the insulator. In an embodiment, the second doping material can include a metal, such as silver. In another embodiment, the second doping material can include a thin layer of material which can at least partially dope a previously formed layer, such as an insulator, discussed above. In an embodiment, the second doping material can be similar, but not necessarily identical to, to a first doping material (discussed above), for example, in composition, thickness, and/or fabrication technique. In an embodiment, the metallic material can include gold, copper, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the second doping material can comprise a semi- metallic material. Non- limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. In various embodiments, the second doping material can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the second doping material can have a thickness of approximately 0.1 nm to approximately 100 nm, with an example thickness of approximately 1 nm to approximately 10 nm. In an embodiment, the second doping material may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0060] At block 410, a second electrode can be deposited on the second doped material. In an embodiment, the second electrode can be similar, but not necessarily identical to, to the first electrode (discussed above), for example, in composition, thickness, and/or fabrication technique. In an embodiment, the second electrode can include a metallic material. In an embodiment, the second electrode can include an inert metal. In an embodiment, the metallic material can include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials. In various embodiments, the second electrode can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi- metallic materials may also be any mixtures of such materials. In various embodiments, the second electrode can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. In an embodiment, the second electrode can have a thickness of approximately 1 nm to approximately 400 nm, with an example thickness of approximately 15 nm to approximately 100 nm. In an embodiment, the second electrode may be deposited by any suitable mechanism including, but not limited to, PVD, CVD, MOCVD, metal foil lamination, sputtering, metal paste deposition, combinations thereof, or the like.

[0061] At block 412, optionally a memory device can be formed on the second electrode. In various embodiments, the process flow as described above in connection with blocks 402, 404, 406, 408, and 410 can be used to fabricate a selector device, for example, a selector for use in connection with memory. In an embodiment, the selector can include a symmetric device that has current- voltage characteristics that are symmetric under opposing voltage biases. In an embodiment, the selector can be used in connection with a portion of a memory array, for example, in connection with wordlines and bitlines used in the memory device. In an embodiment, the selector can turn a memory device, for example, a resistive memory device such as an spin-transfer torque memory (STTM) device, on or off. In an embodiment, one or more selector and memory devices can be used in a first deck between a wordline and bitline in a portion of a memory array, and one or more second selector and memory devices can be used in a second deck between second wordline and bitline in the memory array.

[0062] In an embodiment, the selector fabricated by the process flow as described above can be used can enable multideck stacking in a memory array. In an embodiment, the selector can be fabricated using back-end-of-line (BEOL) processing and fabrication techniques.

[0063] In an embodiment, the selector can be used in connection with an interposer. In an embodiment, an interposer can refer to substrate used to bridge a first substrate to a second substrate. The first substrate may be, for instance, an integrated circuit die. The second substrate may be, for instance, a memory module that includes one or more embodiments described herein, a computer motherboard, or another integrated circuit die. In an embodiment, the interposer can be used to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer may couple an integrated circuit die to a ball grid array (BGA) that can subsequently be coupled to the second substrate. In some embodiments, the first and second substrates are attached to opposing sides of the interposer. In other embodiments, the first and second substrates are attached to the same side of the interposer. And in further embodiments, three or more substrates can be interconnected by way of the interposer. In an embodiment, the interposer may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. In an embodiment, the interposer may include metal interconnects and vias, including but not limited to through- silicon vias (TSVs). The interposer may further include embedded devices, including passive and active devices. Such devices include, but are not limited to, stackable thin film based memory devices as described herein, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and stackable thin film memory devices may also be formed on the interposer.

[0064] FIG. 5 depicts an example of a system 500 according to one or more embodiments of the disclosure. In an embodiment, the system 500 can include the selector devices described herein. In one embodiment, system 500 includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a tablet, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular telephone, a mobile computing device, a smart phone, an Internet appliance or any other type of computing device. In some embodiments, system 500 can include a system on a chip (SOC) system

[0065] In one embodiment, system 500 includes multiple processors including processor 510 and processor N 505, where processor N 505 has logic similar or identical to the logic of processor 510. In one embodiment, processor 510 has one or more processing cores (represented here by processing core 1 512 and processing core N 512N, where 512N represents the Nth processor core inside processor 510, where N is a positive integer). More processing cores can be present (but not depicted in the diagram of FIG. 5). In some embodiments, processing core 512 includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions, a combination thereof, or the like. In some embodiments, processor 510 has a cache memory

516 to cache instructions and/or data for system 500. Cache memory 516 may be organized into a hierarchical structure including one or more levels of cache memory

[0066] In some embodiments, processor 510 includes a memory controller (MC) 514, which is configured to perform functions that enable the processor 510 to access and communicate with memory 530 that includes a volatile memory 532 and/or a non-volatile memory 534. In some embodiments, processor 510 can be coupled with memory 530 and chipset 520. Processor 510 may also be coupled to a wireless antenna 578 to communicate with any device configured to transmit and/or receive wireless signals. In one embodiment, the wireless antenna antenna 578 operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

[0067] In some embodiments, volatile memory 532 includes, but is not limited to, Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM), and/or any other type of random access memory device. Non-volatile memory 534 includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.

[0068] Memory device 530 stores information and instructions to be executed by processor 510. In one embodiment, memory 530 may also store temporary variables or other intermediate information while processor 510 is executing instructions. In the illustrated embodiment, chipset 520 connects with processor 510 via Point-to-Point (PtP or P-P) interface

517 and P-P interface 522. Chipset 520 enables processor 510 to connect to other elements in system 500. In some embodiments of the disclosure, P-P interface 517 and P-P interface 522 can operate in accordance with a PtP communication protocol, such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.

[0069] In some embodiments, chipset 520 can be configured to communicate with processor 510, the processor N 505, display device 540, and other devices 572, 576, 574, 560, 562, 564, 566, 577, etc. Chipset 520 may also be coupled to the wireless antenna 578 to communicate with any device configured to transmit and/or receive wireless signals.

[0070] Chipset 520 connects to display device 540 via interface 526. Display 540 may be, for example, a liquid crystal display (LCD), a plasma display, cathode ray tube (CRT) display, or any other form of visual display device. In some embodiments of the disclosure, processor 510 and chipset 520 are integrated into a single SOC. In addition, chipset 520 connects to bus 550 and/or bus 555 that interconnect various elements 574, 560, 562, 564, and 566. Bus 550 and bus 555 may be interconnected via a bus bridge 572. In one embodiment, chipset 520 couples with a non-volatile memory 560, a mass storage device(s) 562, a keyboard/mouse 564, and a network interface 566 via interface 524 and/or 504, smart TV 576, consumer electronics 577, etc.

[0071] In one embodiment, mass storage device(s) 552 can include, but not be limited to, a solid state drive, a hard disk drive, a universal serial bus flash memory drive, or any other form of computer data storage medium. In one embodiment, network interface 566 is implemented by any type of well-known network interface standard including, but not limited to, an Ethernet interface, a universal serial bus (USB) interface, a Peripheral Component Interconnect (PCI) Express interface, a wireless interface and/or any other suitable type of interface. In one embodiment, the wireless interface operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

[0072] While the modules shown in FIG. 5 are depicted as separate blocks within the system 500, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although cache memory 516 is depicted as a separate block within processor 510, cache memory 516 or selected elements thereof can be incorporated into processor core 512.

[0073] It is noted that the system 500 described herein may include any suitable type of microelectronics packaging and configurations thereof, including, for example, system in a package (SiP), system on a package (SOP), package on package (PoP), interposer package, 3D stacked package, etc. Further, any suitable type of microelectronic components may be provided in the semiconductor packages, as described herein. For example, microcontrollers, microprocessors, baseband processors, digital signal processors, memory dies, field gate arrays, logic gate dies, passive component dies, MEMSs, surface mount devices, application specific integrated circuits, baseband processors, amplifiers, filters, combinations thereof, or the like may be packaged in the semiconductor packages, as disclosed herein. The semiconductor devices (for example, the semiconductor devices described in connection with any of FIGS. 1-4), as disclosed herein, may be provided in any variety of electronic device including consumer, industrial, military, communications, infrastructural, and/or other electronic devices.

[0074] In various embodiments, the devices, as described herein, may be used in connection with one or more processors. The one or more processors may include, without limitation, a central processing unit (CPU), a digital signal processor(s) (DSP), a reduced instruction set computer (RISC), a complex instruction set computer (CISC), a microprocessor, a microcontroller, a field programmable gate array (FPGA), or any combination thereof. The processors may also include one or more application specific integrated circuits (ASICs) or application specific standard products (ASSPs) for handling specific data processing functions or tasks. In certain embodiments, the processors may be based on an Intel® Architecture system and the one or more processors and any chipset included in an electronic device may be from a family of Intel® processors and chipsets, such as the Intel® Atom® processor(s) family or Intel-64 processors (for example, Sandy Bridge®, Ivy Bridge®, Haswell®, Broadwell®, Skylake®, etc.).

[0075] Additionally or alternatively, the devices, as described herein, may be used in connection with one or more additional memory chips. The memory may include one or more volatile and/or non-volatile memory devices including, but not limited to, magnetic storage devices, read-only memory (ROM), random access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), double data rate (DDR) SDRAM (DDR-SDRAM), RAM-BUS DRAM (RDRAM), flash memory devices, electrically erasable programmable read-only memory (EEPROM), non-volatile RAM (NVRAM), universal serial bus (USB) removable memory, or combinations thereof.

[0076] In example embodiments, the electronic device in which the disclosed devices are used and/or provided may be a computing device. Such a computing device may house one or more boards on which the devices may be disposed. The board may include a number of components including, but not limited to, a processor and/or at least one communication chip. The processor may be physically and electrically connected to the board through, for example, electrical connections of the devices. The computing device may further include a plurality of communication chips. For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, and others. In various example embodiments, the computing device may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, combinations thereof, or the like. In further example embodiments, the computing device may be any other electronic device that processes data.

[0077] Example 1 may include a selector, comprising: a first electrode on a substrate; a first doped material on the first electrode; an insulator on the first doped material; a second doped material on the insulator; and a second electrode on the second doped material.

[0078] Example 2 may include the selector of example 1 and/or some other example herein, wherein first current- voltage characteristics associated with the selector biased under positive voltage is substantially similar to second current-voltage characteristics associated with the selector biased under negative voltage.

[0079] Example 3 may include the selector of example 1 and/or some other example herein, wherein the first doped material includes one or more of silver, copper, or titanium.

[0080] Example 4 may include the selector of example 1 and/or some other example herein, wherein the second doped material includes one or more of silver, copper, or titanium.

[0081] Example 5 may include the selector of example 1 and/or some other example herein, wherein the insulator comprises hafnium and oxygen.

[0082] Example 6 may include the selector of example 1 and/or some other example herein, wherein the first electrode comprises an inert metal.

[0083] Example 7 may include the selector of example 6 and/or some other example herein, wherein the inert metal comprises one of gold or platinum.

[0084] Example 8 may include the selector of example 1 and/or some other example herein, wherein the second electrode comprises an inert metal.

[0085] Example 9 may include the selector of example 8 and/or some other example herein, wherein the inert metal comprises one of gold or platinum.

[0086] Example 10 may include a memory array, comprising: a first interconnect; a first selector on the first interconnect; a first memory device on the first selector; a second interconnect on the first memory device; a second selector on the second interconnect; a second memory device on the second selector; and a third interconnect on the second memory device; wherein the first selector comprises: a first electrode; a first doped material on the first electrode; an insulator on the first doped material; a second doped material on the insulator; and a second electrode on the second doped material.

[0087] Example 11 may include the memory array of example 10 and/or some other example herein, wherein first current-voltage characteristics associated with the first selector biased under positive voltage is substantially similar to second current-voltage characteristics associated with the first selector biased under negative voltage.

[0088] Example 12 may include the memory array of example 10 and/or some other example herein, wherein the first doped material includes one or more of silver, copper, or titanium.

[0089] Example 13 may include the memory array of example 10 and/or some other example herein, wherein the second doped material includes one or more of silver, copper, or titanium.

[0090] Example 14 may include the memory array of example 10 and/or some other example herein, wherein the insulator comprises hafnium and oxygen.

[0091] Example 15 may include the memory array of example 10 and/or some other example herein, wherein the first electrode comprises an inert metal.

[0092] Example 16 may include the memory array of example 15 and/or some other example herein, wherein the inert metal comprises one of gold or platinum.

[0093] Example 17 may include the memory array of example 10 and/or some other example herein, wherein the first electrode comprises an inert metal.

[0094] Example 18 may include the memory array of example 17 and/or some other example herein, wherein the inert metal comprises one of gold or platinum.

[0095] Example 19 may include the memory array of example 10 and/or some other example herein, wherein the first interconnect and the second interconnect are substantially perpendicular to one another.

[0096] Example 20 may include a chip comprising a memory array, the memory array including a selector, the selector comprising: a first electrode; a first doped material on the first electrode; an insulator on the first doped material; a second doped material on the insulator; and a second electrode on the second doped material.

[0097] Example 21 may include the chip of example 20 and/or some other example herein, wherein the selector is a first selector, the chip further comprising: a first interconnect; the first selector on the first interconnect; a first memory device on the first selector; a second interconnect on the first memory device; a second selector on the second interconnect; a second memory device on the second selector; and a third interconnect on the second memory device. [0098] Example 22 may include the chip of example 20 and/or some other example herein, wherein first current- voltage characteristics associated with the selector biased under positive voltage is substantially similar to second current-voltage characteristics associated with the selector biased under negative voltage.

[0099] Example 23 may include an electronic device comprising: a selector, comprising: a first electrode on a substrate; a first doped material on the first electrode; an insulator on the first doped material; a second doped material on the insulator; and a second electrode on the second doped material.

[0100] Example 24 may include the electronic device of example 23 and/or some other example herein, wherein first current-voltage characteristics associated with the selector biased under positive voltage is substantially similar to second current-voltage characteristics associated with the selector biased under negative voltage.

[0101] Example 25 may include the electronic device of example 23 and/or some other example herein, wherein the first doped material includes one or more of silver, copper, or titanium.

[0102] Example 26 may include the electronic device of example 23 and/or some other example herein, wherein the second doped material includes one or more of silver, copper, or titanium.

[0103] Example 27 may include the electronic device of example 23 and/or some other example herein, wherein the insulator comprises hafnium and oxygen.

[0104] Example 28 may include the electronic device of example 23 and/or some other example herein, wherein the first electrode comprises an inert metal.

[0105] Example 29 may include the electronic device of example 28 and/or some other example herein, wherein the inert metal comprises one of gold or platinum.

[0106] Example 30 may include the electronic device of example 23 and/or some other example herein, wherein the second electrode comprises an inert metal.

[0107] Example 31 may include the electronic device of example 30 and/or some other example herein, wherein the inert metal comprises one of gold or platinum.

[0108] Various features, aspects, and embodiments have been described herein. The features, aspects, and embodiments are susceptible to combination with one another as well as to variation and modification, as will be understood by those having skill in the art. The present disclosure should, therefore, be considered to encompass such combinations, variations, and modifications. [0109] The terms and expressions which have been employed herein are used as terms of description and not of limitation, and there is no intention, in the use of such terms and expressions, of excluding any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible within the scope of the claims. Other modifications, variations, and alternatives are also possible. Accordingly, the claims are intended to cover all such equivalents.

[0110] While the disclosure includes various embodiments, including at least a best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the foregoing description. Accordingly, the disclosure is intended to embrace all such alternatives, modifications, and variations, which fall within the scope of the included claims. All matters disclosed herein or shown in the accompanying drawings are to be interpreted in an illustrative and non-limiting sense.

[0111] This written description uses examples to disclose certain embodiments of the disclosure, including the best mode, and also to enable any person skilled in the art to practice certain embodiments of the disclosure, including making and using any apparatus, devices or systems and the performance of any incorporated methods and processes. The patentable scope of certain embodiments of the invention is defined in the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal language of the claims.