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Title:
SELF-ADAPTIVE SELECTION AND DESIGN METHOD FOR CONVOLUTIONAL-LAYER HARDWARE ACCELERATOR
Document Type and Number:
WIPO Patent Application WO/2020/119318
Kind Code:
A1
Abstract:
Disclosed is a self-adaptive selection and design method for a convolutional-layer hardware accelerator, comprising the following steps: (1) analyzing convolutional layer structures, designing four different hardware accelerator solutions for different kinds of convolutional layer structures, and storing the four different hardware accelerator solutions in an accelerator solution pool; and (2) obtaining a convolutional layer structure and a convolutional layer parameter from an input source, selecting, according to the convolutional layer structure, an optimal accelerator solution from the accelerator solution pool, and constructing a corresponding convolutional-layer accelerator on the basis of the optimal accelerator solution. The invention is employed to design a solution pool of convolution-layer accelerators, self-adaptively select an optimal solution, and generate a hardware accelerator, thereby enabling more flexible hardware design, while also reducing resource consumption and increasing parallel operation speeds of convolution layers.

Inventors:
QIN HUABIAO (CN)
CAO QINPING (CN)
Application Number:
PCT/CN2019/114910
Publication Date:
June 18, 2020
Filing Date:
October 31, 2019
Export Citation:
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Assignee:
UNIV SOUTH CHINA TECH (CN)
International Classes:
G06N3/04
Foreign References:
CN109740731A2019-05-10
CN108805267A2018-11-13
CN105869117A2016-08-17
CN207993065U2018-10-19
CN108875915A2018-11-23
US20180157969A12018-06-07
Other References:
XIAO, HAO ET AL.: "Design of FPGA Hardware Accelerator for Convolutional Neural Network", INDUSTRIAL CONTROL COMPUTER, vol. 31, no. 6, 30 June 2018 (2018-06-30)
Attorney, Agent or Firm:
YOGO PATENT & TRADEMARK AGENCY LIMITED COMPANY (CN)
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