BACKGROUND

[0001] The present invention relates to semiconductors, and more specifically, to techniques for forming semiconductor structures. Semiconductors and integrated circuit chips have become ubiquitous within many products, particularly as they continue to decrease in cost and size. There is a continued desire to reduce the size of structural features and/or to provide a greater amount of structural features for a given chip size. Miniaturization, in general, allows for increased performance at lower power levels and lower cost. Present technology is at or approaching atomic level scaling of certain micro-devices such as logic gates, field effect transistors (FETs), and capacitors.

SUMMARY

[0002] Embodiments of the invention provide techniques for forming self-aligned gate isolation structures with both symmetric and asymmetric cut placements.

[0003] In one embodiment, a method of forming a semiconductor structure comprises forming a plurality of fins over a top surface of a substrate, forming a shallow trench isolation region over the top surface of the substrate surrounding the plurality of fins, and forming a plurality of nanosheet stacks of channel material over the plurality of fins, the plurality of nanosheet stacks providing channels for one or more nanosheet field-effect transistors. The method also comprises forming a channel protecting liner over at least a portion of sidewalls and a top surface of a first one of the plurality of nanosheet stacks formed over a first one of the plurality of fins, the channel protecting liner being further formed over a portion of the shallow trench isolation region extending from the portion of the sidewalls of the first nanosheet stack toward a second one of the plurality of nanosheet stacks formed over a second one of the plurality of fins. The method further comprises forming a plurality of gate stacks surrounding portions of the plurality of nanosheet stacks exposed by the channel protecting liner, forming at least one asymmetric self-aligned gate isolation structure over the channel protecting liner, and forming at least one symmetric self-aligned gate isolation structure over a portion of the shallow trench isolation region between a third one of the plurality of fins and a fourth one of the plurality of fins.

[0004] In another embodiment, a semiconductor structure comprises a substrate, a plurality of fins disposed over a top surface of the substrate, a shallow trench isolation region disposed over the top surface of the substrate surrounding the plurality of fins, and a plurality of nanosheet stacks of channel material disposed over the plurality of fins, the plurality of nanosheet stacks providing channels for one or more nanosheet field-effect transistors. The semiconductor structure also comprises a channel protecting liner disposed over at least a portion of sidewalls and a top surface of a first one of the plurality of nanosheet stacks disposed over a first one of the plurality of fins, the channel protecting liner being further disposed over a portion of the shallow trench isolation region extending from the portion of the sidewalls of the first nanosheet stack toward a second one of the plurality of nanosheet stacks disposed over a second one of the plurality of fins. The semiconductor structure further comprises a plurality of gate stacks surrounding portions of the plurality of nanosheet stacks exposed by the channel protecting liner, at least one asymmetric self-aligned gate isolation structure disposed over the channel protecting liner, and at least one symmetric self-aligned gate isolation structure disposed over a portion of the shallow trench isolation region between a third one of the plurality of fins and a fourth one of the plurality of fins.

[0005] In another embodiment, an integrated circuit comprises a nanosheet field-effect transistor structure comprising a substrate, a plurality of fins disposed over a top surface of the substrate, a shallow trench isolation region disposed over the top surface of the substrate surrounding the plurality of fins, and a plurality of nanosheet stacks of channel material disposed over the plurality of fins, the plurality of nanosheet stacks providing channels for one or more nanosheet field-effect transistors. The nanosheet field-effect transistor structure also comprises a channel protecting liner disposed over at least a portion of sidewalls and a top surface of a first one of the plurality of nanosheet stacks disposed over a first one of the plurality of fins, the channel protecting liner being further disposed over a portion of the shallow trench isolation region extending from the portion of the sidewalls of the first nanosheet stack toward a second one of the plurality of nanosheet stacks disposed over a second one of the plurality of fins. The nanosheet field-effect transistor structure further comprises a plurality of gate stacks surrounding portions of the plurality of nanosheet stacks exposed by the channel protecting liner, at least one asymmetric self-aligned gate isolation structure disposed over the channel protecting liner, and at least one symmetric self-aligned gate isolation structure disposed over a portion of the shallow trench isolation region between a third one of the plurality of fins and a fourth one of the plurality of fins.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] FIG. 1 A depicts a top-down view of an aligned gate cut between two fins, according to an embodiment of the invention.

[0007] FIG. 1 B depicts a top-down view of a mis-aligned and enlarged gate cut between two fins, according to an embodiment of the invention.

[0008] FIG. 2 depicts a top-down view of asymmetric gate cuts in a topology of a static random-access memory structure, according to an embodiment of the invention.

[0009] FIG. 3A depicts a side cross-sectional view of a semiconductor structure after patterning of nanosheet stacks, according to an embodiment of the invention. [0010] FIG. 3B depicts a top-down view of a portion of the FIG. 3A structure, according to an embodiment of the invention.

[0011] FIG. 4 depicts a side cross-sectional view of the FIG. 3A structure following formation of a channel protecting liner, a dummy gate and a gate hard mask, according to an embodiment of the invention.

[0012] FIG. 5A depicts a first side cross-sectional view of the FIG. 4 structure following formation of source/drain regions and planarization, according to an embodiment of the invention.

[0013] FIG. 5B depicts a second side cross-sectional view of the FIG. 4 structure following the formation of source/drain regions and planarization, according to an embodiment of the invention.

[0014] FIG. 6 depicts a side cross-sectional view of the FIG. 5A structure following removal of the dummy gate, according to an embodiment of the invention.

[0015] FIG. 7 depicts a side cross-sectional view of the FIG. 6 structure following patterning of the channel protecting liner, according to an embodiment of the invention.

[0016] FIG. 8 depicts a side cross-sectional view of the FIG. 7 structure following selective growth of the sacrificial nanosheet material, according to an embodiment of the invention.

[0017] FIG. 9 depicts a side cross-sectional view of the FIG. 8 structure following formation of a self-aligned isolation layer, according to an embodiment of the invention.

[0018] FIG. 10 depicts a side cross-sectional view of the FIG. 9 structure following formation of an organic planarization layer, according to an embodiment of the invention.

[0019] FIG. 11 depicts a side cross-sectional view of the FIG. 10 structure following patterning of symmetric and asymmetric gate cuts, according to an embodiment of the invention.

[0020] FIG. 12 depicts a side cross-sectional view of the FIG. 11 structure following fill of the symmetric and asymmetric gate cuts with a dielectric material, according to an embodiment of the invention.

[0021] FIG. 13 depicts a side cross-sectional view of the FIG. 12 structure following removal of the organic planarization layer and the sacrificial nanosheet material, according to an embodiment of the invention.

[0022] FIG. 14 depicts a side cross-sectional view of the FIG. 13 structure following formation of gate structures, according to an embodiment of the invention.

DETAILED DESCRIPTION

[0023] Illustrative embodiments of the invention may be described herein in the context of illustrative methods for performing self-aligned gate isolation with both symmetric and asymmetric cut placements. However, it is to be understood that embodiments of the invention are not limited to the illustrative methods, apparatus, systems and devices but instead are more broadly applicable to other suitable methods, apparatus, systems and devices.

[0024] A FET is a transistor having a source, a gate, and a drain, and having action that depends on the flow of majority carriers along a channel that runs past the gate between the source and drain. Current through the channel between the source and drain may be controlled by a transverse electric field under the gate. The length of the gate determines how fast the FET switches, and can be about the same as the length of the channel (such as the distance between the source and drain).

[0025] In some FETs, more than one gate or multi-gate arrangements may be used for controlling the channel. Multi-gate FETs are promising candidates to scale down complementary metal-oxide-semiconductor (CMOS) FET technology. However, the smaller dimensions associated with multi-gate FETs (as compared to single-gate FETs) necessitate greater control over performance issues such as short channel effects, punch-through, metal-oxide semiconductor (MOS) leakage current, and the parasitic resistance that is present in a multi-gate FET.

[0026] Various techniques may be used to reduce the size of FETs. One technique is through the use of fin- shaped channels in FinFET devices. Before the advent of FinFET arrangements, CMOS devices were typically substantially planar along the surface of the semiconductor substrate, with the exception of the FET gate disposed over the top of the channel. FinFETs utilize a vertical channel structure, increasing the surface area of the channel exposed to the gate. Thus, in FinFET structures the gate can more effectively control the channel, as the gate extends over more than one side or surface of the channel. In some FinFET arrangements, the gate encloses three surfaces of the three-dimensional channel, rather than being disposed over just the top surface of a traditional planar channel.

[0027] Another technique useful for reducing the size of FETs is through the use of stacked nanosheet channels formed over a semiconductor substrate. Stacked nanosheets may be two-dimensional nanostructures, such as sheets having a thickness range on the order of 1 to 100 nanometers (nm). Nanosheets and nanowires are viable options for scaling to 7nm and beyond. A general process flow for formation of a nanosheet stack involves removing sacrificial layers, which may be formed of silicon germanium (SiGe), between sheets of channel material, which may be formed of silicon (Si). [0028] As cell height scales, techniques for performing gate cuts do not meet the requirements, as the spacing between active regions is too small. A process referred to as self-aligned gate cut or self-aligned gate isolation may be used to scale active-to-active spacing to 5nm and beyond. SAGE-induced gate cuts, however, are not ideal in certain situations that require the use of asymmetric gate cuts. Static random-access memory (SRAM) devices, for example, may utilize asymmetric gate cuts.

[0029] FIG. 1A depicts a top-down view 100 of an aligned gate cut 101 that is performed between two of a set of fins 102 on one of two gate structures 104. The aligned gate cut 101 represents an ideal case, where the gate cut 101 is perfectly aligned between the adjacent fins 104 and has a small critical dimension 103 (e.g., in the range of 6 to 15nm). FIG. 1 B depicts a top-down view 150 of a mis-aligned gate cut 110 that is performed between two of a set of fins 102 on one of two gate structures 104. As depicted, the gate cut 110 is not perfectly aligned, in that it is closer to one of the two adjacent fins 102 than the other. The mis-aligned gate cut 110 also has a larger critical dimension 130 (e.g., in the range of 15 to 40nm).

[0030] For scaling to 5nm and beyond, the cell height 105 of twice the gate cut 101 to fin 104 spacing plus the critical dimension 103 of the gate cut 101 , with allowances for variations, is approximately 40nm. The gate cut 101- to-fin 104 spacing should not pinch-off, with the required spacing being twice the thickness of the gate stack including a high-k gate dielectric and work function metal (WFM) gate conductor (e.g., 2 x (2 +5) = 14nm). Further, fin critical dimension uniformity (CDU), fin pitch walking (PW), gate cut CDU, and gate cut overlay parameters, which are assumed to be controlled tightly, have a total variation of only 5nm. The CD of the gate cut 101 should therefore be approximately 40nm - (2x14nm) - 5nm = 7nm, which is not achievable using conventional lithography processing.

[0031] As noted above, self-aligned gate cut or self-aligned gate isolation techniques may be used for future cell height scaling. A self-aligned gate cut processing flow may include fin patterning (e.g., of fins and other layers including a passivation layer, a poly-silicon layer and a hard mask layer). Next, a liner dielectric may be formed, followed by a shallow trench isolation (STI) region. The STI region may then be recessed (e.g., a fin reveal is performed), followed by formation of a dummy gate dielectric. A spacer (e.g., of poly-silicon) is then formed, which is either merged or discrete depending on fin spacing. An isolation plug is then formed. The dummy gate is then patterned using a gate hard mask and techniques such as self-aligned double patterning (SADP). An anisotropic etch is then performed, where the anisotropic etch is selective to the isolation plug, the dummy gate dielectric and the gate hard mask. In this way, symmetric gate cuts may be performed.

[0032] Self-aligned gate cut processing, however, is not suitable for forming asymmetric gate cuts needed in some application scenarios. For example, as noted above, SRAM structures may utilize asymmetric gate cuts. SRAM is a type of memory device that offers high speed, low power consumption and simple operation. Unlike dynamic random-access memory (DRAM), SRAM does not need to regularly refresh stored data and has a straightforward design. SRAM cells may be formed using varying numbers of transistors.

[0033] The six transistor (6T) SRAM cell is widely used as a primary memory in microprocessor circuits. A 6T SRAM cell may include a first n-type FET device (nFET) connected to a first bit line node (BL), a first output node (Q), and a word line node (WL). A second nFET device of the 6T SRAM cell is connected to the Q node, a ground node (e.g., VSS), and a second output node (Q ¹ ). A first p-type FET device (pFET) is connected to the Q node, the Q' node, and a voltage source or supply node (e.g., VDD). A second pFET device is connected to the VDD node, the Q node and the Q' node. A third nFET device is connected to the VSS node, the Q node, and the Q' node. A fourth nFET device is connected to a second bit line node (BLB), the WL node and the Q' node. The first and fourth nFET devices are pass-gate (PG) transistors of the 6T SRAM cell, the second and third nFET devices are the pull down (PD) transistors of the 6T SRAM cell, and the first and second pFET devices are the pull-up (PU) transistors of the 6T SRAM cell.

[0034] FIG. 2 depicts a top-down view 200 of asymmetric gate cuts 209-1 and 209-2 for an SRAM cell. In the top- down view 200, element 201 shows VSS (e.g., a 0 volt (V) or "ground” voltage) connections while element 203 shows VDD (e.g., a positive supply voltage) connections. Elements 205-1 and 205-2 show WL connections of the SRAM cell, and elements 207-1 and 207-2 show bitline connections (e.g., BL and BLB, respectively) of the SRAM cell. Elements 209-1 and 209-2 illustrate the asymmetric gate cuts, which are disposed closer to one of two adjacent fins, rather than being formed symmetrically between two adjacent fins.

[0035] An illustrative process for performing self-aligned gate isolation with both symmetric and asymmetric cut placements will now be described in further detail with respect to FIGS. 3-14.

[0036] FIG. 3A shows a side cross-sectional view 300 of a semiconductor structure after patterning of nanosheet stacks over a substrate 302. A set of fins 304-1 through 304-5 (collectively, fins 304) are formed over the substrate 302. The set of fins 304 are surrounded by STI region 306. Nanosheet stacks including alternating layers 308 and 310 of a sacrificial material and a channel material are formed over each of the fins 304. While FIG. 3A shows an example where there are three sacrificial layers 308 and three channel layers 310 in each nanosheet stack, it should be appreciated that this is merely an example, and that nanosheet stacks may include more or fewer than three sets of alternating layers of the sacrificial material and the channel material.

[0037] The substrate 302 may be a semiconductor structure formed of bulk silicon (Si), although other suitable materials may be used, such as various silicon-containing materials. Illustrative examples of silicon-containing materials suitable for the substrate 302 include, but are not limited to, Si, silicon germanium (SiGe), silicon germanium carbide (SiGeC), silicon carbide (SiC), polysilicon, epitaxial silicon, amorphous silicon, and multi-layers thereof. Although silicon is the predominantly used semiconductor material in wafer fabrication, alternative semiconductor materials can be employed, such as, but not limited to, germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), cadmium telluride (CdTe) and zinc selenide (ZnSe). In an alternate embodiment, the substrate 302 may be silicon-on-insulator (SOI) wafer. As is known in the art, a SOI wafer includes a SOI layer separated from a substrate by a buried insulator. Suitable substrate materials include, but are not limited to, Si, strained Si, silicon carbide (SiC), Ge, SiGe, SiGeC, Si alloys, Ge alloys, GaAs, indium arsenide (InAs), indium phosphide (InP), or any combination thereof. Suitable dielectric materials for the buried insulator include, but are not limited to, an oxide material such as silicon dioxide (S1O2). When the buried insulator is an oxide, the buried insulator may also be referred to as a buried oxide or BOX.

[0038] The substrate 302 may have a width or horizontal thickness (in direction X-X') that varies as desired (e.g., based on the number of fins 304 or other device structures to be formed). The substrate 302 may have a height or vertical thickness (in direction Y-Y') ranging from 300 micrometers (pm) to 1000pm.

[0039] The fins 304 may be formed of the same material as the underlying substrate 302. For example, in some embodiments the fins 304 are formed from a bulk substrate using lithography and etching (e.g., reactive-ion etching (RIE)). Other suitable techniques, such as sidewall image transfer (SIT), self-aligned double patterning (SADP), self-aligned multiple patterning (SAMP), self-aligned quadruple patterning (SAQP), etc. can be used to form the fins 304. In such cases, the fins 304 may be formed of the same material as the substrate 302 (e.g., Si). Alternatively, the fins 304 may be formed of a different material than the substrate 302 by first epitaxially growing a different material on the substrate 302, and then patterning to form the fins 304. For example, the fins 304 can be silicon germanium (SiGe) while the substrate 302 can be Si.

[0040] Each of the fins 304 may have a vertical thickness or height (in direction Y-Y') in the range of 20 to 35nm and a horizontal thickness or width (in direction X-X') that varies in the range of 6 to 100nm. As shown in FIG. 3A, different ones of the fins 304 have different widths (e.g., fins 304-1, 304-2 and 304-3 are larger in direction X-X than fins 304-4 and 304-5). The spacing between the fins 304 may also vary as will be described in further detail below.

[0041] The STI layer 306 may be formed of a dielectric material such as silicon oxide (SiO _x ), silicon nitride (SiN), silicon oxycarbide (SiOC), silicon oxynitride (SiON), or any other suitable dielectric material. The vertical thickness or height (in direction Y-Y') of the STI layer 306 is defined by fin reveal processing, and will approximately match the level of the bottom surface of the nanosheet stack. The horizontal thickness or width (in direction X-X) of the STI layer 306 is defined by the spacing between the fins 304 as shown.

[0042] The nanosheet stack, as noted above, includes alternating layers of a sacrificial material 308 and a channel material 310. The sacrificial layers 308 may be formed of any suitable material that may be etched selective to the channel material 310. If the channel material 310 is Si, the sacrificial layers 308 may be SiGe. If the channel material 310 is indium gallium arsenide (InGaAs), the sacrificial layers 308 may be indium aluminum arsenide (InAIAs). Various other combinations of lll-V materials may be used. The material of the sacrificial layers 308 is one that can be removed selective to the material of the channel layers 310. The sacrificial layers 308 and channel layers 310 may each have a thickness in the range of 4nm to 15nm. The nanosheet stack of sacrificial layers 308 and channel layers 310 may be epitaxially grown over the fins 304.

[0043] FIG. 3A shows two regions, denoted 301 and 303, of nanosheet stacks formed over a common substrate 302. The region 301 is referred to herein as a "logic” region, and the fins 304-1 and 304-2 may provide for nFET or pFET devices as desired for logic devices of a resulting structure. The region 303 is referred to herein as an "SRAM” region, where the fins 304-3, 304-4 and 304-5 provide nFET and pFET devices for forming SRAM cells (e.g., such as that shown in the top-down view 200 of FIG. 2). In some embodiments, the fin 304-3 provides for nFET devices while the fins 304-4 and 304-5 provide for pFET devices. The spacing between the fin 304-3 providing the nFET device and the fin 304-4 providing the pFET device, denoted in FIG. 3A as element 305, may be approximately 40nm. The width of the fin 304-4, denoted in FIG. 3A as element 307, may be approximately 15nm. The spacing between the fins 304-4 and 304-5 providing pFET devices, denoted in FIG. 3A as element 309, may be approximately 30nm.

[0044] FIG. 3B shows a top-down view 350 of the region 303 of a resulting SRAM cell formed from the structure shown in the side cross-sectional view 300 of FIG. 3A. The side cross-sectional view 300 of FIG. 3A (as well as the side cross-sectional views of FIGS. 4, 5A and 6-14) is taken across or perpendicular to the fins 304.

[0045] FIG. 4 shows a side cross-sectional view 400 of the FIG. 3A structure following formation of a channel protecting liner 312, a dummy gate 314, and a gate hard mask 316. The channel protecting liner 312, as shown, is formed over the STI region 306 and surrounding the nanosheet stacks. The channel protecting liner 312, which may also be referred to as a dummy gate oxide layer 312, may have a uniform thickness in the range of 2 to 5nm. The channel protecting liner 312 may be formed using atomic layer deposition (ALD) or other suitable techniques. The channel protecting liner 312 may be formed of an oxide such as silicon dioxide (S1O2).

[0046] The dummy gate 314 is formed over the channel protecting liner 312, filling the spaces between the nanosheets stacks and overfilling the structure. The dummy gate 314 may have a height or vertical thickness (in direction Y-Y'), as measured from the channel protecting liner 312 formed over the STI region 306, in the range of 60 to 200nm. The dummy gate 314 may be formed of amorphous silicon (a-Si) or another suitable material such as amorphous silicon germanium (a-SiGe), poly-silicon (poly-Si) poly-silicon germanium (poly-SiGe), etc. The dummy gate 314 may be formed using ALD, chemical vapor deposition (CVD), physical vapor deposition (PVD) or other suitable processing.

[0047] The gate hard mask 316 is patterned over the top of the dummy gate 314 (e.g., in regions where gates for the resulting structures will be formed). The gate hard mask 316 may be formed using CVD, PVD or other suitable processing. The gate hard mask 316 may be formed of S1O2, SiN, combinations thereof, etc. The gate hard mask 316 may have a height or vertical thickness (in direction Y-Y') in the range of 20 to 120nm.

[0048] FIG. 5A shows a first side cross-sectional view 500 of the FIG. 4 structure, following formation of source/drain regions 318 and planarization. FIG. 5B shows a second side cross-sectional view 550 of the FIG. 4 structure following formation of the source/drain regions 318. FIG. 5B also shows a first spacer 320 formed between the sacrificial layers 308 and the source/drain regions 318 and a second spacer 322 formed between the dummy gate 314 and an interlayer dielectric (ILD) 316. As noted above, the side cross-sectional view 500 of FIG. 5A is taken across or perpendicular to the fins 304. The side cross-sectional view 550 of FIG. 5B is taken along or parallel to one of the fins 304.

[0049] The source/drain regions 318 may be formed using an epitaxial growth process. In some embodiments, the epitaxial growth process comprises in-situ doping (dopants are incorporated in epitaxy material during epitaxy). Epitaxial materials may be grown from gaseous or liquid precursors. Epitaxial materials may be grown using vapor- phase epitaxy (VPE), molecular-beam epitaxy (MBE), liquid-phase epitaxy (LPE), rapid thermal chemical vapor deposition (RTCVD), metal organic chemical vapor deposition (MOCVD), ultra-high vacuum chemical vapor deposition (UFIVCVD), low-pressure chemical vapor deposition (LPCVD), limited reaction processing CVD (LRPCVD), or other suitable processes. Epitaxial silicon, silicon germanium (SiGe), germanium (Ge), and/or carbon doped silicon (Si:C) silicon can be doped during deposition (in-situ doped) by adding dopants, such as n-type dopants (e.g., phosphorus (P), arsenic (As), antimony (Sb), etc.) or p-type dopants (e.g., boron (B), boron fluoride (BF2), gallium (Ga), indium (In), thallium (Tl), etc.), depending on the type of transistor. The dopant concentration in the source/drain can range from 1x10 ¹⁹ cm ^·3 to 3x10 ²¹ cm ^·3 , or preferably between 2x10 ²⁰ cm ^·3 to 3x10 ²¹ cm ^·3 .

[0050] The spacer 322 may be formed by depositing a conformal spacer liner, followed by anisotropic spacer RIE. The spacer 320 may be formed by recessing the nanosheet stack, followed by forming selective indentation of the sacrificial layers 308 of the nanosheet stack (e.g., where the sacrificial layers 308 may be formed of SiGe and the channel layers 310 may be formed of Si as noted above). The spacer material for spacer 320 may then be filled in the indents with a conformal spacer liner, with the spacer liner being removed elsewhere using an isotropic etching process. The spacer 320 and spacer 322 may each be formed of SiN, silicon oxycarbonitride (SiOCN), silicon oxycarbide (SiOC), SiC, silicon boron carbide nitride (SiBCN), etc.

[0051] FIG. 6 shows a side cross-sectional view 600 of the FIG. 5A structure following removal of the dummy gate 314. The dummy gate 314 may be removed using a selective wet or dry etch process, such as a hot ammonia clean. Removal of the dummy gate 314 exposes the channel protecting liner 312.

[0052] FIG. 7 shows a side cross-sectional view 700 of the FIG. 6 structure following patterning of the channel protecting liner 312 using a dummy oxide mask layer 324. The dummy oxide mask layer 324 is patterned over a portion of the fin 304-4 that faces fin 304-3 (e.g., for an SRAM device, the dummy oxide mask layer 324 protects the SRAM pFET side that faces the nFET provided using fin 304-3). The dummy oxide mask layer 324 may be formed and patterned using lithography and etching or other suitable techniques.

[0053] The dummy oxide mask layer 324 may be formed of an organic planarization layer (OPL) material such as polyacrylate resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylenether resin, polyphenylenesulfide resin, benzocyclobutene (BCB), etc. The dummy oxide mask layer 324 may be formed using spin-on coating or other suitable processing. The dummy oxide mask layer 324 may have a height or vertical thickness (in direction Y-Y'), as measured from a top of the channel protecting liner 312 formed over the STI region 306, in the range of 60 to 200nm. The width or horizontal thickness (in direction X-X') of the EG mask layer 324 may vary, such as based on the width of the fin 304-4 and the spacing between the fins 304-3 and 304-4. As shown in FIG. 7, the dummy oxide mask layer 324 extends from a middle of a top of the nanosheet stack over fin 304-4 to a middle of the STI region 306 between the fins 304-3 and 304-4.

[0054] After the dummy oxide mask layer 324 is patterned, the channel protecting liner 312 exposed by the patterned dummy oxide mask layer 324 is removed, such as using an isotropic oxide dry etch process.

[0055] FIG. 8 shows a side cross-sectional view 800 of the FIG. 7 structure, following removal of the patterned dummy oxide mask layer 324 (e.g., using ashing) and following selective epitaxial growth 326 of the material (e.g., SiGe) of the sacrificial layers 308 of the nanosheet stacks. As shown, the material 326 is grown over exposed surfaces of the nanosheet stacks not covered by the remaining channel protecting liner 312. The epitaxial growth of material 326 may have a uniform thickness in the range of 5 to 30nm.

[0056] FIG. 9 shows a side cross-sectional view 900 of the FIG. 8 structure following formation of a self-aligned isolation layer 328. The self-aligned isolation layer 328 may be formed of a dielectric material such as S1O2, SiN, SiOCN, SiOC, SiC, SiBCN, etc. The self-aligned isolation layer 328 may be formed by depositing the dielectric material into the gaps, followed by etching back to the level of the top surface of material 326 that is revealed as described above. The isolation layer 328 is self-aligned as it fills the gaps between the material 326 over the STI region 306 and the remaining channel protecting liner 312.

[0057] FIG. 10 shows a side cross-sectional view 1000 of the FIG. 9 structure following formation of an OPL 330 over the top of the self-aligned isolation layer 328 and the material 326. The OPL 330 may be formed using spin-on coating, using materials similar to that described above with respect to the dummy oxide mask layer 324. The OPL 330 may have a height or vertical thickness (in direction Y-Y') in the range of 20 to 100nm.

[0058] FIG. 11 shows a side cross-sectional view 1100 of the FIG. 10 structure following patterning of gate cuts in the OPL 330. More particularly, FIG. 11 shows a symmetric gate cut 1101 formed in the OPL 330 in the logic region 301, and an asymmetric gate cut 1103 formed in the OPL 330 in the SRAM region 303. The symmetric gate cut 1101 and the asymmetric gate cut 1103 may be formed by patterning a mask over the OPL 330 and etching the exposed portion of the OPL 330 to reveal portions of the underlying self-aligned isolation layer 328. The symmetric gate cut 1101 and asymmetric gate cut 1103 may be defined using lithography. The asymmetric gate cut 1103 exposes portions of the self-aligned isolation layer 328. The isolation layer 328 is self-aligned, and thus the asymmetric gate cut 1103 may therefore be viewed as self-aligned. As noted elsewhere herein, the asymmetric gate cut 1103 in some embodiments may be formed between fin 304-3 providing an SRAM nFET device and fin 304-4 providing an SRAM pFET device. The portion of the self-aligned isolation layer 328 exposed by the asymmetric gate cut 1103 is close to the nanosheet stack above fin 304-4, and thus the asymmetric gate cut 1103 may be referred to as a self-aligned asymmetric gate cut.

[0059] The symmetric gate cut 1101 exposes the self-aligned isolation layer 328 that is formed between the fins 304-1 and 304-2 in the logic region 301. The symmetric gate cut 1101 may have a width or horizontal thickness (in direction X-X') in the range of 15 to 35nm.

[0060] The asymmetric gate cut 1103 exposes at least a portion of the self-aligned isolation layer 328 that is formed over the remaining channel protecting liner 312 as illustrated. The asymmetric gate cut 1103 may have a width or horizontal thickness (in direction X-X) in the range of 15 to 35nm.

[0061] FIG. 12 shows a side cross-sectional view 1200 of the FIG. 11 structure following fill of the symmetric gate cut 1101 and the asymmetric gate cut 1103 with a dielectric material 332. The dielectric material 332 may comprise SiN, SiCO, SiC or another suitable material.

[0062] FIG. 13 shows a side cross-sectional view 1300 of the FIG. 12 structure following removal of the OPL 330 and the sacrificial material (e.g., sacrificial nanosheets 308 and material 326). The OPL 330 may be removed using ashing. The sacrificial material (e.g., 308 and 326) is removed using a selective etch.

[0063] FIG. 14 shows a side cross-sectional view 1400 of the FIG. 13 structure following formation of gate structures 334 (e.g., using a replacement metal gate (RMG) process). The gate structures 334 may include a gate dielectric layer that is conformally deposited followed by formation of a gate conductor layer.

[0064] The gate dielectric layer may be formed of a high-k dielectric material. Examples of high-k materials include but are not limited to metal oxides such as hafnium oxide (Hf0 ₂ ), hafnium silicon oxide (Hf-Si-O), hafnium silicon oxynitride (HfSiON), lanthanum oxide (La ₂ 0 ₃ ), lanthanum aluminum oxide (LaAIOa), zirconium oxide (Zr0 ₂ ), zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide O^Os), titanium oxide (T1O2), barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide (Y ₂ O ₃ ), aluminum oxide (AI ₂ O ₃ ), lead scandium tantalum oxide, and lead zinc niobate. The high-k material may further include dopants such as lanthanum (La), aluminum (Al), and magnesium (Mg). The gate dielectric layer may have a uniform thickness in the range of 1nm to 4nm.

[0065] The gate conductor layer may include a metal gate or work function metal (WFM). In some embodiments, the gate conductor layer is formed using atomic layer deposition (ALD) or another suitable process. For nFET devices, the WFM for the gate conductor layer may be titanium (Ti), aluminum (Al), titanium aluminum (TiAI), titanium aluminum carbon (TiAIC), a combination of Ti and Al alloys, a stack which includes a barrier layer (e.g., of titanium nitride (TiN) or another suitable material) followed by one or more of the aforementioned WFM materials, etc. For pFET devices, the WFM for the gate conductor may be TiN, tantalum nitride (TaN), or another suitable material. In some embodiments, the pFET WFM may include a metal stack, where a thicker barrier layer (e.g., of TiN, TaN, etc.) is formed followed by a WFM such as Ti, Al, TiAI, TiAIC, or any combination of Ti and Al alloys. It should be appreciated that various other materials may be used for the gate conductor layer as desired.

[0066] The processing described above with respect to FIGS. 3-14 advantageously enables the formation of a structure (e.g., an integrated circuit) with both symmetric and asymmetric self-aligned gate isolations. For the gate cut region, an additional gate cut structure is formed over the self-aligned gate isolations. For asymmetric self- aligned gate isolations, some top portion of the isolation structure is formed over the top of a nanosheet stack.

[0067] The process for forming the self-aligned gate isolation includes forming a channel protecting liner (e.g., the dummy oxide layer 312), and using a mask (e.g., the dummy oxide mask 322) to protect at least some of the channel protecting liner and removing the unprotected liner to expose the channel of the nanosheet stacks. A sacrificial liner (e.g., material 326) is formed over the exposed channel of the nanosheet stacks, followed by formation of self-aligned gate isolation (e.g., self-aligned gate isolation layer 328). A sacrificial material (e.g., OPL 330) is formed over the self-aligned gate isolation and the sacrificial liner, followed by formation of gate cuts (e.g., symmetric gate cut 1101 and asymmetric gate cut 1103) into the sacrificial material. The sacrificial material and sacrificial liner are then removed, followed by RMG processing to form the gate structures.

[0068] In some embodiments, a method of forming a semiconductor structure comprises forming a plurality of fins over a top surface of a substrate, forming an STI region over the top surface of the substrate surrounding the plurality of fins, and forming a plurality of nanosheet stacks of channel material over the plurality of fins, the plurality of nanosheet stacks providing channels for one or more nanosheet FETs. The method also comprises forming a channel protecting liner over at least a portion of sidewalls and a top surface of a first one of the plurality of nanosheet stacks formed over a first one of the plurality of fins, the channel protecting liner being further formed over a portion of the STI region extending from the portion of the sidewalls of the first nanosheet stack toward a second one of the plurality of nanosheet stacks formed over a second one of the plurality of fins. The method further comprises forming a plurality of gate stacks surrounding portions of the plurality of nanosheet stacks exposed by the channel protecting liner, forming at least one asymmetric self-aligned gate isolation structure over the channel protecting liner, and forming at least one symmetric self-aligned gate isolation structure over a portion of the STI region between a third one of the plurality of fins and a fourth one of the plurality of fins.

[0069] The asymmetric self-aligned gate isolation structure formed over the channel protecting liner may comprise a first portion formed adjacent the channel protecting liner surrounding sidewalls of the first nanosheet stack and a second portion formed over a top surface of the channel protecting liner surrounding the portion of the top surface of the first nanosheet stack.

[0070] The first nanosheet stack and the second nanosheet stack provide nanosheet channels for nanosheet FETs of at least one SRAM device structure. The first nanosheet stack may provide nanosheet channels for a pFET and the second nanosheet stack provides nanosheet channels for an nFET. A third one of the plurality of nanosheet stacks formed over the third fin and a fourth one of the plurality of nanosheet stacks formed over the fourth fin may provide nanosheet channels for nanosheet FETs of one or more logic device structures.

[0071] Forming the channel protecting liner may comprise forming the channel protecting liner surrounding the plurality of nanosheet stacks and over the STI region between the plurality of fins, forming a dummy gate structure over the channel protecting liner, patterning a gate hard mask over the dummy gate structure, and removing portions of the dummy gate structure exposed by the patterned gate hard mask. Forming the channel protecting liner may further comprise forming source/drain regions in spaces formed by removal of the dummy gate structure, and removing remaining portions of the dummy gate structure. Forming the channel protecting liner may further comprise patterning a mask layer over portions of the channel protecting liner surrounding the portion of the sidewalls and the top surface of the first nanosheet stack and the portion of the STI region extending from the portion of the sidewalls of the first nanosheet toward the second nanosheet stack, and removing portions of the channel protecting liner exposed by the patterned mask layer.

[0072] Forming the plurality of nanosheet stacks may comprise forming alternating layers of a sacrificial material and the channel material, and the method may further comprise selectively growing additional sacrificial material over portions of the plurality of nanosheet stacks exposed by the channel protecting liner. Forming the asymmetric self-aligned gate isolation structure and the symmetric self-aligned gate structure may comprise forming an isolation material over the structure surrounding the additional sacrificial material. Forming the asymmetric self-aligned gate isolation structure and the symmetric self-aligned gate structure may further comprise forming an OPL over the isolation material and the additional sacrificial material. Forming the asymmetric self-aligned gate isolation structure and the symmetric self-aligned gate structure may further comprise patterning the OPL to expose (i) at least a portion of the isolation material formed over the channel protecting liner for the asymmetric self-aligned gate isolation structure and (ii) at least a portion of the isolation material formed over the STI region between the third and fourth nanosheet stacks for the symmetric self-aligned gate isolation structure. Forming the asymmetric self- aligned gate isolation structure and the symmetric self-aligned gate structure may further comprise filling additional isolation material in regions exposed by patterning the OPL.

[0073] Forming the plurality of gate stacks comprises removing the OPL, the sacrificial material of the nanosheet channel stacks, and the additional sacrificial material. Forming the plurality of gate stacks may further comprise forming a gate dielectric and a gate conductor in the spaces formed by removal of the OPL, the sacrificial material of the nanosheet channel stacks, and the additional sacrificial material.

[0074] In some embodiments, a semiconductor structure comprises a substrate, a plurality of fins disposed over a top surface of the substrate, an STI region disposed over the top surface of the substrate surrounding the plurality of fins, and a plurality of nanosheet stacks of channel material disposed over the plurality of fins, the plurality of nanosheet stacks providing channels for one or more nanosheet FETs. The semiconductor structure also comprises a channel protecting liner disposed over at least a portion of sidewalls and a top surface of a first one of the plurality of nanosheet stacks disposed over a first one of the plurality of fins, the channel protecting liner being further disposed over a portion of the STI region extending from the portion of the sidewalls of the first nanosheet stack toward a second one of the plurality of nanosheet stacks disposed over a second one of the plurality of fins. The semiconductor structure further comprises a plurality of gate stacks surrounding portions of the plurality of nanosheet stacks exposed by the channel protecting liner, at least one asymmetric self-aligned gate isolation structure disposed over the channel protecting liner, and at least one symmetric self-aligned gate isolation structure disposed over a portion of the STI region between a third one of the plurality of fins and a fourth one of the plurality of fins.

[0075] The asymmetric self-aligned gate isolation structure disposed over the channel protecting liner may comprise a first portion disposed adjacent the channel protecting liner surrounding sidewalls of the first nanosheet stack and a second portion disposed over a top surface of the channel protecting liner surrounding the portion of the top surface of the first nanosheet stack.

[0076] The first nanosheet stack and the second nanosheet stack may provide nanosheet channels for nanosheet FETs of at least one SRAM device structure. The first nanosheet stack may provide nanosheet channels for a pFET and the second nanosheet stack provides nanosheet channels for an nFET. A third one of the plurality of nanosheet stacks disposed over the third fin and a fourth one of the plurality of nanosheet stacks disposed over the fourth fin may provide nanosheet channels for nanosheet FETs of one or more logic device structures.

[0077] In some embodiments, integrated circuits comprise nanosheet FET structures comprising the above- described semiconductor structures.

[0078] It should be understood that the various layers, structures, and regions shown in the figures are schematic illustrations that are not drawn to scale. In addition, for ease of explanation, one or more layers, structures, and regions of a type commonly used to form semiconductor devices or structures may not be explicitly shown in a given figure. This does not imply that any layers, structures, and regions not explicitly shown are omitted from the actual semiconductor structures. Furthermore, it is to be understood that the embodiments discussed herein are not limited to the particular materials, features, and processing steps shown and described herein. In particular, with respect to semiconductor processing steps, it is to be emphasized that the descriptions provided herein are not intended to encompass all of the processing steps that may be required to form a functional semiconductor integrated circuit device. Rather, certain processing steps that are commonly used in forming semiconductor devices, such as, for example, wet cleaning and annealing steps, are purposefully not described herein for economy of description.

[0079] Moreover, the same or similar reference numbers are used throughout the figures to denote the same or similar features, elements, or structures, and thus, a detailed explanation of the same or similar features, elements, or structures are not repeated for each of the figures. It is to be understood that the terms "about” or "substantially” as used herein with regard to thicknesses, widths, percentages, ranges, etc., are meant to denote being close or approximate to, but not exactly. For example, the term "about” or "substantially” as used herein implies that a small margin of error is present, such as ±5%, preferably less than 2% or 1% or less than the stated amount.

[0080] In the description above, various materials and dimensions for different elements are provided. Unless otherwise noted, such materials are given by way of example only and embodiments are not limited solely to the specific examples given. Similarly, unless otherwise noted, all dimensions are given by way of example and embodiments are not limited solely to the specific dimensions or ranges given.

[0081] Semiconductor devices and methods for forming same in accordance with the above-described techniques can be employed in various applications, hardware, and/or electronic systems. Suitable hardware and systems for implementing embodiments of the invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell and smart phones), solid-state media storage devices, functional circuitry, etc. Systems and hardware incorporating the semiconductor devices are contemplated embodiments of the invention. Given the teachings provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of embodiments of the invention.

[0082] In some embodiments, the above-described techniques are used in connection with semiconductor devices that may require or otherwise utilize, for example, complementary metal-oxide-semiconductors (CMOSs), metal-oxide-semiconductor field-effect transistors (MOSFETs), and/or fin field-effect transistors (FinFETs). By way of non-limiting example, the semiconductor devices can include, but are not limited to CMOS, MOSFET, and FinFET devices, and/or semiconductor devices that use CMOS, MOSFET, and/or FinFET technology.

[0083] Various structures described above may be implemented in integrated circuits. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low- end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.

[0084] The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.