THEREOF

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Patent Application number 62/115,808 filed 13 February 2015, the entire contents of which are incorporated herein by reference for all purposes.

TECHNICAL FIELD

[0002] The present invention relates to semiconductor arrangements and methods for fabricating thereof.

BACKGROUND

[0003] The terahertz (THz) frequency range, from 300 GHz to 3 THz, has been identified as a critical spectrum range for numerous applications such as security screening, medical imaging, radars and communications, biological and material analysis, and etc. However, high cost and low level of integration for III-V devices needed for the systems have limited the usage of terahertz devices. The improvements in the high frequency capability of CMOS have made it possible to consider CMOS as a lower cost alternative for realizing the systems that can greatly expand the use of this spectrum range. At THz, it becomes more feasible to integrate an antenna with other circuits into a single chip in semiconductor technologies than at millimeter-wave frequencies, as the antenna size becomes substantially smaller. For example, a 0.41 -THz push-push oscillator with an on-chip patch antenna may be fabricated in a 6-metal-layer 45-nm digital CMOS technology. The top metal layer may be used to form the patch of size 200x200 μιη . The ground plane may be formed by shunting metal 1 to 5 layers to lower the loss. A 0.65 THz focal-plane array may be fabricated in a 5-metal-layer 0.25-μιη CMOS technology. The top metal layer may be used to form the patch of size 100x88 μιη . The ground plane may be formed by the bottom metal layer. However, existing antennas-on-chip suffer from low power efficiency.

[0004] Therefore, there is a need for a THz antenna device that can integrate an antenna and other circuits into a single package using the standard packaging process, while achieving a reasonable level of efficiency. SUMMARY

[0005] According to various embodiments, there may be provided a semiconductor arrangement including a radio circuitry; an interface pad coupled to the radio circuitry, the interface pad configured to at least one of receive inputs from an antenna and further configured to provide the received inputs to the radio circuitry, or receive outputs from the radio circuitry and further configured to provide the received outputs to the antenna; and a bump provided on the interface pad.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments are described with reference to the following drawings, in which:

[0007] FIG. 1A shows a conceptual diagram of a semiconductor arrangement according to various embodiments.

[0008] FIG. IB shows a conceptual diagram of a semiconductor arrangement according to various embodiments.

[0009] FIG. 2 shows a flow diagram showing a method for fabricating a semiconductor arrangement according to various embodiments.

[0010] FIG. 3 shows a cross-sectional diagram illustrating the structural geometry of a semiconductor arrangement according to various embodiments.

[0011] FIG. 4 shows a cross-sectional diagram illustrating the structural geometry of a semiconductor arrangement according to various embodiments.

[0012] FIG. 5 shows a three-dimensional view of a semiconductor arrangement according to various embodiments.

[0013] FIG. 6 shows a three-dimensional view of a semiconductor arrangement according to various embodiments.

[0014] FIG. 7 shows a three-dimensional view of a semiconductor arrangement according to various embodiments.

[0015] FIG. 8 shows a three-dimensional view of a semiconductor arrangement according to various embodiments. [0016] FIG. 9 shows a three-dimensional view of a semiconductor arrangement according to various embodiments.

[0017] FIG. 10 shows a three-dimensional view of a semiconductor arrangement according to various embodiments.

[0018] FIG. 11 shows a cross-section view of a semiconductor arrangement according to various embodiments.

[0019] FIG. 12 shows a top view of the semiconductor arrangement of FIG. 11.

[0020] FIG. 13 shows a cross-section view of a semiconductor arrangement according to various embodiments.

[0021] FIG. 14 shows a graph showing the simulated antenna performance of an interface pad antenna.

[0022] FIG. 15 shows the radiation pattern of the interface pad antenna of FIG. 14.

[0023] FIG. 16 shows a graph showing how the peak gain and the radiation efficiency of the interface pad antenna of FIG. 14 varies with frequency.

[0024] FIG. 17 shows a graph showing the simulated antenna performance of a semiconductor arrangement according to various embodiments.

[0025] FIG. 18 shows the radiation pattern of the semiconductor arrangement of FIG. 17.

[0026] FIG. 19 shows a graph showing how the peak gain and the radiation efficiency of the semiconductor arrangement of FIG. 17 varies with frequency.

[0027] FIG. 20 shows a graph showing the simulated antenna performance of a semiconductor arrangement according to various embodiments.

[0028] FIG. 21 shows the radiation pattern of the semiconductor arrangement of FIG. 20.

[0029] FIG. 22 shows a graph showing how the peak gain and the radiation efficiency of the pillar semiconductor arrangement of FIG. 20 varies with frequency.

[0030] FIG. 23 shows a graph showing a comparison of peak directivity between the interface pad antenna of FIG. 14, the semiconductor arrangement of FIG. 17 and the semiconductor arrangement of FIG. 20.

[0031] FIG. 24 shows a diagram showing the simulated surface currents on a semiconductor arrangement according to various embodiments.

[0032] FIG. 25 shows a diagram showing the simulated surface currents on a semiconductor arrangement according to various embodiments.

[0033] FIG. 26 shows an on-chip antenna.

[0034] FIG. 27 shows a semiconductor arrangement according to various embodiments.

[0035] FIG. 28 shows a semiconductor arrangement according to various embodiments. [0036] FIG. 29 shows a diagram showing an on-chip dipole antenna.

[0037] FIG. 30 shows a semiconductor arrangement according to various embodiments.

[0038] FIG. 31 shows a semiconductor arrangement according to various embodiments.

[0039] FIG. 32 shows an on-chip patch antenna.

[0040] FIG. 33 shows a semiconductor arrangement according to various embodiments.

[0041] FIG. 34 shows a semiconductor arrangement according to various embodiments.

[0042] FIG. 35 shows an on-chip patch antenna with a feed line.

[0043] FIG. 36 shows a semiconductor arrangement according to various embodiments.

[0044] FIG. 37 shows a semiconductor arrangement according to various embodiments.

[0045] FIG. 38 shows a semiconductor arrangement according to various embodiments.

[0046] FIG. 39 shows a graph showing the simulated antenna performance of the semiconductor arrangement of FIG. 38.

[0047] FIG. 40 shows the radiation pattern of the semiconductor arrangement of FIG. 38.

[0048] FIG. 41 shows a graph showing how the peak gain and the radiation efficiency of the semiconductor arrangement of FIG. 38 varies with frequency.

[0049] FIG. 42 shows a semiconductor arrangement according to various embodiments.

[0050] FIG. 43 shows a bottom view of the interface pad of the semiconductor arrangement of FIG. 42.

[0051] FIG. 44 shows cross-sectional conceptual view of the semiconductor arrangement of FIG. 42.

[0052] FIG. 45 shows a graph showing the simulated antenna performance of the semiconductor arrangement of FIG. 42.

[0053] FIG. 46 shows a graph showing a relationship between the axial ratio and the frequency of the semiconductor arrangement of FIG. 42.

[0054] FIG. 47 shows a graph showing how the peak gain and the radiation efficiency of the semiconductor arrangement of FIG. 42 varies with frequency.

[0055] FIG. 48 shows the radiation pattern of the semiconductor arrangement of FIG. 42.

[0056] FIG. 49 shows a semiconductor arrangement according to various embodiments.

[0057] FIG. 50 shows a graph showing a relationship between peak gain of the semiconductor arrangement of FIG. 49 with the number of radiation elements.

[0058] FIG. 51 shows the normalized radiation pattern of the semiconductor arrangement of FIG. 49, wherein the semiconductor arrangement of FIG. 49 includes 12 radiation elements. DESCRIPTION

[0059] Embodiments described below in context of the devices are analogously valid for the respective methods, and vice versa. Furthermore, it will be understood that the embodiments described below may be combined, for example, a part of one embodiment may be combined with a part of another embodiment.

[0060] In order that the invention may be readily understood and put into practical effect, particular embodiments will now be described by way of examples and not limitations, and with reference to the figures.

[0061] Various embodiments are provided for devices, and various embodiments are provided for methods. It will be understood that basic properties of the devices also hold for the methods and vice versa. Therefore, for sake of brevity, duplicate description of such properties may be omitted.

[0062] It will be understood that any property described herein for a specific device may also hold for any device described herein. It will be understood that any property described herein for a specific method may also hold for any method described herein. Furthermore, it will be understood that for any device or method described herein, not necessarily all the components or steps described must be enclosed in the device or method, but only some (but not all) components or steps may be enclosed.

[0063] The term "coupled" (or "connected") herein may be understood as electrically coupled or as mechanically coupled, for example attached or fixed, or just in contact without any fixation, and it will be understood that both direct coupling or indirect coupling (in other words: coupling without direct contact) may be provided.

[0064] The terahertz (THz) frequency range, from 300 GHz to 3 THz, has been identified as a critical spectrum range for numerous applications such as security screening, medical imaging, radars and communications, biological and material analysis, and etc. However, high cost and low level of integration for III-V devices needed for the systems have limited the usage of terahertz devices. The improvements in the high frequency capability of CMOS have made it possible to consider CMOS as a lower cost alternative for realizing the systems that can greatly expand the use of this spectrum range. At THz, it becomes more feasible to integrate an antenna with other circuits into a single chip in semiconductor technologies than at millimeter-wave frequencies, as the antenna size becomes substantially smaller. For example, a 0.41 -THz push-push oscillator with an on-chip patch antenna may be fabricated in a 6-metal-layer 45-nm digital CMOS technology. The top metal layer may be used to form 2

the patch of size 200x200 μηι . The ground plane may be formed by shunting metal 1 to 5 layers to lower the loss. A 0.65 THz focal-plane array may be fabricated in a 5-metal-layer 0.25-μιη CMOS technology. The top metal layer may be used to form the patch of size 100x88 μιη . The ground plane may be formed by the bottom metal layer. However, existing on-chip antennas suffer from low power efficiency. Therefore, there is a need for a THz antenna device that can integrate an antenna or an antenna array and other circuits into a single package using the standard packaging process, while achieving a reasonable level of efficiency.

[0065] In the context of various embodiments, "interface pad" may be but is not limited to being interchangeably referred to as an "input/output pad".

[0066] FIG. 1A shows a conceptual diagram of a semiconductor arrangement 100A according to various embodiments. The semiconductor arrangement 100A may include a radio circuitry 102; an interface pad 104; and a bump 106. The interface pad 104 may be coupled to the radio circuitry 102 and may be configured to at least one of receive inputs from an antenna and further configured to provide the received inputs to the radio circuitry

102, or receive outputs from the radio circuitry 102 and further configured to provide the received outputs to the antenna. The bump 106 may be provided on the interface pad 104.

[0067] In other words, according to various embodiments, the semiconductor arrangement

100 A may include a radio circuitry 102. The radio circuitry 102 may be provided in a radio chip. The radio chip may be part of the semiconductor arrangement 100A. The radio chip may include a passivation layer, a silicon oxide layer, an on-chip ground layer and a silicon layer. The passivation layer may be arranged above the silicon oxide layer; the silicon oxide layer may be arranged above the on-chip ground layer; the on-chip ground layer may be arranged above the silicon layer; and the silicon layer may be arranged above an off-chip ground layer. The semiconductor arrangement 100A may further include an interface pad 104 coupled to the radio circuitry 102. The interface pad 104 may be provided on the radio chip, for example, at least partially embedded in the passivation layer. The interface pad 104 may be an input/output pad. The interface pad 104 may be configured to receive inputs from an antenna and further configured to provide the received inputs to the radio circuitry 102. The interface pad 104 may be configured to receive outputs from the radio circuitry 102 and further configured to provide the received outputs to the antenna. Instead of being provided on the radio chip, the interface pad 104 may alternatively be provided on a substrate separate from the radio chip. The radio chip may be soldered to a first side of the substrate; and the interface pad 104 may be provided on the first side of the substrate. The interface pad may be coupled to the radio chip by a trace line, the trace line configured to conduct electricity. Alternatively, the interface pad 104 may be provided on a second side of the substrate, wherein the second side opposes the first side. The radio circuitry 102 may be electrically coupled to the substrate by bonding wires. The substrate may be a wafer or part of a package. The semiconductor arrangement 100A may further include a bump 106, provided on the interface pad 104. The bump 106 may be formed directly on the interface pad 104.

[0068] The bump 106 may be formed using flip-chip technology. The bump 106 may include at least one from the group consisting of Au, Cu, Ni, SnAg, SnCu, SnAu and PbSn. The bump 106, which may be one of a ball bump or a pillar bump, may be configured to at least one of enhance a directivity of the antenna or increase a gain of the antenna. The ball bump may have a diameter that is at least substantially equal to 25% of a resonance wavelength of the antenna. The diameter of the ball bump may be less than the length of the interface pad 104. The diameter of the ball bump may be at least substantially in a range of 10% to 25% of the length of the interface pad 104.

[0069] The pillar bump may have a diameter that is at least substantially equal to 25% of the resonance wavelength. The height of the pillar bump may be arbitrary. Therefore, the height of the semiconductor arrangement 100A may not be limited by the height of the pillar bump. The height of the pillar bump may be less than three times the resonance wavelength. The gain and efficiency of the semiconductor 100 A may be the highest when the height of the

2n— 1

pillar bump is at least substantially equal to λ , where λ denotes the resonance wavelength and n denotes an integer. The gain and efficiency of the semiconductor 100A may be the lowest, when the height of the pillar bump is at least substantially equal to -^λ. In other words, the gain and efficiency of the semiconductor 100A may be the highest when the height of the pillar bump is at least substantially equal to 25% of the resonance wavelength multiplied by a factor, the factor being an odd integer. The maximum gain and efficiency may be due to the radiation adding of the current on the surface of the interface pad and the current on the top surface of the pillar bump. The gain and efficiency of the semiconductor 100A may be the lowest when the height of the pillar bump is at least substantially equal to 25% of the resonance wavelength multiplied by a factor, the factor being an even integer. The minimum gain and efficiency may be due to the radiation cancellation of the current on the surface of the interface pad and the current on the top surface of the pillar bump. The pillar bump may include a pillar comprising copper. [0070] FIG. IB shows a conceptual diagram of a semiconductor arrangement 100B according to various embodiments. The semiconductor arrangement 100B may be similar to the semiconductor arrangement 100A in that it may include a radio circuitry 102, an interface pad 104 and a bump 106. The interface pad 104 may be coupled to the radio circuitry 102 and may be configured to at least one of receive inputs from an antenna and further configured to provide the received inputs to the radio circuitry 102, or receive outputs from the radio circuitry 102 and further configured to provide the received outputs to the antenna. The bump 106 may be provided on the interface pad 104. As compared to the semiconductor arrangement 100A, the semiconductor arrangement 100B may further include the antenna 108 and at least one parasitic pad 110. The antenna 108 may be one from the group consisting of microstrip patch antenna, microstrip dipole antenna, microstrip patch antenna, microstrip quasi- Yagi antenna and microstrip bow-tie antenna. The at least one parasitic pad 110 may be arranged adjacent to the interface pad 104. The at least one parasitic pad 110 may be at least substantially identical to the interface pad 104. The parasitic pad 110 may not be coupled to any feed line or feed structures. The parasitic pad 110 may increase the operating bandwidth of the semiconductor arrangement 100B. The antenna 108 may be integral to the interface pad 104. Alternatively, the antenna 108 may be separate from the interface pad 104.

[0071] FIG. 2 shows a flow diagram 200 showing a method for fabricating a semiconductor arrangement according to various embodiments. The method may include process 202, in which a radio circuitry is provided; process 204, in which an interface pad coupled to the radio circuitry is provided, wherein the interface pad is configured to at least one of receive inputs from an antenna and further configured to provide the received inputs to the radio circuitry, or receive outputs from the radio circuitry and further configured to provide the received outputs to the antenna; and process 206, in which a bump is provided on the interface pad. The process of providing the bump on the interface pad may include the abovementioned steps in a sequential order. The process of providing the bump on the interface pad may include depositing a photoresist over the interface pad and forming an opening in the photoresist. The process of providing the bump on the interface pad may further include depositing solder material into the opening, removing the photoresist, and reflowing the solder material to form an at least substantially spherical bump. The at least substantially spherical bump may be a ball bump. Alternatively, the process of providing the bump on the interface pad may further include depositing copper into the opening to form a copper pillar in the opening. The copper pillar may be a pillar bump. [0072] According to various embodiments, the antenna device is an antenna-in-package (AiP) device.

[0073] According to various embodiments, a semiconductor arrangement may include bumps fabricated using the standard flip-chip technology, to enhance the performance of an on-chip antenna and antenna array. The bumps may be at least one of ball bumps or pillar bumps. The bumps may enhance gain of the on-chip antenna by about 5.4dB. As the bump may be provided using conventional flip-chip technology, the semiconductor arrangement may provide cheaper and more reliable antenna solutions than existing antenna solutions such as lens techniques or superstate techniques.

[0074] FIG. 3 shows a cross-sectional diagram illustrating the structural geometry of a semiconductor arrangement 300 according to various embodiments. The semiconductor arrangement 300 may be identical to or at least substantially similar to the semiconductor arrangement 100A of FIG. 1A. The semiconductor arrangement 300 may include a substrate which may be a wafer 330; interface pads 304; and bumps. The wafer 330 may be a silicon (Si) wafer. The bumps may be spherical, referred herein as ball bumps 306. The semiconductor arrangement 300 may further include a passivation layer 332 arranged over the wafer 330 and adjacent to the interface pads 304. The semiconductor arrangement 300A may further include Under Bump Metallization (UBM) 334, underneath the ball bumps 306. The ball bumps 306 may be identical to solder bumps used for soldering two wafer chips together and may be fabricated using conventional flip-chip assembly technologies. The ball bumps 306 may be deposited onto the Si wafer 330 by electroplating on the interface pads 304 of a chip. Each ball bump 306 may be deposited on a respective UBM 334. The ball bumps 306 may include at least one from the group consisting of Au, Cu, Ni, SnAg, SnCu, SnAu and PbSn. The ball bumps 306 may be deposited on the interface pads 304 of a package or a printed circuit board (PCB).

[0075] According to various embodiments, the ball bump 306 may be about 20 μιη in height or in other words, about 20 μιη in diameter. The ball bump pitch, in other words, a distance between the centers of two adjacent solder ball bumps, may be about 40μιη. A height variation of less than 2μιη for bumps of about 25 μιη in height may be achievable on an 8 inch wafer.

[0076] FIG. 4 shows a cross-sectional diagram illustrating the structural geometry of a semiconductor arrangement 400 according to various embodiments. The semiconductor arrangement 400 may be similar to the semiconductor arrangement 300, except that the bumps of the semiconductor arrangement 400 are pillar bumps 406 instead of ball bumps 306. Each pillar bump 406 may include a copper pillar 440. Each pillar bump 406 may optionally include a solder cap 442 arranged over the copper pillar 440. The pillar bumps 406 may be fabricated using the same thin film materials as the conventional ball bumps 306 and may be fabricated using processing techniques similar to processing techniques for fabricating the conventional solder bumps. In addition to the fabrication of ball bumps 306, the fabrication of pillar bumps 406 may further include plating copper over the UBM 334, forming the copper pillar 440 by plating, followed by plating a lead-free solder cap 442 on top of the copper pillar 440. The pillar bumps 406 may be deposited on the interface pads 304 of a package or a PCB.

[0077] According to various embodiments, the pillar bumps 406 may have a diameter of about 20 to 50 μιη and a height of about 30 to 45 μιη.

[0078] According to various embodiments, an antenna device may include at least one of a ball bump antenna or a pillar bump antenna. The antenna device may also include at least one of an array of ball bump antennas or an array of pillar bump antennas. The ball bump antenna or the pillar bump antenna may be realized on input/output (I/O) pads of radio signals on a die. Alternatively, the ball bump antenna or the pillar bump antenna may be realized on the I/O pads of radio signals on a package.

[0079] FIG. 5 shows a three-dimensional view of a semiconductor arrangement 500 according to various embodiments. The semiconductor arrangement 500 may include an array of ball bump antennas on a radio chip 502. The radio chip 502 may be fabricated from a die. Each ball bump antenna may include a ball bump 506 positioned on an interface pad 504 coupled to the radio chip 502. The ball bump 506 may be fabricated using conventional fabrication processes for flip chip bonding. The radio chip 502 may include a radio circuitry configured to process radio signals, for example, changing the frequency of the radio signals, modulating the radio signals according to a modulation scheme or encoding the radio signals.

The radio signals may have a frequency in the range of THz. The radio circuitry may include a receiver of radio signals or a transmitter of radio signals. The radio circuitry may include a transceiver. The radio circuitry may be coupled to the interface pad 504. The interface pad

504 may include an antenna feed structure. The radio chip 502 may include a silicon wafer layer 530; an on-chip ground layer over the silicon layer 530; a silicon oxide layer 550 arranged over the on-chip ground layer; and a passivation layer 532. The interface pad 504 may be at least partially embedded in the passivation layer 532, with a top surface of the interface pad 504 in contact with the ball bump 506. The radio chip 502 may include conducting pads 552. The conducting pads 552 may be arranged on the passivation layer 532. The radio chip may be positioned on a substrate, such as a wafer 554. The wafer 554 may include further conducting pads 556. The radio chip 502 may be electrically coupled to the wafer 554 through bonding wires 558 connecting the conducting pads 552 to the further conducting pads 556. The radio chip 502, together with the wafer 554, may be a wafer package. The wafer package may include other circuitry which receives information from the radio chip 502 or transmits information through the radio chip 502.

[0080] FIG. 6 shows a three-dimensional view of a semiconductor arrangement 600 according to various embodiments. The semiconductor arrangement 600 may be similar to the semiconductor arrangement 500, except that the semiconductor arrangement 600 includes an array of pillar bump antennas instead of an array of ball bump antennas. Each pillar bump antenna may include a pillar bump 606 positioned on an interface pad 504 coupled to the radio chip 502. The pillar bump 606 may be fabricated using conventional fabrication processes for flip chip bonding.

[0081] FIG. 7 shows a three-dimensional view of a semiconductor arrangement 700 according to various embodiments. The semiconductor arrangement 700 may be similar to the semiconductor arrangement 500, except that the array of ball bump antennas is arranged on the wafer 554 instead of on the radio chip 502. The radio chip 502 may include a silicon wafer layer 530; an on-chip ground layer over the silicon wafer layer 530; a silicon oxide layer 550 arranged over the on-chip ground layer; and a passivation layer 532. The radio chip

502 may further include solder structures 770 for bonding the radio chip 502 to the wafer 554.

The radio chip 502 may be flipped and bonded to the wafer 554 such that the top part of the radio chip 502 where the passivation layer 532 is arranged, is facing the wafer 554. The radio chip 502 may be bonded to the wafer 554 by first flipping the radio chip 502 over so that its top side faces down, and aligned so that bonding pads on the radio chip 502 align with matching pads on the wafer 554, and then reflowing the solder structures 770 on the radio chip 502. Each ball bump antenna of the plurality of ball bump antennas may include a ball bump 506 positioned on an interface pad 504 coupled to the radio chip 502. The interface pad

504 may be provided on the wafer 554, instead of on the radio chip 502 as in the semiconductor arrangement 500. The ball bump 506 may be fabricated using conventional fabrication processes for flip chip bonding. The radio chip 502 may be provided in a die. The radio chip 502 may include a radio circuitry configured to process radio signals. The interface pad 504 may be connected to the radio circuitry or to the radio chip 502, through a plurality of trace lines 772. The solder structures 770 may be at least partially embedded in the passivation layer 532, with a top surface of the solder structures 770 in contact with the trace lines 772. The radio chip 502, together with the wafer 554, may be a wafer package. The wafer package may be coupled to external circuitry.

[0082] FIG. 8 shows a three-dimensional view of a semiconductor arrangement 800 according to various embodiments. The semiconductor arrangement 800 may be similar to the semiconductor arrangement of FIG. 7, except that the radio chip 502 may be arranged on a first side of the wafer 554 while the plurality of ball bump antennas may be arranged on a second side of the wafer 554, wherein the second side opposes the first side. In other words, the plurality of ball bump antennas may be provided on an opposite side of the wafer 554 from the radio chip 502. The plurality of ball bump antennas may be connected to the radio chip 502 through a respective plurality of interconnects through the wafer 554. The plurality of interconnects may include a plurality of vias.

[0083] FIG. 9 shows a three-dimensional view of a semiconductor arrangement 900 according to various embodiments. The semiconductor arrangement 900 may be similar to the semiconductor arrangement 600, except that instead of a plurality of ball bump antennas, the semiconductor arrangement includes a plurality of pillar bump antennas. The plurality of pillar bump antennas may be on the same side of the wafer 554 as the radio chip 502. Each pillar bump antenna may include a pillar bump 606.

[0084] FIG. 10 shows a three-dimensional view of a semiconductor arrangement 1000 according to various embodiments. The semiconductor arrangement 1000 may be similar to the semiconductor arrangement 800, except that instead of a plurality of ball bump antennas, the semiconductor arrangement may include a plurality of pillar bump antennas. Each pillar bump antenna may include a pillar bump 606.

[0085] FIG. 11 shows a cross-section view of a semiconductor arrangement 1100 according to various embodiments, showing the geometry and dimensions of the ball bump antenna. The semiconductor arrangement 1100 may include an off-chip ground layer 1112; a silicon layer 330 arranged over the off-chip ground layer 1112; an on-chip ground layer 1110 arranged over the silicon layer 330; a silicon oxide layer 550 arranged over the on-chip ground layer 1110; and a passivation layer 332 arranged over the silicon oxide layer 550. An interface pad 304 may be arranged on the passivation layer 332, wherein the interface pad 304 may be coupled to a radio circuitry. The silicon layer 330 may be about 300 μιη thick with a dielectric constant of 11.9 and resistivity of lOQ.cm. The silicon oxide layer 550 may be about 8 μιη thick with a dielectric constant of 4. A ball bump 306 may be provided on the interface pad 304. The semiconductor arrangement 1100 may be a ball bump antenna. [0086] FIG. 12 shows a top view 1200 of the semiconductor arrangement 1100. The ball bump 306 may have a radius denoted as 1220. The ball bump 306 may be positioned on top of the interface pad 304 having a length denoted as l _pa d 1224 and a width denoted as w _pa d ΥΣΣ1. The rbaii 1220 may be smaller than each of l _pa d 1224 and w _pa d 222.

[0087] FIG. 13 shows a cross-section view of a semiconductor arrangement 1300 according to various embodiments, showing the geometry and dimensions of a pillar bump antenna. The semiconductor arrangement 1300 may be a pillar bump antenna. The semiconductor arrangement 1300 may include an off-chip ground layer 1112; a silicon layer 330 arranged over the off-chip ground layer 1112; an on-chip ground layer 1110 arranged over the silicon layer 330; a silicon oxide layer 550 arranged over the on-chip ground layer 1110; and a passivation layer 332 arranged over the silicon oxide layer 550. An interface pad 304 may be arranged on the passivation layer 332, wherein the interface pad 304 may be coupled to a radio circuitry. A thickness of the silicon layer 330 may be about 300 μιη. The thickness of the silicon layer 330 may be denoted as h _si 1338. The silicon layer 330 may have a dielectric constant of about 11.9 and a resistivity of aboutlOQ.cm. A thickness of the silicon oxide layer 550 may be about 8 μιη. The thickness of the silicon oxide layer 550 may be denoted as h _sio 2 1336. The silicon oxide layer 550 may have a dielectric constant of about 4. A pillar bump 406 may be provided on the interface pad 304. There may be a gap between two adjacent interface pads 304, the width of the gap denoted as w _gap 1332. A height of the pillar bump 406 is denoted as h _{p ar} 1334 while a radius of the pillar bump 406 is denoted as r _{p ar} 1330. The semiconductor arrangement 1300 may further include feed lines 1340. The feed line 1340 may be positioned a distance w _gap apart from a further feed line 1340. The feed line and the further feed line may be configured to provide voltages of different polarities to the pillar bumps 1330.

[0088] In the following, the simulation results of semiconductor arrangements according to various embodiments will be described. The semiconductor arrangements may be fabricated using standard flip-chip technology. The semiconductor arrangements may include THz transceivers integrated with ball bump antenna or pillar bump antenna, in a single wafer package. As can be seen from the simulation results presented subsequently, each of the ball bump antenna and the pillar bump antenna is able to achieve a large gain enhancement.

[0089] FIG. 14 shows a graph 1400 showing the simulated antenna performance of an interface pad antenna. The graph 1400 includes a vertical axis 1442; and a horizontal axis

1444. The vertical axis 1442 indicates the input impedance in ohms (Ω) for the antenna; while the horizontal axis 1444 indicates the frequency in GHz. The antenna studied has dimensions of w _pa d 1222 = l _pa d \22A= 252 μιη. The antenna may be arranged on an 8-μιη thick Si0 ₂ layer on low-resistivity 10-Qcm 300-μιη thick Si substrate. The graph 1400 includes a first line 1446 with square markers representing the imaginary component of the input impedance; and a second line 1448 with circle markers representing the real component of the input impedance. The graph 1400 shows that the second line 1448 peaks at around 285 GHz and that the first line drops to a minimum at around 290GHz. FIG. 14 also shows an inset graph 1410 having a vertical axis 1412 and a horizontal axis 1414. The vertical axis 1412 indicates ISnl in dB while the horizontal axis 1414 indicates the operating frequency in GHz. IS i _l l represents the magnitude of power reflected from the antenna and is also known as the reflection coefficient or return loss. From the graph 1410, the return loss is the lowest at around 290GHz.

[0090] FIG. 15 shows the radiation pattern 1500 of the interface pad antenna of FIG. 14. The radiation pattern 1500 includes a vertical axis 1502 indicating gain of the antenna in dB. The radiation pattern 1500 includes a first plot 1504 indicating cross-polarization on H-plane; a second plot 1506 indicating cross-polarization on E-plane; a third plot 1508 indicating co- polarization on E-plane; and a fourth plot 1510 indicating co -polarization on H-plane. E- plane refers to the electric field while H-plane refers to the magnetizing field. As there is an on-chip ground which serves as a reflector between the silicon substrate and the silicon- dioxide layer, the radiation pattern of the interface antenna appears similar to the radiation pattern of a patch antenna.

[0091] FIG. 16 shows a graph 1600 showing how the peak gain and the radiation efficiency of the interface pad antenna varies with frequency. The graph 1600 includes a first vertical axis 1602 indicating peak gain in dB; a second vertical axis 1604 indicating radiation efficiency; and a horizontal axis 1606 indicating frequency in GHz. The graph 1600 also includes a first plot 1608 representing radiation gain, which is to be read in conjunction with the first vertical axis 1602. The graph 1600 further includes a second plot 1620 representing radiation efficiency, which is to be read in conjunction with the second vertical axis 1604. As can be seen from the first plot 1608, the gain of the interface pad antenna is the highest at about 3.2 dBi when the frequency is about 302 GHz. The second plot 1620 shows that the radiation efficiency is about 34% at 302 GHz.

[0092] FIG. 17 shows a graph 1700 showing the simulated antenna performance of a ball bump antenna. The ball bump antenna may be similar to, or identical to the semiconductor arrangement 1100 of FIG. 11. The ball bump antenna may be formed by adding ball bumps onto the interface pad antenna of FIG. 14. The ball bump may have a radius of about 105um. The graph 1700 includes a vertical axis 1772; and a horizontal axis 1774. The vertical axis 1772 indicates the input impedance in ohms; while the horizontal axis 1774 indicates the frequency in GHz. The graph 1700 includes a first line 1776 with square markers representing the imaginary component of the input impedance; and a second line 1778 with circle markers representing the real component of the input impedance. The graph 1700B shows that the second line 1778 peaks at around 285 GHz and that the first line drops to a minimum at around 290GHz, similar to the graph 1400 for the interface pad antenna which does not include the ball bumps. FIG. 17 also shows an inset graph 1710 having a vertical axis 1712 and a horizontal axis 1714. The vertical axis 1712 indicates ISnl in dB for the ball bump antenna in dB while the horizontal axis 1714 indicates the frequency in GHz. From the graph 1710, the return loss is the lowest at around 290GHz, similar to the graph 1410 of FIG. 14. FIG. 17 shows that the resonance frequency of the ball bump antenna is almost the same as compared with that of the interface pad antenna.

[0093] FIG. 18 shows the radiation pattern 1800 of the ball bump antenna of FIG. 17. The radiation pattern 1800 includes a vertical axis 1802 indicating gain of the ball bump antenna in dB. The radiation pattern 1800 includes a first plot 1804 indicating cross-polarization on H-plane; a second plot 1806 indicating cross-polarization on E-plane; a third plot 1808 indicating co-polarization on E-plane; and a fourth plot 1810 indicating co-polarization on H- plane.

[0094] FIG. 19 shows a graph 1900 showing how the peak gain and the radiation efficiency of the ball bump antenna of FIG. 17 varies with frequency. The graph 1900 includes a first vertical axis 1902 indicating peak gain in dB; a second vertical axis 1904 indicating radiation efficiency; and a horizontal axis 1906 indicating frequency in GHz. The graph 1900 also includes a first plot 1908 representing radiation gain, which is to be read in conjunction with the first vertical axis 1902. The graph 1900 further includes a second plot 1920 representing radiation efficiency, which is to be read in conjunction with the second vertical axis 1904. As can be seen from the first plot 1908, the gain of the ball bump antenna is the highest at about

8 dBi when the frequency is about 310 GHz. The second plot 1910 shows that the radiation efficiency is about 56% at 310 GHz. The maximum radiation efficiency is 72% at 270 THz.

While the resonance frequency of the ball bump antenna is almost the same as compared with that of the interface pad antenna of FIG. 14, the maximum gain of the ball bump antenna is about 4.8 dB higher than the interface pad antenna, as a result of the attached ball bumps.

[0095] FIG. 20 shows a graph 2000 showing the simulated antenna performance of a pillar bump antenna. The pillar bump antenna may be similar to or identical to the semiconductor arrangement 1300. The pillar bump antenna may be formed by adding pillar bumps onto the interface pads of the interface pad antenna of FIG. 14. The pillar bumps may each have a radius of about 105um and a height of about 210um. The graph 2000 includes a vertical axis 2002; and a horizontal axis 2004. The vertical axis 2002 indicates the input impedance in ohms; while the horizontal axis 2004 indicates the frequency in GHz. The graph 2000 includes a first line 2006 with square markers representing the imaginary component of the input impedance; and a second line 2008 with circle markers representing the real component of the input impedance. The graph 2000 shows that the second line 2008 peaks at around 285 GHz and that the first line drops to a minimum at around 290GHz, similar to the graph 1400. FIG. 20 also shows an inset graph 2010 having a vertical axis 2012 and a horizontal axis 2014. The vertical axis 2012 indicates ISnl in dB while the horizontal axis 2014 indicates the frequency in GHz. From the graph 2010, the return loss is the lowest at around 290GHz, similar to the graph 1410 of FIG. 14. FIG. 20 shows that the resonance frequency of the pillar bump antenna is almost the same as compared with that of the interface pad antenna of FIG. 14.

[0096] FIG. 21 shows the radiation pattern 2100 of the pillar bump antenna of FIG. 20. The radiation pattern 2100 includes a vertical axis 2102 indicating gain of the pillar bump antenna in dB. The radiation pattern 2100 includes a first plot 2104 indicating cross-polarization on H-plane; a second plot 2106 indicating cross-polarization on E-plane; a third plot 2108 indicating co-polarization on E-plane; and a fourth plot 2110 indicating co-polarization on H- plane.

[0097] FIG. 22 shows a graph 2200 showing how the peak gain and the radiation efficiency of the pillar bump antenna of FIG. 20 varies with frequency. The graph 2200 includes a first vertical axis 2202 indicating peak gain in dB; a second vertical axis 2204 indicating radiation efficiency; and a horizontal axis 2206 indicating frequency in GHz. The graph 2200 also includes a first plot 2208 representing radiation gain, which is to be read in conjunction with the first vertical axis 2202. The graph 2200 further includes a second plot 2220 representing radiation efficiency, which is to be read in conjunction with the second vertical axis 2204. As The gain of the pillar bump antenna is the highest at about 8.9 dBi when the frequency is about 300 GHz. The radiation efficiency is about 70% at 290 GHz. The maximum radiation efficiency is about 75% at 260 GHz. While the resonance frequency of the pillar bump antenna is almost the same as compared with that of the interface pad antenna of FIG. 14, the maximum gain of the pillar bump antenna is about 5.8 dB higher than the interface pad antenna, as a result of the attached pillar bumps. The graph 2200 demonstrates that the pillar bump can also be used to improve the radiation gain.

[0098] FIG. 23 shows a graph 2300 showing a comparison of peak directivity between the interface pad antenna of FIG. 14, the ball bump antenna of FIG. 17 and the pillar bump antenna of FIG. 20. The graph 2300 includes a vertical axis 2302 indicating peak directivity; and a horizontal axis 2304 indicating frequency in GHz. The graph 2300 further includes a first plot 2306 representing the peak directivity of the interface pad antenna; a second plot 2308 representing the peak directivity of the ball bump antenna; and a third plot 2310 representing the peak directivity of the pillar bump antenna. The peak directivities clearly illustrate that the each of the ball bump antenna and the pillar bump antenna is capable of achieving a higher directivity of about 5dB higher than the interface pad antenna, at the resonance frequency. As seen in FIGS. 19 and 22, the ball bump antenna and the pillar bump antenna can also achieve higher radiation efficiency than the interface pad antenna. The increased gain via the ball bump or the pillar bump may be due to enhanced directivity and the improved radiation efficiency.

[0099] FIG. 24 shows a diagram 2400 showing the simulated surface currents on a ball bump antenna according to various embodiments. The diagram 2400 includes a top view 2402 of the ball bump antenna; and a side view 2404 of the ball bump antenna. The surface currents on the ball bump antenna were plotted based on electromagnetic simulation, in order to study the improvements in directivity of the ball bump antenna over a pad antenna.

[0100] FIG. 25 shows a diagram 2500 showing the simulated surface currents on a pillar bump antenna according to various embodiments. The diagram 2500 includes a top view 2502 of the pillar bump antenna; and a side view 2504 of the pillar bump antenna. The surface currents on the pillar bump antenna were plotted based on electromagnetic simulation, in order to study the improvements in directivity of the pillar bump antenna over a pad antenna.

[0101] From FIGS. 24 and 25, it can be seen that on the top surface, the currents works as a dipole which operates as the second radiator, while the original radiator is via the currents on the interface pad. Hence, the ball bump antenna and the pillar bump antenna can each be modeled as two dipole array with a reflector. The reflector may be the on-chip ground layer.

[0102] The simulation results shown in FIGS. 14-25 are also applicable to the semiconductor arrangements shown in FIGS. 32-34.

[0103] According to various embodiments, the semiconductor arrangement may include an on-chip antenna and a bump. The bump may be one of ball bump or pillar bump. As demonstrated in FIGS. 14-25, the addition of ball bumps or pillar bumps may greatly enhance the performance of the on-chip antenna. The ball bumps or pillar bumps may be added on the pad antennas using standard flip-chip technology. The mechanism of the gain enhancement of the ball bump antenna and the pillar bump antenna, may be improved directivity and efficiency. The improved directivity may result from a more optimal array factor while the improved efficiency may result from reducing the lossy effect from the silicon substrate.

[0104] FIG. 26 shows a semiconductor arrangement 2600. The semiconductor arrangement 2600 may include an on-chip patch antenna 2602 placed adjacent and in between two parasitic pads 2604. The on-chip patch antenna 2602 may be arranged on an 8-μιη thick Si0 ₂ layer on low-resistivity 10-Qcm 300-μιη thick Si substrate. The parasitic pads 2604 may be arranged in the E-plane. The gap distance between the patch antenna pad 2602 and any one of the parasitic pads 2604 may be about 30 μιη. The parasitic pads may present limited impact to the resonance frequency of the on-chip patch antenna. The maximum gain and maximum radiation efficiency of the semiconductor arrangement 2600 may be similar to that of an on- chip patch antenna without parasitic pads.

[0105] FIG. 27 shows a semiconductor arrangement 2700 according to various embodiments. The semiconductor arrangement 2700 may be similar to the semiconductor arrangement 2600 but further including a ball bump 2706 on top of each parasitic pad 2604 and patch antenna 2602. The patch antenna 2602 and the parasitic pads 2604 may be arranged on an 8-μιη Si0 ₂ layer on a low-resistivity 10-Qcm 300-μιη thick Si substrate. The parasitic pads 2604 and ball bumps 2706 may be added on the E-plane. The gap distance between the patch antenna 2602 pad and the parasitic pad 2604 may be about 30 μιη. The semiconductor arrangement 2700 may also be referred herein as a ball bump antenna.

[0106] The resonance frequency of the semiconductor arrangement 2700 may be similar to that of the on-chip patch antenna with parasitic pads of FIG. 27, in other words, the semiconductor arrangement 2600. However, the gain of the ball bump antenna and the radiation efficiency of the ball bump antenna with parasitic pads may be better than that of the on-chip patch antenna without parasitic pads.

[0107] FIG. 28 shows a semiconductor arrangement 2800. The semiconductor arrangement

2800 may be similar to the semiconductor arrangement 2700 except that the parasitic pads

2604 are arranged in the H-plane. A ball bump 2706 may be arranged on top of each parasitic pad 2604, as well as on top of the patch antenna 2602. Each of the patch antenna 2602 and the parasitic pad 2604 may be positioned on an 8-μιη Si0 ₂ layer on a low-resistivity 10-Qcm

300-μιη thick Si substrate. The gap distance between the patch antenna 2602 and each of the parasitic pads 2604 is about 30 μηι. The semiconductor arrangement 2800 may also be referred herein as a ball bump antenna. The maximum gain of the ball bump antenna may be similar to the maximum radiation gain and maximum radiation efficiency of the semiconductor arrangement 2700. In other words, when the parasitic pads and parasitic balls are placed on the H plane as shown in FIG. 28, there may be limited contribution to the maximum radiation gain and maximum radiation efficiency.

[0108] FIG. 29 shows a diagram showing a semiconduc _t or arrangement 2900 including a dipole antenna 3102 and two interface pads 3104. The semiconductor arrangement 2900 may be an on-chip dipole antenna. Common forms of on-chip antennas include microstrip dipole, patch, quasi- Yagi, and bow-tie. The dipole antenna 3102 may be arranged on an 8-um Si0 ₂ layer on low-resistivity 10-Ω 300-um thick Si substrate. The dipole antenna 3102 may be designed to be a half-wavelength dipole. The length and width of a dipole arm may be equal to quarter wavelength, i.e. a quarter of the desired resonance wavelength. The semiconductor arrangement 2900 is used as a reference antenna for comparing the simulation results of other semiconductor arrangements discussed below.

[0109] FIG. 30 shows a semiconductor arrangement 3000 including a dipole antenna 3102 and two interface pads 3104, according to various embodiments. In addition to the semiconductor arrangement 2900, the semiconductor 3000 further includes a ball bump 2706 on top of each interface pad 3104. The semiconductor arrangement 3000 may be an on-chip ball bump antenna. The dipole antenna 3102 may be arranged on an 8-μιη Si0 ₂ layer on low- resistivity 10-Qcm 300-μιη thick Si substrate. The diameter of each ball bump 2706 may be designed to be slightly less than quarter wavelength. The resonance frequency of the semiconductor arrangement 3000 may be similar to that of the semiconductor arrangement 2900 but the maximum gain of the semiconductor arrangement 3000 may be at least substantially higher than the semiconductor arrangement 2900, as a result of the attached ball bumps 2706.

[0110] FIG. 31 shows a semiconductor arrangement 3100 according to various embodiments.

The semiconductor arrangement 3100 may be similar to the semiconductor arrangement 3000 except that the ball bumps 2706 are replaced with pillar bumps 3306. The semiconductor arrangement 3100 may include a dipole antenna 3102, two interface pads 3104 and a pillar bump 3306 on top of each interface pad 3104. The semiconductor arrangement 3100 may be an on-chip pillar bump antenna. The dipole antenna 3102 may be arranged on an 8-μιη Si0 ₂ layer on low-resistivity 10-Qcm 300-μιη thick Si substrate. The diameter and height of a pillar bump 3306 may be designed to be slightly less than quarter wavelength. The resonance frequency of the pillar bump antenna may be almost the same as compared with that of the semiconductor arrangement 2900. However, the maximum gain of the pillar bump antenna may be at least substantially higher, as a result of the attached pillar bumps 3306. The enhancement in gain achieved by adding ball bumps or pillar bumps to an on-chip antenna can be understood by comparing the current distributions of the semiconductor arrangements. The enhancement in gain may be due to better directivity, in other words, array factor; and better efficiency. The improvement in efficiency may be mainly due to radiation efficiency from the top surfaces of the balls and the pillars.

[0111] FIG. 32 shows a semiconductor arrangement 3200. The semiconductor arrangement 3200 may include a patch antenna 3402. The patch antenna 3402 may include an interface pad. The patch antenna 3402 may be provided on an 8-μιη Si0 ₂ layer on low-resistivity 10- Qcm 300-μιη thick Si substrate. The patch antenna 3402 may be fed by via from a first metal layer up to a top metal layer. The semiconductor arrangement 3200 may be used as a reference for comparison with other semiconductor arrangements. The on-chip patch antenna 3402 may be designed to be quarter-wavelength patch. The length of the patch antenna 3402 may be equal to quarter-wavelength and the width of the patch antenna 3402 may be larger than, or equal to quarter-wavelength.

[0112] FIG. 33 shows a semiconductor arrangement 3300 according to various embodiments. The semiconductor arrangement 3300 may be similar to the semiconductor arrangement 3200 but it may further include a ball bump 2706 on top of the patch antenna 3402. Like the semiconductor arrangement 3200, the semiconductor arrangement 3300 may include an on- chip patch antenna 3402 on an 8-μιη Si0 ₂ layer on low-resistivity 10-Qcm 300-μιη thick Si substrate. The patch antenna 3402 may include an interface pad.

[0113] FIG. 34 shows a semiconductor arrangement 3400 according to various embodiments. The semiconductor arrangement 3400 may be similar to the semiconductor arrangement 3300 except that the ball bump 2706 is replaced by a pillar bump 3306. The semiconductor arrangement 3400 may include an on-chip patch antenna 3402 on an 8-μιη Si02 layer on low-resistivity 10-Qcm 300-μιη thick Si substrate.

[0114] FIG. 35 shows a semiconductor arrangement 3500. The semiconductor arrangement

3500 may include an on-chip patch antenna 3402 on an 8-μιη Si0 ₂ layer on low-resistivity

10-Qcm 300-μιη thick Si substrate. The semiconductor arrangement 3500 may further include a feed line 3702 coupled to the patch antenna 3402. The feed line 3702 may be a quarter-wavelength feed line. The patch antenna 3402 may be fed by a via at the end of the feed line 3702 from a first metal layer up to a top metal layer. The semiconductor arrangement 3500 is used as a reference antenna for comparing with other semiconductor arrangements. The on-chip patch antenna 3402 may be designed to be a quarter-wavelength patch antenna. The length of the patch may be equal to quarter-wavelength and the width of the patch may be larger than or equal to quarter-wavelength.

[0115] FIG. 36 shows a semiconductor arrangement 3600 according to various embodiments. The semiconductor arrangement 3600 may be similar to the semiconductor arrangement 3500, but may further include a ball bump 2706 on the patch antenna 3402.

[0116] FIG. 37 shows a semiconductor arrangement 3700 according to various embodiments. The semiconductor arrangement 3700 may be similar to the semiconductor arrangement 3600, except that the ball bump 2706 is replaced by a pillar bump 3306.

[0117] FIG. 38 shows a semiconductor arrangement 3800. The semiconductor arrangement 3800 may include an on-chip pillar bump monopole antenna 4006 on an 8-μιη Si0 ₂ layer on low-resistivity 10-Qcm 300-μιη thick Si substrate. The pillar bump monopole antenna 4006 may be thought of or considered as a monopole antenna. Similarly, an array of pillar bump antenna 4006 may also be thought of or considered as a monopole antenna. In other words, the pillar bump monopole antenna 4006 or an array of pillar bump monopole antenna 4006 may be configured to function as a monopole antenna; and may have a radiation pattern similar to that of a monopole antenna. The pillar bump monopole antenna 4006 may radiate in a lateral direction, which is different from an on-chip antenna or an array of on-chip antenna that radiates in the bore sight direction as shown above. The length of the pillar bump monopole antenna 4006 may be designed to be quarter wavelength long and its diameter should be much smaller than a wavelength of the resonance frequency. The pillar bump monopole antenna 4006 may be arranged on an interface pad 4004. The interface pad 4004 may include a patch antenna.

[0118] FIG. 39 shows a graph 3900 showing the simulated antenna performance of the semiconductor arrangement 3800. The graph 3900 includes a vertical axis 4102; and a horizontal axis 4104. The vertical axis 4102 indicates the input impedance in ohms; while the horizontal axis 4104 indicates the frequency in GHz. The graph 3900 includes a first line

4106 representing the imaginary component of the input impedance; and a second line 4108 with representing the real component of the input impedance. FIG. 39 also shows an inset graph 4110 having a vertical axis 4112 and a horizontal axis 4114. The vertical axis 4112 indicates ISnl in dB while the horizontal axis 4114 indicates the frequency in GHz.

[0119] FIG. 40 shows the radiation pattern 4000 of the semiconductor arrangement 3800.

The radiation pattern 4000 includes a vertical axis 4202 indicating gain of the antenna in dB. The radiation pattern 4000 includes a first plot 4204 indicating cross-polarization on H-plane; a second plot 4206 indicating cross -polarization on E-plane; a third plot 4208 indicating co- polarization on E-plane; and a fourth plot 4210 indicating co-polarization on H-plane.

[0120] FIG. 41 shows a graph 4100 showing how the peak gain and the radiation efficiency of the semiconductor arrangement 3800 varies with frequency. The graph 4100 includes a first vertical axis 4302 indicating peak gain in dB; a second vertical axis 4304 indicating radiation efficiency; and a horizontal axis 4306 indicating frequency in GHz. The graph 4100 also includes a first plot 4308 representing radiation gain, which is to be read in conjunction with the first vertical axis 4302. The graph 4100 further includes a second plot 4310 representing radiation efficiency, which is to be read in conjunction with the second vertical axis 4304. As can be seen from the first plot 4308, the peak realized gain of the antenna is 0.7dBi at 0.29THz and the radiation efficiency is 65% at 0.29THz.

[0121] FIG. 42 shows a semiconductor arrangement 4200 according to various embodiments, the semiconductor arrangement 4200 including a pillar bump 3306 over an interface pad 4004, arranged over an 8-μιη Si0 ₂ layer on low-resistivity 10-Qcm 300-μιη thick Si substrate. The pillar bump 3306 may be differentially excited by two anti-phased feeding pins under the interface pad 4004 and the circular polarization bandwidth may be from 0.22 to 0.39 THz.

[0122] FIG. 43 shows a bottom view 4300 of the interface pad 4004 of the semiconductor arrangement 4200. A first feeding pin 4502A and a second feeding pin 4502B may be arranged under the interface pad 4004, wherein the feeding pins may be configured to feed radio signals to the pillar bump 3306 through a respective via.

[0123] FIG. 44 shows cross-sectional conceptual view 4400 of the semiconductor arrangement 4200. The feeding pins may be arranged under the interface pad 4004 and electrically coupled to the pillar bump 3306. The first feeding pin 4502A may be providing a positive voltage to the pillar bump 3306 whereas the second feeding pin 4502B may be providing a negative voltage to the pillar bump 3306. In other words, the first feeding pin 4502A and the second feeding pin 4502B may be a pair of anti-phased feeding pins. By providing the anti-phased input to the pillar bump 3306, the pair of feeding pins is configured to generate a circularly polarized signal.

[0124] FIG. 45 shows a graph 4500 showing the simulated antenna performance of the semiconductor arrangement 4200. The graph 4500 includes a vertical axis 4702; and a horizontal axis 4704. The vertical axis 4702 indicates the input impedance in ohms; while the horizontal axis 4704 indicates the frequency in GHz. The graph 4500 includes a first line 4706 representing the imaginary component of the Zl l input impedance; a second line 4708 with representing the real component of the Zl l input impedance; a third line 4710 representing the imaginary component of the Z21 input impedance; and a fourth line 4712 with representing the real component of the Z21 input impedance.

[0125] FIG. 46 shows a graph 4600 showing a relationship between the axial ratio and the frequency for the semiconductor arrangement 4200. The graph 4600 includes a vertical axis 4802 indicating the axial ratio in dB; and a horizontal axis 4804 indicating frequency in GHz. The axial ratio is an indicator of the polarization type of an antenna. When the axial ratio is less than 3dB, the polarization may be circular polarization. Circular polarization antennas may have the benefit of receiving electromagnetic waves of any type of polarization, while linear polarization antennas may only receive electromagnetic waves of the same linear polarization.

[0126] FIG. 47 shows a graph 4700 showing how the peak gain and the radiation efficiency of the semiconductor arrangement 4200 varies with frequency. The graph 4700 includes a first vertical axis 4902 indicating peak gain in dB; a second vertical axis 4904 indicating radiation efficiency; and a horizontal axis 4906 indicating frequency in GHz. The graph 4700 also includes a first plot 4908 representing radiation gain, which is to be read in conjunction with the first vertical axis 4902. The graph 4700 further includes a second plot 4910 representing radiation efficiency, which is to be read in conjunction with the second vertical axis 4904. As can be seen from the first plot 4908, the peak realized gain of the antenna is 4.6 dBi at 0.315 THz and the radiation efficiency is 51% at 0.315 THz.

[0127] FIG. 48 shows the radiation pattern 4800 of the semiconductor arrangement 4200. The radiation pattern 4800 includes a vertical axis 5002 indicating gain of the antenna in dB. The radiation pattern 4800 includes a first plot 5004 indicating cross-polarization on H-plane; a second plot 5006 indicating cross -polarization on E-plane; a third plot 5008 indicating co- polarization on E-plane; and a fourth plot 5010 indicating co-polarization on H-plane.

[0128] FIG. 49 shows a semiconductor arrangement 4900 according to various embodiments, the semiconductor arrangement 4900 including a linear array of ball bumps 2706, wherein each ball bump 2706 is arranged over an interface pad 4004. The ball bumps may be positioned on an 8-μιη Si0 ₂ layer on low-resistivity 10-Qcm 300-μιη thick Si substrate. Each ball bump 2706 may be at least substantially identical to the other ball bumps 2706 in the array. The array may include at least one row of ball bumps 2706. Each row may include at least one ball bump 2706. Each interface pad 4004 may be coupled to a feed line. Each ball bump 2706, together with the respective interface pad 4004 and feed line, may be considered as a radiation element. The distance between each radiation element may be quarter- wavelength at 0.32 THz. The radiation elements may be arranged to construct a circular array, a square array and other arrays of any other shaped.

[0129] FIG. 50 shows a graph 5000 showing a relationship between peak gain of the semiconductor arrangement 4900 with the number of radiation elements. The graph 5000 includes a vertical axis 5202 indicating peak gain in dB; and a horizontal axis 5204 indicating the number of radiation elements. The graph 5000 shows that the peak gain increases as the number of radiation elements increases.

[0130] FIG. 51 shows the normalized radiation pattern 5100 of the semiconductor arrangement 4900, wherein the semiconductor 4900 includes 12 radiation elements. The radiation pattern 5100 includes a vertical axis 5302 indicating gain of the antenna in dB; and a horizontal axis 5304 indicating azimuth angle in degrees. The radiation pattern 5100 includes a first plot 5306 indicating cross-polarization on H-plane; a second plot 5308 indicating cross-polarization on E-plane; a third plot 5310 indicating co-polarization on E- plane; and a fourth plot 5312 indicating co-polarization on H-plane.

[0131] According to various embodiments, a semiconductor arrangement may include an on- chip dipole antenna and at least one of a ball bump or a pillar bump. The new techniques for fabricating antennas, using balls and pillars from the standard flip-chip technology, may greatly enhance the performance of on-chip antennas. In the above-described simulations, it has been demonstrated that the peak gain of a conventional on-chip dipole antenna maybe increased from 5.7dBi to 11.1 dBi, by simply adding two bumps. The mechanism of gain enhancement by 5.4 dB may be due to improved directivity (array factor) and efficiency (less effect of lossy Si substrate).

[0132] According to various embodiments, a semiconductor arrangement may include a via- fed on-chip patch antenna and at least one of a ball bump or a pillar bump. The simulation results have also shown that the peak gain of a conventional via-fed on-chip patch antenna may be increased from 2.3 dBi to 5.13 dBi, by adding a ball bump on the patch antenna. Similarly the peak gain of the on-chip patch antenna may be increased to 5.3 dBi by adding a pillar bump.

[0133] According to various embodiments, a semiconductor arrangement may include a microstrip-line-fed on-chip patch antenna and at least one of a ball bump or a pillar bump.

The simulation results have also shown that the peak gain of a microstrip-line-fed on-chip patch antenna may be increased from 1.0 dBi to 2.8 dBi, by adding a ball bump. Similarly, the peak gain of the microstrip-line-fed on-chip patch antenna may be increased to 3.3 dBi by adding a pillar bump. The mechanism of gain enhancement by about 2 to 3 dB may be due to improved directivity (array factor) and efficiency (less effect of lossy Si substrate).

[0134] According to various embodiments, a semiconductor arrangement may be configured to function as a monopole antenna. The current distributions simulations have also shown that a copper pillar antenna or array may function as a monopole antenna or array. A copper pillar antenna or array may radiates in a lateral direction.

[0135] According to various embodiments, the semiconductor arrangement may be a circularly-polarized on-chip antenna or a circularly-polarized on-chip antenna array.

[0136] According to various embodiments, the method for fabricating a semiconductor arrangement may be applied in highly-integrated THz systems, using standard flip-chip technology. The method may realize antennas with high gain using at a lower cost and higher reliability than existing solutions.

[0137] While embodiments of the invention have been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced. It will be appreciated that common numerals, used in the relevant drawings, refer to components that serve a similar or the same purpose.