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Patent Searching and Data

Document Type and Number:
WIPO Patent Application WO/2018/025597
Kind Code:
Provided is a semiconductor chip, using a nanowire FET, that has a layout configuration effective in facilitating easy manufacturing. A semiconductor chip (1) is provided with: a first block (100) that includes a standard cell (110) having a nanowire FET; and a second block (400) that includes a nanowire FET. On the first and second blocks (100, 400), the arrangement pitch, in the Y direction, of nanowires (111, 411) extending in the X direction is an integral multiple of a pitch P1, and the arrangement pitch, in the X direction, of pads (112, 412) is an integral multiple of a pitch P2.

SHIMBO Hiroyuki
Application Number:
Publication Date:
February 08, 2018
Filing Date:
July 11, 2017
Export Citation:
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SOCIONEXT INC. (2-10-23 Shin-Yokohama, Kohoku-Ku Yokohama-sh, Kanagawa 33, 〒2220033, JP)
International Classes:
H01L21/82; H01L21/822; H01L21/8238; H01L27/04; H01L27/088; H01L27/092; H01L29/06
Attorney, Agent or Firm:
MAEDA & PARTNERS (Shin-Daibiru Bldg. 23F, 2-1 Dojimahama 1-chome, Kita-ku, Osaka-sh, Osaka 04, 〒5300004, JP)
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