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Title:
SEMICONDUCTOR CIRCUIT, DRIVING METHOD AND ELECTRONIC APPARATUS
Document Type and Number:
WIPO Patent Application WO/2017/199677
Kind Code:
A1
Abstract:
A semiconductor circuit includes first (IV1, IV3) and second (IV2, IV4) circuits, first (31) and second (32) transistors, a first storage element (35), and a driver (22, 23, 52, 53). The first (IV1, IV3) and second (IV2, IV4) circuits, respectively, apply inverted voltages of voltages at first (N1) and second (N2) nodes to the second (N2) and first (N1) nodes. The first transistor (31) is turned on to couple the first (N1) and third nodes. The second transistor (32) includes a gate coupled to the first node (N1), a drain and a source. One of the drain and the source is coupled to the third node, and another is supplied with a first control voltage (SCL1). The first storage element (35) includes a first end coupled to the third node and a second end supplied with a second control voltage (SCTRL). The first storage element (35) is able to take a first or second resistance state. The driver (22, 23, 52, 53) controls operation of the first transistor (31) and generates the first (SCL1) and second (SCTRL) control voltages.

Inventors:
KANDA, Yasuo (1-7-1 Konan, Minato-k, Tokyo 75, 〒1080075, JP)
TORIGE, Yuji (SONY LSI DESIGN INCORPORATED, 4-16-1 Okata, Atsugi-sh, Kanagawa 21, 〒2430021, JP)
Application Number:
JP2017/015850
Publication Date:
November 23, 2017
Filing Date:
April 20, 2017
Export Citation:
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Assignee:
SONY CORPORATION (1-7-1, Konan Minato-k, Tokyo 75, 〒1080075, JP)
International Classes:
G11C14/00; G11C7/20; G11C11/16; G11C11/412; G11C11/419; G11C13/00
Attorney, Agent or Firm:
TSUBASA PATENT PROFESSIONAL CORPORATION (3F Sawada Building, 15-9 Shinjuku 1-chome, Shinjuku-k, Tokyo 22, 〒1600022, JP)
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