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Patent Searching and Data

Document Type and Number:
WIPO Patent Application WO/2017/208901
Kind Code:
Provided is a semiconductor computing device which enables a broadband NoC by using, as a communication path among a plurality of computing units, interlayer wiring of a three-dimensional integrated circuit. A semiconductor computing device 10 includes element layers in which computing units 111 to 113 are respectively arranged in rectangular regions each having a lengthwise dimension Lv and a crosswise dimension Lh, and in which two or more of the computing units 111 to 113 are arranged in a two-dimensional array in the same layer. The element layers 121 to 12A are stacked. The element layers are stacked such that, in the first element layer 121 and the second element layer 122 adjacent to each other in the stacking direction, the computing units, the arrangement positions of which overlap, are arranged so as to be shifted relative to each other in the diagonal direction of one of the computing units in the element layers.

OUCHI Shinichi (Tsukuba Central 2 1-1, Umezono 1-chome, Tsukuba-sh, Ibaraki 68, 〒3058568, JP)
FUKETA Hiroshi (Tsukuba Central 2 1-1, Umezono 1-chome, Tsukuba-sh, Ibaraki 68, 〒3058568, JP)
Application Number:
Publication Date:
December 07, 2017
Filing Date:
May 23, 2017
Export Citation:
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NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY (3-1 Kasumigaseki 1-chome, Chiyoda-ku Tokyo, 21, 〒1008921, JP)
International Classes:
H01L21/822; H01L21/82; H01L27/04
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