Title:
SEMICONDUCTOR DEVICE, SEMICONDUCTOR CHIP, AND SYSTEM
Document Type and Number:
WIPO Patent Application WO/2017/141505
Kind Code:
A1
Abstract:
To suppress lowering of inductance of an inductor in a plurality of semiconductor chips laminated to each other.
A semiconductor device of the present invention is provided with first and second semiconductor chips laminated to each other, a first inductor, a disposition-regulated region, and a circuit. In the semiconductor device, the first inductor is disposed on the first semiconductor chip. The disposition-regulated region is provided in a region of the second semiconductor chip, said region corresponding to the first inductor. The circuit is disposed in a region of the second semiconductor chip, said region excluding the disposition-regulated region.
Inventors:
SAEKI TAKANORI (JP)
Application Number:
PCT/JP2016/083256
Publication Date:
August 24, 2017
Filing Date:
November 09, 2016
Export Citation:
Assignee:
SONY CORP (JP)
International Classes:
H01F17/00; H01L21/822; H01F27/00; H01L27/04
Foreign References:
| JP2005217804A | 2005-08-11 | |||
| JPH1168033A | 1999-03-09 | |||
| JP2010016142A | 2010-01-21 | |||
| JP2010278400A | 2010-12-09 |
Attorney, Agent or Firm:
MARUSHIMA, Toshikazu (JP)
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