SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATION METHOD

Title:

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATION METHOD

Document Type and Number:

WIPO Patent Application WO/2014/073656

Kind Code:

A1

Abstract:

A protector diode (101) is configured with a basic structure (103) of n+ layer (11)/n- layer (10)/ p+ layer (12)/ n- layer (10). By treating p-type layers which configure the protector diode (101) as the heavily doped p+ layers (12), stretching of a depletion layer is alleviated, and it is possible to reduce the surface area of the protector diode (101). By forming the lightly doped n- layers (10) of a polysilicon layer (9), which configures the protector diode (101), with an ion implantation of phosphorus atoms, which have a large diffusion coefficient, and diffusing the phosphorus atoms, which are implanted in the polysilicon layer (9), by heat treatment at temperatures of 1000°C or higher, it is possible to make uniform doping profiles in the depth direction of the n- layers (10). As a result, pn junction surfaces between the heavily doped p+ layers (12) and the lightly doped n- layers (10) are approximately perpendicular to a substrate surface, and it is possible to alleviate electrical field concentrations at pn junctions between the p+ layers (12) and the n- layers (10).

Inventors:

NAITO TATSUYA (JP)

Application Number:

PCT/JP2013/080301

Publication Date:

May 15, 2014

Filing Date:

November 08, 2013

Export Citation:

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Assignee:

FUJI ELECTRIC CO LTD (JP)

International Classes:

H01L27/04; H01L21/329; H01L21/822; H01L29/739; H01L29/78; H01L29/861; H01L29/866; H01L29/868

Foreign References:

JPH1065157A	1998-03-06
JP2002043574A	2002-02-08
JPH0918001A	1997-01-17
JP2012005009A	2012-01-05
JPH09186315A	1997-07-15
JPH0888354A	1996-04-02
JPH0918001A	1997-01-17
JP2002043574A	2002-02-08

Other References: