SEMICONDUCTOR DEVICE HAVING A BYTE-ERASABLE EEPROM MEMORY

WIPO Patent Application WO2003047163

A3

The invention relates to a semiconductor device having a byte-erasable EEPROM memory comprising a matrix of rows and columns of memory cells. In order to provide a semiconductor device having a byte-erasable EEPROM which has a reduced chip size and increased density and which is suitable for low-power applications it is proposed according to the present invention that the memory cells each comprise a selection transistor having a selection gate and, arranged in series therewith, a memory transistor having a floating gate and a control gate, the selection transistor being further connected to a source line of the byte-erasable EEPROM memory, which source line is common for a plurality of memory cells, and the memory transistor being further connected to a bit line of the byte-erasable EEPROM memory, wherein the columns of memory cells are located in separate p-type wells separated by n-type wells. Preferably, high voltage switching elements are provided for dividing global control gates into local control gates for each column of bytes.

DORMANS GUIDO J M (NL)
VERHAAR ROBERTUS D J (NL)
GARBE JOACHIM C H (NL)

PCT/IB2002/004473

November 27, 2003

October 24, 2002

Click for automatic bibliography generation  

KONINKL PHILIPS ELECTRONICS NV (NL)
DORMANS GUIDO J M (NL)
VERHAAR ROBERTUS D J (NL)
GARBE JOACHIM C H (NL)

G11C16/04; H01L21/8247; G11C16/02; H01L27/115; H01L29/788; H01L29/792; H04L12/00; (IPC1-7): G11C16/04; H01L27/115

WO2000075994A1

2000-12-14

US5455790A	1995-10-03
US5912842A	1999-06-15
EP0741415A1	1996-11-06

PATENT ABSTRACTS OF JAPAN vol. 2000, no. 04 31 August 2000 (2000-08-31)

View/Download PDF      PDF Help

Previous Patent: POLICY CO-ORDINATION IN A COMMUNICATIONS NETWORK

Next Patent: CONTROL OF SERVICES IN MOBILE PACKET DATA NETWORKS