TECHNICAL FIELD

The various aspects and embodiments thereof relate to a semiconductor device having a junction between a first region having a first conductivity type extending from the top surface and a second region having a second conductivity type opposite to the first conductivity type extending from the top surface and adjacent to the first bulk area.

BACKGROUND

An ideal diode has not voltage over it in forward mode, irrespective from the current through it and transmits no current in backward mode, irrespective of the voltage applied over it. However, virtually every semiconductor diode has a reverse breakdown voltage. The breakdown voltage depends on various parameters, like the amount of defects in the current path and the doping level. At the surface, the breakdown electrical field is usually significantly lower than in the bulk.

A reason for this is that at a boundary of the semiconductor bulk and in particular a boundary between a monocrystalline semiconductor material and an isolation like an oxide of the semiconductor material, many defects are present, like dangling bonds and/or other defects. Defects can be a source of degradation, i.e., increase of leakage current and reduction of breakdown voltage, when the boundary is exposed to electrical stress or radiation. From that perspective, charge carrier transport at the

semiconductor surface is not preferred. Yet, in some applications, charge carrier transport along the surface is preferred for specific reasons, for example in sensor applications. SUMMARY

It is preferred to provide a semiconductor having improved breakdown characteristics at the surface.

A first aspect provides a semiconductor device. The device comprises a semiconductor bulk having a top surface, a first bulk region having a first conductivity type extending from the top surface and a second bulk region having a second conductivity type opposite to the first

conductivity type extending from the top surface and adjacent to the first bulk area. The device further comprises a first terminal for providing an electrical contact to the first bulk region, a second terminal for providing an electrical contact to the second bulk region which second terminal is laterally spaced apart from the first terminal. On the top surface, a top layer is provided, the top layer comprising at least 50% and preferably at least 99% of a group III or group V material, the layer covering at least a boundary between the first bulk region and the second bulk region.

Firstly, the atoms of the top layer may align with silicon atoms at the top of the crystalline semiconductor bulk. This passivates bonds of the semiconductor substrate at the top, which reduces defects and with that, this increases the breakdown field strength.

Second, the top layer may function as a resistive voltage divider over the junction. In this way, high field peaks are smoothened out throughout the bulk, near the junction and at the surface. Also this effect increases the breakdown field strength.

These two effects of the first aspect result in an increased critical field at the surface of the bulk of the device, compared to providing a passivation top layer, for example predominantly comprising an oxide of the bulk material like S1O2. This allows for high voltage devices to be designed with smaller footprint, while able to withstand the same voltage. Otherwise, with the same footprint, devices may be designed and manufactured that are able to withstand a higher reverse voltage. This means that devices according to this aspect are well suited for high voltage electronics.

However, other fields or application are not excluded.

In an embodiment, the second sub-region comprises third sub- regions having the same conductivity type as the second of the first bulk region and the second bulk region. The third sub-regions act as guard rings for evening out any peaks in electrical field strength.

In another embodiment, a first of the first bulk region and the second bulk region comprises a first sub-region having a first doping level and a second sub-region having a second doping level, the first sub-region has a higher doping level than the second sub-region; and the second sub- region is provided between the first sub-region and a second of the first bulk region and the second bulk region. This embodiment provides a possibility for a depleted drift region and non-depleted contact regions.

In another embodiment, after deposition of the top layer, the top layer has a sheet resistance of at least 1 ΜΩ/sq with a voltage of zero volts applied between the first terminal and the second terminal. This allows the top layer to function as a voltage divider which, in turn, evens out peaks in the electrical field below the top layer and at junctions in particular.

Manufacturing of such layer is predominantly a technology issue. The surface of the bulk should be well treated and the top layer material should be deposited at a temperature that is not too high. The latter point is important, as a higher temperature may result in atoms of the top layer diffusing in the semiconductor bulk layer - which is not preferred.

In a further embodiment, the semiconductor device comprises a dielectric layer(-stack) provided on top of the top layer. In some applications, the layers on top of the top layer may be designed to block as much

radiation as possible. In other applications, preferably, the dielectric layer has a transparency of at least 10% for electromagnetic waves having a wavelength between 0.01 nanometres and 2000 nanometres and preferably between 100 nanometres and 400 nanometres. This embodiment allows the semiconductor device to be used as a detector of radiation. Alternatively or additionally, the dielectric layer has a transparency of at least 10% for particles, including, but not limited to alpha particles, electrons, positrons, neutrons and protons.

A second aspect provides a method of manufacturing a semiconductor device according to any of the preceding claims. The method comprises providing a semiconductor bulk having a top surface, introducing donor atoms in the semiconductor bulk via a first area of the top surface, introducing acceptor atoms in the semiconductor bulk via a second area of the top surface, the second area being adjacent to the first area. The method further comprises providing a top layer on the top surface, the top layer comprising at least 50% and preferably 99% of a group III or group V material, the layer covering at least a boundary between the first bulk region and the second bulk region, providing a first terminal for providing an electrical contact to the first bulk region and providing a second terminal for providing an electrical contact to the second bulk region which second terminal is laterally spaced apart from the first terminal. The voltage along the top layer can be modified by placing and biasing electrodes at different positions along the top layer.

BRIEF DESCRIPTION OF THE DRAWINGS

The various aspects and embodiments thereof will now be discussed in further detail in conjunction with drawings. In the drawings:

Figure 1 A: shows a symbolic representation of a diode;

Figure 1 B: shows a high level implementation of a practical surface based diode;

Figure 2: shows a detailed view of a surface based diode;

Figure 3: shows another detailed view of a surface based diode; Figure 4: shows a further detailed view of a surface based diode;

Figure 5: shows another implementation of the surface based diode;

Figure 6: shows a surface based diode with an isolation layer on top of it;

Figure 7 A: shows a first topology of a surface based diode;

Figure 7 B: shows a second topology of a surface based diode;

Figure 7 C: shows a third topology of a surface based diode; and

Figure 8: shows another embodiment of a diode having a junction boundary ending at a top surface of a semiconductor bulk.

DETAILED DESCRIPTION

Figure 1 A shows a symbol for a diode. The diode comprises an anode 110 and a cathode 120. Figure 1 B shows the diode 100 having a practical implementation, the diode 100 comprising semiconductor bulk 200 with the anode 110 and the cathode 120 provide at the top of the

semiconductor bulk 200.

Figure 2 shows the diode 100 in further detail. The diode 100 comprises a semiconductor bulk 200 having a first bulk region 220 having a first conductivity type and a second bulk region 230 having a second conductivity type opposite to the first conductivity type. The bulk preferably comprises a group-IV element material, comprising silicon, germanium, sihcon germanium, germanium tin, carbon or silicon carbide, another group- IV element or a combination thereof. Alternatively or additionally, the semiconductor bulk 200 comprises a mix of group-Ill and group-V elements, of each group in substantially equal amounts. In such embodiments, the semiconductor bulk 200 may comprise boron, aluminium, gallium and/or indium as one part of the mix and nitride, phosphorus, arsenic and/or antimony as another part of the mix.

The paper "PureGaB p+n Ge diodes grown in large windows to Si with a sub-300 nm transition region", by A.Sammak, W. B. de Boer, L. Qi and L. K. Nanver, as published in J. Solid-State Electronics, vol. 74, no. 1, pp. 126-133, aug. 2012, discloses deposition of a pure gallium plus pure boron layer as a type III material on n-type germanium as a type IV semiconductor.

Nanver SBMicro2012 proc: discusses experiments showing the use of Ga depositions on Si and Ge to form ideal p+n junctions on either Si or Ge single crystals, (ref: L. K. Nanver, A. Sammak, V. Mohammadi, K. R. C. Mok, L. Qi, A. Sakic, N. Golshani, J. Derakhshandeh, T. M. L. Scholtes, and W. D. de Boer, "Pure dopant deposition of B and Ga for ultrashallow junctions in Si-based devices," ECS Trans., vol. 49, no. 1, pp. 25-33, Sep. 2012).

The paper "N-type induced junction black Si photo-diode for UV detection," by M.A. Juntunen, J. Heinonen, H.S. Laine, V. Vahanissi, P. Repo, A. Vaskuri, and H. Savin, as published in Proc. of SPIE Vol. 10249, 2017, 1024901 pp.1-7, discloses the use of an aluminium containing material (AI2O3) as a means of inducing a p ⁺ n junction on n-type silicon.

With respect to group V elements deposited on n-type silicon, the CVD deposition of pure arsenic or pure phosphorus is shown to lower the Schottky barrier height of n-type Schottky diodes in "Comparison of

Selective Deposition Techniques for Fabricating p ⁺ n Ultrashallow Silicon Diodes," by X. Liu, S.D. Thammaiah, T.L.M. Scholtes, and L.K. Nanver in Proceedings ICT-Open 2016, pp. 25-19, and "Metal/silicon Schottky barrier lowering by RTCVD interface passivation," by Q.W. Ren, W.D. van Noort, L.K. Nanver and J.W. Slotboom in Electrochemical Society Proceedings Volume 2000-9, pp. 161-166. Preferably, the first conductivity type is p-type. In addition to the basic material of the semiconductor bulk the first bulk region 220 may comprise acceptor atoms and has an acceptor atom dopant level between zero and 10 ²¹ per cubic centimetre. The acceptor atoms are preferably group - III elements including, but not limited to boron, aluminium, galhum and indium, other or a combination thereof.

Preferably, the second conductivity type is n-type. In addition to the basic material of the semiconductor bulk, the first bulk region 230 may comprise donor atoms and has a donor atom dopant level between zero and 10 ²¹ per cubic centimetre. The dopant atoms are preferably group -V elements including, but not limited to phosphorus, arsenic, antimony other or a combination thereof.

The dopant atoms may be introduced in the semiconductor bulk 200 by means of implantation, diffusion, deposition of group-IV material with the dopant atoms, other, or a combination thereof. In Figure 2, a dashed line is provided indicating a boundary between the first bulk region 220 and the second bulk region 230. In practice this will in most cases not be a strict boundary, but more or a boundary region, albeit a very narrow region.

At the top surface of the semiconductor bulk, a top layer 210 is deposited. The top layer 210 preferably comprises at least 50% boron. More preferably, the top layer 210 comprises at least 75%, 80%, 90%, 95%, 99%, 99,99% and 99,99999% boron. Alternatively or additionally, the top layer comprises another group-Ill material with the same purity level, including, but not limited to aluminium, gallium and indium. In an alternative embodiment, the top layer 210 comprises a group -V element, including, but not limited to phosphorous, arsenic, antimony, other, or a combination thereof.

The top layer 210 preferably has a sheet resistance of at least 1 ΜΩ/sq and more preferably at least 10 ΜΩ/sq, at least 10 ² ΜΩ/sq, at least 1 θΩ/sq, or at least 1 ΤΩ/sq. In the embodiments discussed below, the top layer 210 will be discussed as predominantly comprising boron, but this does not exclude other options. With such sheet resistance, the top layer 210 functions as a voltage divider, providing a more constant field strength along the top surface of the semiconductor bulk 200 compared to a case when the top layer 210 was not present.

At both ends of the top layer, contact pads are provided. The anode contact pad 112 is provided on the p-type region and the cathode contact pad 120 is provided at the n-type region. The contact pads

preferably comprise a metal, including but not limited to tungsten, copper or aluminium, other, or a combination thereof. The contact pads preferably provide an ohmic contact to the semiconductor bulk 200. To achieve such ohmic contact, a silicide material (not shown) may be provided between the contact pads and the semiconductor bulk 200.

With the boron top layer provided on the top surface of the semiconductor bulk 200, a layer 212 with holes as excess charge carriers is created at the surface of the semiconductor bulk 200. The hole layer preferably has a sheet resistance of at least 1 kΩ/sq, preferably at least 10 kQ/sq, at least 30 k /sq and more preferred at least 1 ΜΩ/sq. The hole layer 212 will be depleted upon reverse biasing and the sheet resistance could then increase to the θΩ/sq range. If the top layer predominantly comprises a type-V material, the surface layer 212 comprises electrons as excess charge carriers. The top layer 210 and hole layer 212 provide a conductive path between the anode and the cathode. But due to the high resistance, the current flowing through the top layer is very small. To further reduce leakage current, an optional layer contact 132 may be provided for picking up charge flowing along the surface of the bulk, through the top layer 210 ancl/or the surface layer 212. The adjacent p-type material and n-type material result in a depletion region 204, indicated by the dotted lines. Figure 2 shows the depletion region 204 with the top layer 210 predominantly comprising boron.

Figure 3 shows a practical embodiment of the semiconductor device according to the first aspect. The diode 100 comprises a

semiconductor bulk 200 comprising one or more group-IV materials, preferably silicon, germanium, tin, or carbon, like silicon germanium or silicon carbide. In this embodiment, the semiconductor bulk 200 is doped with donor atoms at a doping level between 0 and 10 ¹⁹ atoms per cubic centimetre.

Within the semiconductor bulk 200, a p-type doping region 240 is provided. The doping level of the p-type doping region 240 is between 0 and 10 ²¹ atoms per cubic centimetre. The p-type doping region 240 is preferably between 0.1 micrometres and 10 micrometres deep, depending on required characteristics of the diode 100. Preferably, the doping level of the n-type doping region 240 is higher than the doping level of the semiconductor bulk 200, but this is not necessary. With the p-type doping region 240 being provided in the n-type doped semiconductor bulk 200, a p-n junction is created at the boundary of the p-type doping region 240.

At a distance from the p-type doping region 240, an n-type doping region 250 is provided. The distance between the p-type doping region 240 and the n-type doping region 250 depends on what voltage the diode 100 is to withstand. With a theoretical breakdown field of about 3 10 ⁵ Volt per centimetre at a doping level of 3x 10 ¹⁴ atoms per cubic centimetre, the distance between the two regions should be at least 30 micrometres to withstand a reverse voltage of 600 Volt. This distance should increase with decreasing doping level of the semiconductor bulk 200. However, as the practical breakdown field is usually significantly lower than the theoretical breakdown field, the diode 100 is preferably designed with a larger distance between the p-type doping region 240 and the n-type doping region 250.

The doping level of the n-type doping region 250 is between 0 and 10 ²¹ atoms per cubic centimetre. The n-type doping region 250 is preferably between 0.1 micrometres and 10 micrometres deep, depending on required characteristics of the diode 100. Preferably, the doping level of the n-type doping region 250 is higher than the doping level of the semiconductor bulk 200, but this is not necessary. The semiconductor bulk 200 having an n-type conductivity type and the n-type doping region 250 form a region having an n-type conductivity type, with the n-type doping region 250 forming a first n-type sub-region and the semiconductor bulk 200 forming a second n-type sub -region.

Figure 3 also shows the top layer 210 discussed above. In this embodiment, the top layer 210 predominantly comprises boron. This results in a layer with holes as excess charge carriers being located below the top layer, at the surface of the semiconductor bulk 200. As with the embodiment discussed in conjunction with Figure 2, the top layer 210 is contacted by an anode contact pad 112 and a cathode contact pas 122.

In steady state, without a voltage applied between the anode 110 and the cathode 120, a depletion region 204 extends from the p-type doping region 240 to the n-type doping region 250. Between these regions, the bulk region is fully depleted in this embodiment, wherein the doping level of the p-type doping region 240 is one, two or more orders of magnitude higher than the doping level of the bulk. If the doping levels are of the same order, the depletion region 204 will not extend as far into the n-type region.

The depletion layer is at the top bound by a surface hole layer 212. The surface hole layer 212 is located at the surface of the

semiconductor bulk 200 and has holes as excess carriers by virtue of the boron layer provided on the surface of the semiconductor bulk 200. As discussed, the top layer 210 that induces hole layer 212, functions as a voltage divider, providing a more constant field strength along the top surface of the semiconductor bulk 200 compared to a case when the top layer 210 was not present. However, in some cases, this measure may not be sufficient for reducing local peaks of electrical field strength at the surface of the semiconductor bulk 200 in order to increase breakdown voltage of the diode 100. To that purpose, intermediate p-type pockets are provided in the second n-type sub-region, the semiconductor bulk 200 between the p-type doping region 240 and the n-type doping region 250. This is depicted by Figure 4, which shows p-type pockets 410 extending from the top surface of the semiconductor bulk 200 between the p-type doping region 240 and the n-type doping region 250. For the sake of clarity, the surface hole layer 212 is also present in the device depicted by Figure 4, but it has been omitted for the sake for clarity.

Figure 5 shows another implementation of the diode 100. Most elements are the same as the implementation shown by Figure 3, which elements will not be specifically mentioned again. Different than depicted by Figure 3, the top layer 210 does not extend to the n-type doping region 250.

Furthermore, a layer contact 132 is provided on the top layer 210, at or nearby a boundary of the top layer 210 for separate biasing and picking up current from the top layer 210. Whereas the current through the top layer 210 will in most cases be relatively low or even negligible by virtue of the high sheet resistance of the top layer, further reduction of the reverse current has positive effects and is even preferred in certain embodiments.

In particular if the diode 100 is used as a sensor for quantitative measurement of particular values, influence of the current through the top layer is preferably reduced by means of the layer contact 132.

Figure 5 does show the top layer 210 in contact with the p-type doping region 240 and not in contact with the n-type doping region 250. Alternatively, the top layer 210 is in contact with the n-type doping region 250 and not in contact with the p-type doping region 240. In yet another alternative, the top layer 210 is not in contact with either one of the n-type doping region 250 and the p-type doping region 240.

In particular in the latter embodiment, other and optionally more electrodes are provided in contact with the top layer 210. Depending on the voltage applied to the extra electrodes, this can allow a part of the voltage drop over diode 100 to fall over an insulating region. The electrode also provides a sink for any charge that may disturb any measurements. In such embodiment, preferably contacts are provided at the top layer 210 at opposite ends of the top layer 210.

In addition to or as an alternative, other and/or further contacts may be provided on the top layer 210 for controlling and/or adjusting the electrical field under the top layer 210 and at any junction in particular. Figure 6 shows the diode 100 with an isolation layer 510 provided on top of the semiconductor bulk 200 and the top layer 210. In the isolation layer, contact holes are provided, which are filled with metal plugs for contacting the p-type doping region 240 and the n-type doping region 250. As discussed above, the metal plugs may comprise aluminium, tungsten, copper, other, or a combination thereof. Prior to patterning of the holes, for example by means of etching and after deposition of the material for the isolation layer 510, the isolating material may be polished.

The diode 100 may be used as a sensor for detecting radiation and measuring a radiation level. Such radiation may be particle radiation, including, but not limited to electron, positron, proton, neutron and/or alpha particle radiation. Alternatively or additionally, the diode 100 is suitable for detecting and measuring level of electromagnetic radiation. Preferably, the diode 100 is suitable for detecting and measuring radiation having wavelengths between 0.01 nanometres and 2000 nanometres. Measurement and detection of electromagnetic radiation having a wavelength between 10 nanometres and 400 nanometres is particularly preferred. Such

electromagnetic radiation covers the extreme ultraviolet, deep ultraviolet and ultraviolet spectrum. This type of radiation is used in medical imaging and wafersteppers used for manufacturing of integrated circuits, which makes the diode 100 suitable for use in such apparatus.

With the diode 100 being preferred to be used for detecting and measuring various types of radiation, including a wide range of the electromagnetic spectrum, it is preferred the isolation layer 510 is at least somewhat transparent to the radiation to be detected and/or of which the level is to be measured. Preferably, the isolation layer 510 is at least 20% transparent to the relevant radiation, in case applicable to the relevant radiation in the relevant part of the spectrum. A transparency of at least 50%, 60%, 75%, 80%, 90% or 99% is preferred as well. To this purpose, the isolation layer may comprise S1O2, SiN _x , AI2O3, AIN, Hf02, oxynitrides, other, or a combination thereof. Depending on the radiation type and, in case applicable, the part of the spectrum for which the diode 100 is intended to be used as a sensor, a particular material or mix of materials may be selected.

Figure 7 A, Figure 7 B and Figure 7 B show possible topologies for the diode 100 to be used as a radiation detector. Figure 7 A shows a rectangular and in particular square top layer 210 between two elongated, preferably rectangular contacts, providing an anode 110 and a cathode 120. Figure 7 B shows the anode 110 and the cathode 120 having a comb structure, with the teeth of both comb structures being interleaved. The top layer 210 is provided between the teeth of the combs. Figure 7 C shows a small cathode 120 within a circular anode 110. The cathode 120 is

preferably shaped as a circle as well. Also in this topology, the top layer 210 is provided between the anode 110 and the cathode 120. In an alternative embodiment, the anode 110 is provided at the centre and the cathode is provided at the edge, in the circle. Thus far, planar devices are presented having a junction with a boundary having a directional component substantial perpendicular to the upper surface and/or a junction at the surface. In such embodiment, charge carrier transport takes at least partially place along the upper surface.

Other diodes and other semiconductor devices (triacs and other switching devices) are known that have a junction with a directional component perpendicular to the surface -so having a junction at the surface -, but not at the upper surface.

An embodiment is shown by Figure 8. Figure 8 shows a diode having an anode contact 112 at the top and a cathode contact 122 at the bottom. The diode 100 comprises a semiconductor bulk having a first bulk region 220 having a first conductivity type, p-type in this embodiment, and a second bulk region 230 having a second conductivity type opposite to the first conductivity type - n-type in this embodiment.

The edges of the bulk are bevelled. The bevel structure may be achieved by mechanical means, physical etching, chemical etching - wet and/or dry, other processes or a combination thereof. The majority of charge carrier transport takes place in the bulk, but a part will flow along the bevelled edges. Hence, defects at the bevelled top surface of the diode 100 as depicted by Figure 8 may seriously decrease the breakdown voltage of the diode 100. This is also the case if the bevelled top surface is covered with an insulating passivation layer.

Such passivation layers may include charge, the amount of which may depend on an amount of stress applied. Furthermore, defects may exist, remain to exist or occur at the interface with the passivation. Application of the top layer 210 as discussed above on the surface on which a junction boundary 202 ends may reduce the amount of defects that are detrimental to the (reverse) breakdown voltage of the diode 100 as depicted by Figure 8.

The diode 100 according to the various embodiments can be manufactured using a combination of various process technologies. Doped or undoped monocrystalline semiconductor wafers are commercially available, with various material compositions, including sihcon, sihcon germanium, silicon carbide, germanium and a wide range of III-V mixtures, including gallium arsenide. The - preferably - higher doped p-type and n-type regions may be selectively implanted. Otherwise, the higher doped p-type and n- type regions are created by etching of blanket deposited layers. The areas where the implants are not to be provided may be masked by means of a photolithographic process and covered by photoresist, another layer blocking atoms to be implanted, or a combination thereof. Alternatively or

additionally to implant, a diffusion process may be used, with a gaseous, liquid or solid source of dopant atoms. Also an implant step may be followed by a diffusion and/or annealing step at increased temperatures. This step is executed twice, once for acceptor atoms and once for donor atoms.

Preferably after, but optionally before the doping step, the top layer is deposited. Preferably, the top layer is deposited at a temperature at which the atoms of the top layer material do not diffuse into the bulk material - or only diffuse to a very low extent. Studies have shown that when using boron as a material for the top layer, the temperature is preferably kept around 400 degrees Centigrade or lower. At such

temperatures, deposited boron atoms in one or more first atomic layer or layers will align with silicon atoms at the top of the crystalline

semiconductor bulk and they will not diffuse in the bulk. Further deposited boron will grow as an amorphous layer, having a high sheet resistance. When depositing other materials for the top layer, other temperature requirements may apply. Further information is provided in an article

"Conductance Along the Interface Formed by 400 °C Pure Boron Deposition on Silicon" by Lin Qi and Lis K. Nanver, IEEE ELECTRON DEVICE

LETTERS, VOL. 36, NO. 2, FEBRUARY 2015, pages 102 to 104 and in "Robust UV VUV/EUV PureB Photodiode Detector Technology With High CMOS Compatibility" by Lis K. Nanver et al., IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL. 20, NO. 6, NOVEMBER/DECEMBER 2014, page 3801711 .

The top layer thus created may optionally be patterned. As the sheet resistance is preferably very high - in the order of 1 GQ - presence of the boron layer at locations where it is not required mostly does not raise any issues. In case this would cause any problems, patterning is preferred. After deposition of the top layer, the isolation layer 510 and the contact pads are created. In one embodiment, metal or another highly conductive material is deposited and patterned. This is followed by deposition of the isolation layer 510, formation of contact holes in the isolation layer 510 and filling the contact holes with metal. Alternatively, the metal deposition step prior to deposition of the isolation layer 510 is omitted. Optionally, a silicide may be formed at the locations where the anode and cathode terminals are provided.

In an alternative method, metal is patterned while deposited on the top layer 212. This allows metal to be patterned before deposition of the isolation layer 510. Additionally or alternatively, a lift-off process can be used to deposit metal only on contacting regions. In another alternative or additional option, the metal may be removed from other regions by wet- etching to the top layer, for example as proposed by A. Sakic, et al., "High- efficiency silicon photodiode detector for sub-keV electron microscopy," IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL 59, NO. 10, OCTOBER 2012, pages 2707 to 2714.

In the description above, it will be understood that when an element such as layer, region or substrate is referred to as being "on" or

"onto" another element, the element is either directly on the other element, or intervening elements may also be present.

Furthermore, the invention may also be embodied with less components than provided in the embodiments described here, wherein one component carries out multiple functions. Just as well may the invention be embodied using more elements than depicted in the Figures, wherein functions carried out by one component in the embodiment provided are distributed over multiple components.

It is to be noted that the figures are only schematic

representations of embodiments of the invention that are given by way of non-limiting examples. For the purpose of clarity and a concise description, features are described herein as part of the same or separate embodiments, however, it will be appreciated that the scope of the invention may include embodiments having combinations of all or some of the features described. The word 'comprising' does not exclude the presence of other features or steps than those listed in a claim. Furthermore, the words One', 'a' and 'an' shall not be construed as hmited to Only one', but instead are used to mean 'at least one', and do not exclude a plurality.

A person skilled in the art will readily appreciate that various parameters and values thereof disclosed in the description may be modified and that various embodiments disclosed and/or claimed may be combined without departing from the scope of the invention.

It is stipulated that the reference signs in the claims do not limit the scope of the claims, but are merely inserted to enhance the legibility of the claims.