Title:
SEMICONDUCTOR DEVICE HAVING SGT AND MANUFACTURING METHOD THEREFOR
Document Type and Number:
WIPO Patent Application WO/2014/199481
Kind Code:
A1
Abstract:
A P+ region (13bb) and an N+ region (12bb) that serve as drains for SGTs at the tops of silicon columns (P1, P2) formed on an i-layer substrate (1) are connected to a power-supply-wiring metal layer (Vdd) and a ground-wiring metal layer (Vss) throughout low-resistance nickel-silicide layers (14c, 14h) that contact the P+ region (13bb) and the N+ region (12bb) and are formed around the silicon columns (P1, P2). The bottom edges of the power-supply-wiring metal layer (Vdd) and the ground-wiring metal layer (Vss) are located at the heights of the surfaces of HfO layers (9ba, 9bb) near interfaces between channels and the P+ and N+ regions (13bb and 12bb).
Inventors:
MASUOKA FUJIO (JP)
HARADA NOZOMU (JP)
NAKAMURA HIROKI (JP)
HARADA NOZOMU (JP)
NAKAMURA HIROKI (JP)
Application Number:
PCT/JP2013/066320
Publication Date:
December 18, 2014
Filing Date:
June 13, 2013
Export Citation:
Assignee:
UNISANTIS ELECT SINGAPORE PTE (SG)
MASUOKA FUJIO (JP)
HARADA NOZOMU (JP)
NAKAMURA HIROKI (JP)
MASUOKA FUJIO (JP)
HARADA NOZOMU (JP)
NAKAMURA HIROKI (JP)
International Classes:
H01L21/336; H01L21/8238; H01L27/092; H01L29/78
Domestic Patent References:
| WO2009075031A1 | 2009-06-18 |
Foreign References:
| JP2007123415A | 2007-05-17 | |||
| JP2009509359A | 2009-03-05 | |||
| JP2011243908A | 2011-12-01 | |||
| JP2012004244A | 2012-01-05 | |||
| JPH01232755A | 1989-09-18 | |||
| JP2011108702A | 2011-06-02 |
Attorney, Agent or Firm:
KIMURA MITSURU (JP)
Mitsuru Kimura (JP)
Mitsuru Kimura (JP)
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