Title:
SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING SYSTEM
Document Type and Number:
WIPO Patent Application WO/2010/029830
Kind Code:
A1
Abstract:
Provided is a user-friendly information processing system which is capable of maintaining latency constant and ensuring the expandability of a memory capacity at high speed and at low cost. The information processing system including an information processing device, a volatile memory, and a nonvolatile memory is configured. The information processing device, the volatile memory, and the nonvolatile memory are connected in series to reduce the number of connection signals, thereby promoting speeding-up while maintaining the expandability of a memory capacity. The information processing device measures latency and performs a correction operation on the latency, thereby maintaining latency constant. The information processing device performs an error correction to improve the reliability when transferring data in the nonvolatile memory to the volatile memory. The information processing system composed of the plurality of chips is configured as an information processing system/module in which the respective chips are arranged and stacked one upon another, and are connected by means of a ball grid array (BGA) and/or a chip-to-chip wiring technique.
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Inventors:
MIURA SEIJI (JP)
Application Number:
PCT/JP2009/064146
Publication Date:
March 18, 2010
Filing Date:
August 10, 2009
Export Citation:
Assignee:
HITACHI LTD (JP)
MIURA SEIJI (JP)
MIURA SEIJI (JP)
International Classes:
G06F12/06; G06F12/00; G06F13/16
Foreign References:
| US20070005922A1 | 2007-01-04 | |||
| JP2008041089A | 2008-02-21 | |||
| JP2007310430A | 2007-11-29 | |||
| JPH06266615A | 1994-09-22 | |||
| JP2002530731A | 2002-09-17 | |||
| JP2006293969A | 2006-10-26 | |||
| US20060095671A1 | 2006-05-04 | |||
| US20080115137A1 | 2008-05-15 | |||
| JP2008276351A | 2008-11-13 |
Attorney, Agent or Firm:
TSUTSUI, YAMATO (JP)
Tsutsui Daiwa (JP)
Tsutsui Daiwa (JP)
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