SEMICONDUCTOR DEVICE AND ITS FABRICATION METHOD

WIPO Patent Application WO/2007/043116

A1

[PROBLEMS] To provide a semiconductor device and its fabrication method that can obtain an electrically reliable connection between a metal interconnection and a conductive plug. [MEANS FOR SOLVING PROBLEMS] A semiconductor device fabrication method comprises steps of forming a first insulating film (45) on a silicon substrate (30), forming a capacitor (Q) on the first insulating film (45), forming a second insulating film (55) covering the capacitor (Q), forming a metal interconnection (65) on the second insulating film (55), forming a first capacitor protection insulating film (66) covering the metal interconnection (65) and the second insulating film (55), forming an insulative sidewall (67a) on a side of the metal interconnection (65), forming a third insulating film (68) on the insulative sidewall (67a), forming a hole (74a) by etching the third insulating film (68) under the condition that the etching speed of the insulative sidewall (67a) is slower than that of the third insulating film (68), and forming a conductive plug (77) in the hole (74a).

KIKUCHI, Hideaki (1-1 Kamikodanaka 4-chome, Nakahara-ku, Kawasaki-sh, Kanagawa 88, 2118588, JP)
菊池 秀明 (〒88 神奈川県川崎市中原区上小田中４丁目１番１号 富士通株式会社内 Kanagawa, 2118588, JP)

JP2005/018173

April 19, 2007

September 30, 2005

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FUJITSU LIMITED (1-1 Kamikodanaka 4 -chome, Nakahara-ku Kawasaki-sh, Kanagawa 88, 2118588, JP)
富士通株式会社 (〒88 神奈川県川崎市中原区上小田中４丁目１番１号 Kanagawa, 2118588, JP)
KIKUCHI, Hideaki (1-1 Kamikodanaka 4-chome, Nakahara-ku, Kawasaki-sh, Kanagawa 88, 2118588, JP)

H01L21/8246; H01L27/105

OKAMOTO, Keizo (OKAMOTO PATENT OFFICE Yamanishi Bldg, 4F 11-7, Nihonbashi Ningyo-cho 3-chome, Chuo-k, Tokyo 13, 1030013, JP)

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