SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SAME

WIPO Patent Application WO/2015/045089

A1

In a semiconductor device (SP1) according to one embodiment, between a substrate layer (2CR) of a wiring board (2) and a semiconductor chip (3), a solder resist film (first insulating layer (SR1)) which adheres closely to the substrate layer, and a resin body (second insulating layer (4)) which adheres closely to the solder resist film and the semiconductor chip, are stacked. Furthermore, the linear expansion coefficient of the solder resist film is greater than or equal to the linear expansion coefficient of the substrate layer, the linear expansion coefficient of the solder resist film is less than or equal to the linear expansion coefficient of the resin body, and the linear expansion coefficient of the substrate layer is less than the linear expansion coefficient of the resin body. According to the configuration, it is possible to suppress damage to the semiconductor device caused by a temperature cycle load, and to improve reliability.

JP2009086374	PHOTOSENSITIVE COMPOSITION, PHOTOSENSITIVE FILM, PHOTOSENSITIVE LAMINATE, METHOD OF FORMING PERMANENT PATTERN, AND PRINTED CIRCUIT BOARD
JP2013157592	FLEXIBLE CIRCUIT BOARD FOR MOUNTING LIGHT EMITTING ELEMENT
JP5830925	Manufacturing method of printed wiring board

SHIMOTE YOSHIKAZU (JP)
BABA SHINJI (JP)
IWASAKI TOSHIHIRO (JP)
NAKAGAWA KAZUYUKI (JP)

PCT/JP2013/076227

April 02, 2015

September 27, 2013

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RENESAS ELECTRONICS CORP (JP)

H05K3/28; H01L23/12

JP2007227708A	2007-09-06
JP2009064812A	2009-03-26
JP2007266136A	2007-10-11
JP2013012648A	2013-01-17
JP2000077471A	2000-03-14
JP2007266136A	2007-10-11

See also references of EP 3051583A4

TSUTSUI, Yamato et al. (JP)
Tsutsui Daiwa (JP)

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