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Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE MANUFACTURING METHOD
Document Type and Number:
WIPO Patent Application WO/2007/026677
Kind Code:
A1
Abstract:
There has been a problem of element characteristic fluctuation due to the change of the composition of an obtaining silicide being dependent on the gate length, at the time of forming a full silicide gate electrode by sintering a metal/poly-Si structure. The element characteristics also fluctuate due to nonuniformity of the composition among the obtaining silicide elements. After forming a full silicide having a metal-rich composition, a Si layer is deposited in addition and sintered. Thus, the metal in the metal rich silicide is diffused and converted into silicide in the Si layer, and the entire composition is converted into a full silicide having a smaller metal composition ratio.

Inventors:
HASE TAKASHI (JP)
Application Number:
PCT/JP2006/316945
Publication Date:
March 08, 2007
Filing Date:
August 29, 2006
Export Citation:
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Assignee:
NEC CORP (JP)
HASE TAKASHI (JP)
International Classes:
H01L29/78; H01L21/28; H01L21/336; H01L21/8238; H01L27/092; H01L29/423; H01L29/49
Foreign References:
JP2001168059A2001-06-22
JP2005085949A2005-03-31
JP2005191545A2005-07-14
JP2002299282A2002-10-11
JPH10125909A1998-05-15
JPH04299825A1992-10-23
Other References:
KENSUKE TAKAHASHI ET AL.: "Dual Workfunction Ni-Silicide/HfSiON Gate stacks by Phase-Controlled Full-Silicidation (PC-FUSI) Technique for 45nm-node LSTP and LOP Devices", IEDM' 04, 2004, pages 91 - 94, XP010788704
KITTL J.A. ET AL.: "Scalability of Ni FUSI gate processes: phase and Vt control to 30nm gate lengths", 2005 SYMPOSIUM ON VLSI TECHNOLOGY DIGEST OF TECHNICAL PAPERS, 2005, pages 72 - 73, XP010818177
Attorney, Agent or Firm:
MIYAZAKI, Teruo et al. (16th Kowa Bldg., 9-20, Akasaka 1-chom, Minato-ku Tokyo 52, JP)
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