Title:
SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2017/002268
Kind Code:
A1
Abstract:
In the semiconductor device manufacturing method according to an embodiment of the present invention, a suspension lead is connected to a chip mounting section on which a semiconductor chip is mounted. The suspension lead includes: a first tab connection section connected to the chip mounting section and extending in a first direction; a first branch section provided on the chip mounting section at a position higher than the first tab connection section, and branching in a plurality of directions intersecting the first direction; and a plurality of first exposed-surface connection sections each provided at a position higher than the first branch section and each having one end connected to a portion exposed from a sealed body. The suspension lead further includes a first offset section connected to the first tab connection section and the first branch section, and a plurality of second offset sections each having one end connected to the first branch section and the other end connected to each of the plurality of first exposed-surface connection sections.
Inventors:
TAKAHASHI NORIYUKI (JP)
Application Number:
PCT/JP2015/069194
Publication Date:
January 05, 2017
Filing Date:
July 02, 2015
Export Citation:
Assignee:
RENESAS ELECTRONICS CORP (JP)
International Classes:
H01L21/56; H01L23/50; H01L23/28
Foreign References:
| US6075283A | 2000-06-13 | |||
| JPH11340401A | 1999-12-10 | |||
| JPH10163402A | 1998-06-19 | |||
| JP2012109435A | 2012-06-07 | |||
| JPS60120543A | 1985-06-28 | |||
| JPH0377356A | 1991-04-02 | |||
| JPS5958952U | 1984-04-17 | |||
| JPS62123753A | 1987-06-05 |
Attorney, Agent or Firm:
TSUTSUI & ASSOCIATES (JP)
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