Title:
SEMICONDUCTOR DEVICE MANUFACTURING METHOD
Document Type and Number:
WIPO Patent Application WO/2017/086043
Kind Code:
A1
Abstract:
Provided is a semiconductor device manufacturing method with which, when a semiconductor element is fixed in place by being sandwiched between two insulating substrates, the development of positional error or inclination of the semiconductor element can be suppressed.
The semiconductor device manufacturing method comprises: a step A of obtaining a laminate in which a semiconductor element is temporarily adhered, via a first pre-sintering layer, on a first electrode formed on a first insulating substrate; a step B, after step A, of obtaining a semiconductor device precursor by temporarily adhering the semiconductor element, via a second pre-sintering layer disposed on the opposite side from the first pre-sintering layer, on a second electrode formed on a second insulating substrate; and a step C, after step B, of simultaneously heating the first pre-sintering layer and the second pre-sintering layer to bond the semiconductor element to the first electrode and the second electrode.
Inventors:
OKUMURA KEISUKE (JP)
HONDA SATOSHI (JP)
HONDA SATOSHI (JP)
Application Number:
PCT/JP2016/079522
Publication Date:
May 26, 2017
Filing Date:
October 04, 2016
Export Citation:
Assignee:
NITTO DENKO CORP (JP)
International Classes:
H01L35/08; H01L35/34
Foreign References:
| JP2012134410A | 2012-07-12 | |||
| JP2014236106A | 2014-12-15 | |||
| JP2000349350A | 2000-12-15 |
Other References:
See also references of EP 3379588A4
Attorney, Agent or Firm:
UNIUS PATENT ATTORNEYS OFFICE (JP)
Download PDF: