Title:
SEMICONDUCTOR DEVICE MANUFACTURING METHOD
Document Type and Number:
WIPO Patent Application WO/2023/233802
Kind Code:
A1
Abstract:
Provided is a semiconductor device manufacturing method capable of suppressing variance in characteristics attributable to the concentration of carbon in a semiconductor substrate. This semiconductor device manufacturing method: includes a process in which trenches (11) are formed from an upper surface side of a first-conductivity-type semiconductor substrate (10), a process in which an insulated-gate-type electrode structure (6, 7) is embedded in the trenches (11), a process in which second-conductivity-type base regions (3) in contact with the trenches (11) are formed in an upper part of the semiconductor substrate (10), a process in which first-conductivity-type first main electrode regions (4) in contact with the trenches (11) are formed on top of the base regions (3), and a process in which a second-conductivity-type second main electrode region (9) is formed on a lower surface side of the semiconductor substrate (10); and adjusts manufacturing conditions of the base regions (3) and/or the second main electrode region (9) according to the concentration of carbon in the semiconductor substrate (10).
Inventors:
OHI KOTA (JP)
Application Number:
PCT/JP2023/013842
Publication Date:
December 07, 2023
Filing Date:
April 03, 2023
Export Citation:
Assignee:
FUJI ELECTRIC CO LTD (JP)
International Classes:
H01L29/78; H01L21/336; H01L21/8234; H01L27/06; H01L29/739; H01L29/861; H01L29/868
Domestic Patent References:
| WO2021125064A1 | 2021-06-24 | |||
| WO2021125140A1 | 2021-06-24 | |||
| WO2020100997A1 | 2020-05-22 | |||
| WO2016204227A1 | 2016-12-22 | |||
| WO2017047276A1 | 2017-03-23 |
Foreign References:
| JP2006352101A | 2006-12-28 |
Attorney, Agent or Firm:
HIROSE Hajime et al. (JP)
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