Title:
SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2023/243189
Kind Code:
A1
Abstract:
Provided is a semiconductor device manufacturing method by which it is possible to reduce the width of a termination region and suppress the electrical field concentration in the termination region. The semiconductor device manufacturing method is for a semiconductor device that has, in the periphery of the active region, a termination region in which a first semiconductor region of a first electroconductive type has formed on the surface thereof a second semiconductor region that is a plurality of well regions of a second electroconductive type. Said method is characterized by forming the second semiconductor region by injecting impurities of the second electroconductive type using, as a mask for forming the second semiconductor region, a mask with which an interval S(x) is substantially equal to the value defined by S(x)=Smax–(Smax–Smin)·(x/XN)1/2, where x is the distance from the reference window at the outermost periphery and the interval S(x) is the interval between the injection window in a position at the distance x and one injection window on the active region side thereof.
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Inventors:
ONOSE HIDEKATSU (JP)
FURUKAWA TOMOYASU (JP)
FURUKAWA TOMOYASU (JP)
Application Number:
PCT/JP2023/013895
Publication Date:
December 21, 2023
Filing Date:
April 04, 2023
Export Citation:
Assignee:
HITACHI POWER SEMICONDUCTOR DEVICE LTD (JP)
International Classes:
H01L29/06; H01L21/329; H01L21/336; H01L29/12; H01L29/739; H01L29/78; H01L29/861; H01L29/868
Domestic Patent References:
| WO2014057700A1 | 2014-04-17 | |||
| WO2010132144A1 | 2010-11-18 |
Foreign References:
| JP2019102747A | 2019-06-24 | |||
| JP2014175431A | 2014-09-22 |
Attorney, Agent or Firm:
POLAIRE I.P.C. (JP)
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