Cross-reference to Related Applications

[0001] The present application claims the benefit of the Singapore patent application 10201507868P filed on 22 September 2015, the entire contents of which are incorporated herein by reference for all purposes.

Technical Field

[0002] Embodiments relate generally to a semiconductor device, and particularly relate to a semiconductor device having a via.

Background

[0003] As ICs (Integrated Circuits) scale in the deep sub-micron regime, Back-End- Of-Line (BEOL) interconnects pose significant bottleneck and is a major challenge for low power, high speed circuits and system performance. Copper for low resistivity and low-k dielectrics become mandatory for interconnects, and the quest to achieve lower parasitic interconnect lines continues.

[0004] In the case of traditional 2D (Two Dimensional) ICs, the RLC (Resistor, Inductor and Capacitor) components of the long running metal lines contribute significantly towards the delay and power dissipation, while vias in BEOL layers comparatively play a less dominant role. In contemporary 2D ICs, only the resistance of the via is considered for circuit analysis, and the effect of BEOL via capacitance may be ignored as it bears insignificant impact compared to the BEOL interconnects. [0005] For 2.5D (2.5 Dimensional) and 3D (Three Dimensional) IC paradigms, in addition to the traditional BEOL interconnects, TSV - the essential vertical interconnect pose additional challenge. Unlike BEOL vias, TSV capacitance (CT _S V) to silicon substrate or GND (ground) is a major parasitic component impacting the 2.5D as well as 3D circuit behavior.

[0006] Three dimensional integrated circuits provide many advantages. For example, 3D ICs could alleviate some CMOS scaling related performance limitations (e.g. interconnect bottleneck), reduce system size, allow heterogeneous integration (e.g. Memory-Logic integration, III-V to Si integration, etc.), and enable novel systems using high density TSV approach.

[0007] Fig. 1 illustrates a diagram of a 3D integrated circuit 100, in which a plurality of components, circuits, dies and/or interposer may be stacked and integrated, such as sensor, RF (radio frequency), FPGA (field-programmable gate array), memory, board/lnterposer, probes and battery being stacked vertically. The vertical connections among the stacked layers may be achieved through TSVs.

[0008] Fig. 2 shows an exemplary TSV structure 200 in a cross-sectional side view and a cross-sectional top view, along with a lumped RC model of the TSV.

[0009] As shown in Fig. 2, the TSV 220 enable the interconnection between a top die and a bottom die, wherein the top die and the bottom die are bonded through a BCB (Benzocyclobutene) bonding layer 202. At the side of the top die, the TSV 220 extends through a substrate 204 and a pre-metal dielectric (PMD) layer 206 and receives TSV Bias voltage through a contact pad formed on the PMD layer 206. At the side of the bottom die, a landing pad formed in an inter-metal dielectric (IMD) layer 208 connects the body of the TSV 220, and the IMD layer 208 is further connected to a copper layer 210. The copper layer 210 may have a resistivity p of about 1.68e-8 Ω -m, for example. [0010] The TSV 220 includes a conductive fill 222 surrounded by a dielectric layer 224. The dimension of the TSV 220 may include a TSV length L _TSV , a TSV dielectric thickness t _ox , and a TSV diameter (p _T sv- The PMD layer 206 may have a predetermined thickness and permittivity.

[0011] Fig. 2 further shows a cross-sectional top view 230 of the TSV formed in the substrate 204, wherein the substrate 204 is grounded. The substrate 204 may be a p-Si substrate, for example. The TSV includes the conductive fill 222 surrounded by an oxide dielectric layer 224. In operation, a depletion region 226 may be formed outside the oxide dielectric layer 224, which may introduce a TSV depletion capacitance C _dep .

[0012] A corresponding TSV lumped RC model 240 of the TSV 220 is illustrated by G. Katti et al. in "3D stacked ICs using Cu TSVs and die to wafer hybrid collective bonding, IEDM 2009, pp. 357-360". In the lumped RC model 240, the equivalent circuit of the TSV 220, when the TSV 220 is operated in the depletion region, includes TSV resistance RTSV, TSV oxide capacitance C _ox and TSV depletion capacitance C _dep - The effective TSV capacitance C _T sv is given as 1/CTSV and is close to the smaller value of C _ox and C _dep in series. Due to the combination of depletion capacitance (C _d e _p ) in series with the oxide capacitance (C _ox ), the TSV capacitance C _T sv may be reduced.

[0013] The parasitic resistance (RTSV), capacitance (CTSV) and inductance (LTSV) of TSV architectures have also been modeled and characterized, e.g., by G. Katti et al. in "Electrical modeling & characterization of through silicon via (TSV) for 3D ICs, IEEE Trans. Electron Devices, vol. 57, no. 1 , pp. 256-262, Jan. 2010", to establish their impact on 3D circuits and systems. It has been shown that RTSV has minimal impact on the delay of 3D circuits, whereas C _T sv is the most dominant parasitic component impacting the electrical performance of 3D circuits and systems. In order to build high speed circuits and systems, existing high capacitive TSVs become a major bottleneck and the TSV capacitance needs to be further reduced.

[0014] In view of high capacitance TSVs in inhibiting high speed and low power vertical electrical connection for 2.5D and 3D ICs, TSV architectures with low TSV-to- GND capacitance as and low TSV-to-TSV crosstalk are desired for 2.5D and 3D circuits and systems.

Summary

[0015] Various embodiments provide a semiconductor device. The semiconductor device may include a semiconductor substrate including a first semiconductor layer and a second semiconductor layer arranged on the first semiconductor layer, wherein the second semiconductor layer includes one of a doped semiconductor layer or a buried insulator layer. The semiconductor device may further include a via extending through the semiconductor substrate, wherein the via has a first portion extending through the first semiconductor layer and a second portion extending through the second semiconductor layer. The semiconductor device may further include an insulating structure extending through the first semiconductor layer and arranged under the second semiconductor layer, wherein the insulating structure at least partially surrounds the first portion of the via and is separated from the first portion of the via by a portion of the first semiconductor layer.

Brief Description of the Drawings

[0016] In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments are described with reference to the following drawings, in which:

Fig. 1 illustrates a diagram of a 3D integrated circuit.

Fig. 2 shows an exemplary TSV in a cross-sectional side view and a cross- sectional top view, along with a lumped RC model of the TSV.

Fig. 3 shows a semiconductor device according to various embodiments.

Fig. 4 shows a semiconductor device according to various embodiments.

Fig. 5 shows a semiconductor device according to various embodiments.

Fig. 6A shows a TSV-to-GND lumped "RC" model for the semiconductor device of Figs. 4 and 5 according to various embodiments.

Fig. 6B shows a TSV-to-TSV crosstalk "RC" model for the semiconductor device of Figs. 4 and 5 according to various embodiments.

Fig. 7 shows a semiconductor device according to various embodiments.

Fig. 8A shows a TSV-to-GND lumped "RC" model for the semiconductor device of Fig. 7 according to various embodiments.

Fig. 8B shows a TSV-to-TSV crosstalk "RC" model for the semiconductor device of Fig. 7 according to various embodiments.

Fig. 9A depicts the eye diagram simulations at 56 GHz for conventional TSVs.

Fig. 9B depicts the eye diagram simulations at 56 GHz for TSVs according to various embodiments.

Fig. 10 illustrates crosstalk reduction achieved using the horizontal and vertical isolations around TSVs according to various embodiments.

Fig. 11 A depicts the eye diagram simulations at 56 GHz for conventional TSVs.

Fig. 11B depicts the eye diagram simulations at 56 GHz for TSVs according to various embodiments. Fig. 12 shows a flowchart illustrating a method of forming a semiconductor device according to various embodiments.

Fig. 13 shows a flowchart illustrating a fabrication process for forming a semiconductor device according to various embodiments.

Fig. 14 shows a flowchart illustrating a fabrication process for forming a semiconductor device according to various embodiments.

Description

[0017] Various embodiments provide a semiconductor device with a via, which achieves low TSV-to-GND (Through Silicon Via to Ground) capacitance as well as reduced TSV-to-TSV crosstalk capacitance.

[0018] Fig. 3 shows a semiconductor device 300 according to various embodiments.

[0019] The semiconductor device 300 may include a semiconductor substrate 310 including a first semiconductor layer 312 and a second semiconductor layer 314 arranged on the first semiconductor layer 312. The second semiconductor layer 314 may include one of a doped semiconductor layer or a buried insulator layer. The semiconductor device 300 may further include a via 320 extending through the semiconductor substrate 310. The via 320 has a first portion 322 extending through the first semiconductor layer 312 and a second portion 324 extending through the second semiconductor layer 314. The semiconductor device 300 may further include an insulating structure 330 extending through the first semiconductor layer 312 and arranged under the second semiconductor layer 314. The insulating structure 330 at least partially surrounds the first portion 322 of the via 320, and is separated from the first portion 322 of the via by a portion of the first semiconductor layer 312. [0020] In other words, various embodiments provides a semiconductor device 300, in which a via structure 320 is provided with both horizontal isolation structure 314 and vertical isolation structure 330 under the horizontal isolation structure 314, so as to reduce the capacitance of the via structure 320.

[0021] According to various embodiments, the insulating structure 330 may be a continuous annular structure surrounding the first portion 322 of the via 320, or may not be a continuous structure but only partially surrounds the first portion 322 of the via 320. The insulating structure 330 may be disposed at a distance away from the first portion 322 of the via, with a portion of the first semiconductor layer 312 located inbetween the via 320 and the insulating structure 330.

[0022] According to various embodiments, the via 320 may be formed within an opening through the semiconductor substrate 310. In this context, the via extending through the semiconductor substrate may be referred as a through silicon/substrate via (TSV). The via may include an insulating liner 326 formed at a wall of the opening, and a conductive fill 328 formed within the opening with the insulating liner 326 surrounding the conductive fill 328. The insulating liner 326 may be an oxide layer, e.g. a silicon dioxide layer, or may be a nitride layer, e.g. a silicon nitride layer, or may be other types of insulating materials. The conductive fill 328 may include a conductive material, such as metal or alloy (e.g. copper or tungsten or an alloy of copper or tungsten), or polysilicon.

[0023] According to various embodiments, the second semiconductor layer 314 may further include one or more transistors. According to various embodiments, the second semiconductor layer 314 may not include a transistor.

[0024] According to various embodiments, the insulating structure 330 may include a layer of insulating material, for example, a layer of silicon dioxide. [0025] According to various embodiments, the insulating structure 330 may include an air duct.

[0026] According to various embodiments, the semiconductor substrate 310 may be a silicon-on-insulator (SOI) substrate. The first semiconductor layer 312 may be a silicon body layer, and the second semiconductor layer 314 may include a silicon film and the buried insulator layer (as shown in Fig. 4 below). The buried insulator layer may be arranged between the silicon film and the silicon body layer. The buried insulator layer may be a silicon dioxide (Si0 ₂ ) layer or may be a layer of air, for example.

[0027] In various embodiments, the silicon film of the second semiconductor layer 314 may be a thin layer of about 150nm. The silicon film is arranged on top of the buried insulator layer, and may be configured to serve as a layer where FEOL (Front-End-Of- Line) transistors may be placed. In various embodiments, the buried insulator layer may act as an etch stop layer when the SOI wafer is used for fabrication.

[0028] In various embodiments, a capacitance produced by the buried insulator layer in the second semiconductor layer 314 may be in connection with a capacitance of the via 320. For example, as shown in Figs. 6A and 6B below, the capacitance Chorizontai produced by the buried insulator layer may be in connection with the capacitance C _T sv siHim, CTsv siBody of the via.

[0029] In various embodiments, the insulating structure 330 may be in contact with a surface of the buried insulator layer, for example, a bottom surface of the buried insulator layer of the second semiconductor layer 314. The insulating structure 330 may extend vertically from the bottom surface of the silicon body layer 312 of the SOI substrate 310 till the bottom surface of the buried insulator layer (as shown in Fig. 4 below).

[0030] According to various embodiments, the first semiconductor layer 312 may be a silicon body layer, and the second semiconductor layer 314 may include a silicon film and the doped semiconductor layer (as shown in Fig. 5 below). The semiconductor substrate 310 may be a bulk silicon substrate. The doped semiconductor layer may be doped with a first conductivity type dopants, e.g., n-type dopants, at a first doping concentration, and may be arranged between the silicon film and the silicon body layer. In various embodiments, the doped semiconductor layer may be a heavily doped layer, e.g. with the first doping concentration selected from a range from 10 /cm to 10 /cm .

[0031] In various embodiments, the silicon film of the second semiconductor layer 314 may be a thin layer of about 150nm. The silicon film is arranged on top of the doped semiconductor layer, and may serve as a layer where FEOL (Front-End-Of-Line) transistors may be placed.

[0032] In various embodiments, a capacitance produced by the doped semiconductor layer in the second semiconductor layer 314 may be in connection with a capacitance of the via 320. For example, as shown in Figs. 6A and 6B below, the capacitance Chorizontai produced by the doped semiconductor layer may be in connection with the capacitance

CTSV_SiFilm, Cxsv_SiBody of the Via.

[0033] In various embodiments, the insulating structure 330 may be in contact with a surface of the doped semiconductor layer, for example, a bottom surface of the doped semiconductor layer of the second semiconductor layer 314. The insulating structure 330 may extend vertically from the bottom surface of the silicon body layer 312 till the bottom surface of the doped semiconductor layer (as shown in Fig. 5 below).

[0034] In various embodiments, the silicon body layer 312 and the silicon film of the second semiconductor layer 314 may be un-doped, or may be doped with a second conductive type dopants at a second doping concentration. The second conductive type dopants, e.g. p-type dopants, are opposite to the first conductive type dopants, and the second doping concentration is lower than the first doping concentration. In various embodiments, the silicon body layer 312 and the silicon film may be lightly doped, for example, with a doping concentration selected from a range from 10 ¹³ /cm ³ to 10 ¹⁶ /cm ³ .

[0035] According to various embodiments, the first semiconductor layer 312 may be a silicon body layer, and the second semiconductor layer 314 may include or may be the doped semiconductor layer doped with a first conductivity type dopants (as shown in Fig. 7 below). The first conductivity type dopants may be n-type dopants, for example. In various embodiments, the first semiconductor layer 312 may be un-doped, or may be doped with a second conductivity type dopants opposite to the first conductivity type dopants of the doped semiconductor layer. For example, the first semiconductor layer 312 may be a p-Si layer, and the second semiconductor layer 314 may be an n-Si layer, and vice versa.

[0036] In various embodiments, the doping concentration of the first semiconductor layer 312 may be substantially similar to or may be different from the doping concentration of the second semiconductor layer 314. The doping concentration of the first semiconductor layer 312 and of the second semiconductor layer 314 may be selected from a range from 10 ¹³ /cm ³ to 10 ¹⁶ /cm ³ .

[0037] In various embodiments, the doped semiconductor layer may include one or more transistors. In various embodiments, a capacitance produced by the one or more transistors may be in connection with a capacitance of the via 320. For example, as shown in Figs. 8A and 8B below, the capacitances Ch ₀ rizontai_pnp, Ch ₀ rizontai_ n _P n produced by the one or more transistors may be in connection with the capacitance Cxsv_nweii, CJSV Body of the via.

[0038] In various embodiments, the insulating structure 330 may be in contact with a surface of the doped semiconductor layer 314, for example, a bottom surface of the doped semiconductor layer 314. The insulating structure 330 may extend vertically from the bottom surface of the silicon body layer 312 till the bottom surface of the doped semiconductor layer 314 (as shown in Fig. 7 below).

[0039] The semiconductor device as described in various embodiments above may be used or included in a 2.5D through silicon interposer, or in a 3D integrated circuit device.

[0040] Various embodiments further provide a through silicon interposer (TSI) having a semiconductor device of various embodiments above. 2.5 dimensional (2.5D) integrated circuit is a form of 3D IC integration, and combines silicon interposer, microbump and TSV technologies to enable integration of heterogeneous, multi-die systems in a single package. The interposer or the through silicon interposer (TSI) may be utilized for interconnection in a 2.5D integrated circuit, and may be referred to as a 2.5D TSI.

[0041] Various embodiments further provide a three dimensional integrated circuit device having a semiconductor device of various embodiments above. The three dimensional integrated circuit device may be referred to as a 3D IC device, using the semiconductor structure of various embodiments for vertical interconnections among vertically stacked dies/circuits/components.

[0042] Various embodiments of the semiconductor device are described in more detail with regard to respective figures below.

[0043] Fig. 4 shows a semiconductor device 400 according to various embodiments.

[0044] The semiconductor device 400 of Fig. 4 is similar to the semiconductor device 300 of Fig. 3 above. Various embodiments of the semiconductor device 300 described above are analogously valid for the semiconductor device 400 of Fig. 4, and vice versa.

[0045] Similar to the embodiments of Fig. 3 described above, the semiconductor device 400 of Fig. 4 includes a semiconductor substrate 310 including a first semiconductor layer 312 and a second semiconductor layer 314 arranged on the first semiconductor layer 312. The semiconductor device 400 may further include a via 320 extending through the semiconductor substrate 310. In the embodiments of Fig. 4, a plurality of vias 320 are included in the semiconductor device 400. The via 320 has a first portion extending through the first semiconductor layer 312 and a second portion extending through the second semiconductor layer 314. The semiconductor device 400 may further include an insulating structure 330 extending through the first semiconductor layer 312 and arranged under the second semiconductor layer 314. The insulating structure 330 at least partially surrounds the first portion of the via 320, and is separated from the first portion of the via by a portion of the first semiconductor layer 312.

[0046] In the embodiments of Fig. 4, the semiconductor substrate 310 may be a silicon-on-insulator (SOI) substrate. The first semiconductor layer 312 may be a silicon body layer, and the second semiconductor layer 314 may include a silicon film 418 and the buried insulator layer 416. The buried insulator layer 416 may be arranged between the silicon film 418 and the silicon body layer 312. The buried insulator layer 416 may be a buried oxide (box) layer, for example, a silicon dioxide (Si0 ₂ ) layer.

[0047] In various embodiments, the silicon film 418 of the second semiconductor layer 314 may be a thin layer, for example, with a thickness t _S j of about 150nm. The silicon film 418 is arranged on top of the buried insulator layer 416. In various embodiments, the buried insulator layer 416 may act as an etch stop layer when the SOI wafer is used for fabrication.

[0048] According to various embodiments, the second semiconductor layer 314 may further include one or more transistors, e.g. in the silicon film 418. According to various embodiments, the second semiconductor layer 314 may not include a transistor.

[0049] In various embodiments, the insulating structure 330 may be in contact with a surface of the buried insulator layer 416, for example, a bottom surface of the buried insulator layer 416. The insulating structure 330 may extend vertically from the bottom surface of the silicon body layer 312 till the bottom surface of the buried insulator layer 416. The insulating structure 330 may include a layer of insulating material, or may include an air duct.

[0050] The via 320 may be formed within an opening through the semiconductor substrate 310. Each via may include an insulating liner formed at a wall of the opening, and a conductive fill (e.g. Cu) formed within the opening with the insulating liner surrounding the conductive fill. The insulating structure 330 may be an annular structure surrounding the first portion of the via 320, or may be only partially surrounding the first portion of the via 320.

[0051] In various embodiments of Fig. 4, two vias 320 are shown which are connected to respective input/output (I/O-l and 1/0-2) and are used as data signal TSVs. Since the dominant impact of parasitic capacitance (C _T sv) of TSV architectures on electrical performance of 3D circuits and systems cannot be ignored, and C _TS v of data signal TSVs is desired to be reduced as much as possible to build high speed data signaling in 2.5D TSI and 3D ICs. Accordingly the vias 320 are provided with horizontal insulator layer 416 and vertical insulating structures 330 to reduce the capacitance of the vias 320 according to various embodiments.

[0052] Fig. 4 also shows a power/ground via 440 which is connected to power/ground (P/G). TSVs carrying power/ground signals will be benefited by high decoupling capacitance, which may enable reliable power/ground networks. Hence, the TSV capacitance of the power/ground TSVs is desired to be as large as possible acting as a decoupling capacitor. Accordingly, the power/ground TSV 440 is not provided with insulating structure 330 as shown in the semiconductor device 400.

[0053] In the embodiments of Fig. 4, one or both of the silicon body layer 312 and the silicon film 418 may be an un-doped silicon layer, or may be a lightly doped layer with a doping concentration selected from a range from 10 ¹³ /cm ³ to 10 ¹⁶ /cm ³ . For example, the silicon body layer 312 and/or the silicon film 418 may be a p-silicon layer, or an n-silicon layer.

[0054] The semiconductor substrate 310 may be grounded through substrate contacts formed in the silicon film 418, e.g. ohmic p+ contact as shown in Fig. 4.

[0055] Fig. 5 shows a semiconductor device 500 according to various embodiments.

[0056] Various embodiments of the semiconductor device 300, 400 described above are analogously valid for the semiconductor device 500 of Fig. 5, and vice versa.

[0057] The semiconductor device 500 of Fig. 5 is similar to the semiconductor device 400 of Fig. 4 above, with the difference that the second semiconductor layer 314 includes a silicon film 518 and the doped semiconductor layer 516. The doped semiconductor layer 516 may be doped with a first conductivity type dopants, e.g., n-type dopants, at a first doping concentration, and may be arranged between the silicon film 516 and the silicon body layer 312.

[0058] According to various embodiments, the semiconductor device 500 may be formed by providing a bulk silicon wafer, in which a buried doped layer 516 is formed, such that the portion of the bulk silicon wafer below the buried doped layer 516 serves as the first semiconductor layer 312 (also referred to as the silicon body layer in this embodiment), and the portion of the bulk silicon wafer above the buried doped layer 516 serves as silicon film 518 of the second semiconductor layer 314.

[0059] In various embodiments, the doped semiconductor layer 516 may be a heavily doped layer, e.g. with the first doping concentration selected from a range from 10 ¹⁸ /cm ³ to 10 ²² /cm ³ . The doped semiconductor layer 516 may be an n ⁺ -doped layer as shown in Fig. 5, or may be a p ⁺ -doped layer in other embodiments. [0060] In various embodiments, the silicon body layer 312 and the silicon film 518 of the second semiconductor layer 314 may be un-doped, or may be doped with a second conductive type dopants at a second doping concentration. The second conductive type dopants, e.g. p-type dopants, are opposite to the first conductive type dopants of the doped semiconductor layer 516. The second doping concentration may be lower than the first doping concentration of the doped semiconductor layer 516. In various embodiments, the silicon body layer 312 and the silicon film 518 may be lightly doped, for example, p- silicon with a doping concentration selected from a range from 10 ¹³ /cm ³ to 10 ¹⁶ /cm ³ .

[0061] In various embodiments, the insulating structure 330 may be in contact with a surface of the doped semiconductor layer 516, for example, a bottom surface of the doped semiconductor layer 516 of the second semiconductor layer 314. The insulating structure 330 may extend vertically from the bottom surface of the silicon body layer 312 till the bottom surface of the doped semiconductor layer 516.

[0062] Similar to Fig. 4, two vias 320 which are connected to respective input/output (I/O-l and 1/0-2) and used as data signal TSVs are shown in the embodiments of Fig. 5. The vias 320 are provided with horizontal doped semiconductor layer 516 and vertical insulating structures 330 to reduce the capacitance of the vias 320 according to various embodiments.

[0063] Similar to Fig. 4, the semiconductor device 500 of Fig. 5 also shows a power/ground via 440 which is connected to power/ground (P/G). The power/ground TSV 440 is not provided with insulating structure 330 as shown in the semiconductor device 500.

[0064] The semiconductor substrate 310 may be grounded through substrate contacts formed in the silicon film 518, e.g. ohmic p+ contact as shown in Fig. 5. [0065] Fig. 6A shows a TSV-to-GND lumped "RC" model 600 for the semiconductor device 400, 500 of Figs. 4 and 5 according to various embodiments. Fig. 6B shows a TSV- to-TSV crosstalk "RC" model 650 for the semiconductor device 400, 500 of Figs. 4 and 5 according to various embodiments.

[0066] In Fig. 6A and 6B, R _TS v denotes the TSV resistance. CJSV siFiim denotes the top-side TSV capacitance contribution, e.g. the capacitance of the portion of the via 320 extending through the silicon film 418, 518. Cxsv_siBody denotes the bottom-side TSV capacitance contribution, e.g. the capacitance of the portion of the via 320 extending through the silicon body layer 312. Choriz _o n _ta i denotes the contribution of the small area horizontal layer capacitance, wherein the horizontal layer is the buried insulator layer 416 or the doped semiconductor layer 516. C _vert i _c ai denotes the capacitance of the vertical insulating structure 330 in the silicon body layer 312. C _ump denotes the C4 bump to silicon body capacitance, and C _P/G is the capacitance of the large area horizontal capacitance accounting P/G coupling from the silicon film 418, 518 to the silicon body 312.

[0067] As shown in Fig. 6A and 6B, the capacitance produced by the buried insulator layer 416 or the doped semiconductor layer 516, Ch _o riz _o n _t ai, may be in connection with the capacitance of the via 320, C _TS v_siFiim and C _T sv_siBod _y ·

[0068] The respective capacitances shown in Figs. 6A and 6B can be determined according to the following equations:

[0069] C _xsv _siBody ⁼ ^TSV " tsiBody/ (t _s i + t-box + tsiBody )

[0070] C _xsv _SiFilm ⁼ ^TSV ' tsi/(t _s i + tbox + t _siBody )

[0071] C _hor j _zonta i = £ ₀ £ _ox ir(R _a nnularInner ^{— r} TSv) ² Abox

[0072] C _vert j _ca j = 2πε ₀ ε _Ο χ tsiBody/ ^m (Rannu)arOuter/RannularInner)

[0073] wherein C _norizonta i « C _P / _G ; C _vertical « C _P/G ; t _si « t _siBody · [0074] wherein t _si represents the thickness of the silicon film 418, 518. t _box represents the thickness of the horizontal insulator layer 416 and the thickness of the horizontal doped semiconductor layer 516. t _sjBody represents the thickness of the silicon body layer 312. r _xsv represents the radius of the via 320. R _an nuiarinner represents the radius from the center of the via 320 to the proximal end of the insulating structure 330, as shown in Figs. 4 and 5. R _an nuiarOuter represents the radius from the center of the via 320 to the distal end of the insulating structure 330, as shown in Figs. 4 and 5. ε ₀ represents the vacuum permittivity. ε _οχ represents the dielectric constant of the horizontal insulator layer 416, e.g., the dielectric constant of silicon dioxide; or represents the dielectric constant of the doped semiconductor layer 516, e.g. the dielectric constant of silicon.

[0075] By introducing Chonzontai and C _ve rticai provided by the buried horizontal structure 416, 516 and the vertical insulating structure 330 of semiconductor device 400, 500, the reduction of TSV-to-GND capacitance and TSV-to-TSV crosstalk capacitance can be achieved according to the models of Fig. 6A and 6B, which will be described in more details below.

[0076] Fig. 7 shows a semiconductor device 700 according to various embodiments.

[0077] Various embodiments of the semiconductor device 300, 400, 500 described above are analogously valid for the semiconductor device 700 of Fig. 7, and vice versa.

[0078] The semiconductor device 700 of Fig. 7 is similar to the semiconductor device 400, 500 above, with the difference that the second semiconductor layer 314 is the doped semiconductor layer. The doped semiconductor layer 314 may be doped with a first conductivity type dopants, e.g., n-type dopants, at a first doping concentration, and may be arranged on the first semiconductor layer 312 which is a silicon body layer. The doped semiconductor layer 314 may be referred to as a well layer or a deep well layer. For example, the doped semiconductor layer 314 may be an n-doped layer, also referred to as deep n-well.

[0079] In various embodiments, the first semiconductor layer 312 may be un-doped, or may be doped with a second conductivity type dopants opposite to the first conductivity type dopants of the doped semiconductor layer. For example, the first semiconductor layer 312 may be a p-Si body layer, and the doped semiconductor layer 314 may be an n- Si layer, and vice versa.

[0080] In various embodiments, the doping concentration of the first semiconductor layer 312 may be substantially similar to or may be different from the doping concentration of the doped semiconductor layer 314. The doping concentration of the first semiconductor layer 312 and of the doped semiconductor layer 314 may be selected from a range from 10 ¹³ /cm ³ to 10 ¹⁶ /cm ³ .

[0081] In various embodiments, the doped semiconductor layer 314 may include one or more transistors. In an exemplary embodiment, the doped semiconductor layer 314 may include a PNP transistor 750 and an NPN transistor 752. The doped semiconductor layer 314 may include other types of transistors in other embodiments. In various embodiments, a capacitance produced by the one or more transistors 750, 752 may be in connection with a capacitance of the via 320. For example, as shown in Figs. 8A and 8B below, the capacitances Ch ₀ rizontai_pnp, Ch _or izontai_npn produced by the transistors 750, 752 may be in connection with the capacitance Cxsv nweii, Cxsv Body of the via 320.

[0082] In various embodiments, the insulating structure 330 may be in contact with a surface of the doped semiconductor layer 314, for example, a bottom surface of the deep well layer 314. The insulating structure 330 may extend vertically from the bottom surface of the silicon body layer 312 till the bottom surface of the deep well layer 314. [0083] According to the embodiments of Fig. 7, the insulating structures 330 are formed only in the first semiconductor layer 312 and stops at the bottom surface of the second semiconductor layer 314, so that the second semiconductor layer 314 may provide sufficient space to place other components, such as FEOL transistors.

[0084] Similar to Fig. 4 and Fig. 5, two vias 320 which are connected to respective input/output (I/O-l and I/0-2) and used as data signal TSVs are shown in the embodiments of Fig. 7. The vias 320 are provided with horizontal doped semiconductor layer 314 and vertical insulating structures 330 to reduce the capacitance of the vias 320 according to various embodiments. The semiconductor device 700 of Fig. 7 also shows a power/ground via 440 which is connected to power/ground (P/G). The power/ground TSV 440 is not provided with insulating structure 330 as shown in the semiconductor device 700.

[0085] Fig. 8A shows a TSV-to-GND lumped "RC" model 800 for the semiconductor device 700 of Fig. 7 according to various embodiments. Fig. 8B shows a TSV-to-TSV crosstalk "RC" model 850 for the semiconductor device 700 of Fig. 7 according to various embodiments.

[0086] In Fig. 8A and 8B, R _TS v denotes the TSV resistance. C _T sv_nweii denotes the topside TSV capacitance contribution, e.g. the capacitance of the portion of the via 320 extending through the n-well layer 314. C _T sv_Body denotes the bottom-side TSV capacitance contribution, e.g. the capacitance of the portion of the via 320 extending through the silicon body layer 312. Ch ₀ rizontai_pnp denotes the capacitance contribution of the PNP transistor 750 formed in the n-well layer 314, and Ch ₀ nzontai_npn denotes the capacitance contribution of the NPN transistor 752 formed in the n-well layer 314. C _ver ticai denotes the capacitance of the vertical insulating structure 330 in the silicon body layer 312. Cbump denotes the C4 bump to silicon body capacitance, and CP/G is the capacitance of the large area horizontal capacitance accounting P/G coupling from the well layer 314 to the silicon body 312.

[0087] As shown in the embodiments of Fig. 8 A and 8B, the capacitances produced by the transistors 750, 752, C _ho rizontai _pn _P , Ch ₀ rizontai_npn, may be in connection with the capacitance of the via 320, C _T sv_nweii and Cxsv Body

[0088] The respective capacitances shown in Figs. 8A and 8B can be determined according to the following equations:

[0089] C _T sv Body ⁼ C _TSV ^■ t _Bo dy/ (tnwell + tBody )

[0090] C _TSV _nwell ⁼ C _TSV ^■ tnwell/ (Well + tBod )

[0091] C _vert j _ca i = 2πε ₀ ε _οχ t _Bod y/ln(R _annuIar0uter /R _annu ] _ar i _nner )

[0092] wherein C _horizonta i _pnp « C _P / _G ; C _vertica i « C _P / _G ; t _nwell « t _Body .

[0093] wherein t _nwe u represents the thickness of the n-well layer 314. t _Body represents the thickness of the silicon body layer 312. R _ann uiarinner represents the radius from the center of the via 320 to the proximal end of the insulating structure 330, as shown in Fig. 7. R _a nnuiarOuter represents the radius from the center of the via 320 to the distal end of the insulating structure 330, as shown in Fig. 7. ε ₀ represents the vacuum permittivity. ε _οχ represents the dielectric constant of silicon dioxide.

[0094] By introducing Chorizontai _pn _P , Chorizontai _j ipn and Cverticai provided by the n-well layer 314 and the transistors formed therein, as well as the vertical insulating structure 330 of semiconductor device 700, the reduction of TS V-to-GND capacitance and TS V-to-TS V crosstalk capacitance can be achieved according to the models of Fig. 8 A and 8B.

[0095] Various embodiments above provide TSV architecture with horizontal and vertical isolation regions at least partially surrounding the TSV to achieve low TSV-to-

GND capacitance as well as reduced TSV-to-TSV crosstalk capacitance. Significant crosstalk through the substrate will also be eliminated according to various embodiments above. Further, there are also no constraints on the area of power/ground wires on the BEOL lines.

[0096] In addition, the structure of various embodiments above provides the horizontal isolation structure above the vertical isolation structure, which may provide space to house hundreds, thousands or millions of FEOL transistors, without waste or loss of silicon area for placing transistors. This is advantageous over conventional approaches which include thicker vertical annular isolation regions surrounding the entire height of the TSV in order to achieve lower TSV-to-GND capacitance but result in larger loss of top silicon real estate occupied by the annular isolation regions.

[0097] Table 1(a) and (b) below show the experimental results illustrating the TSV-to- GND and TSV-to-TSV capacitance reduction achieved using the semiconductor device 400 of Fig. 4 above in 2.5D ICs, for Si0 ₂ filled vertical annular isolations 330 and air filled annular isolations 330 respectively.

[0098] In the experiment, TSV node with Diameter/Height/Oxide Liner thickness = 5 um/50 urn/ 100 nm resulting in the TSV-to-GND capacitance of 50 fF, and TSV node with Diameter/Height/Oxide Liner thickness = 12 um/100 um/ 1000 nm resulting in the TSV- to-GND capacitance of 100 fF are used. The C4 bump capacitance to the silicon substrate is assumed to be 100 fF. Hence the total TSV capacitance in addition to C4 bump capacitance to ground capacitance is 150 fF in case of 5/50/1000nm TSVs, and 200 fF in case of 12 um/100 um/ 1000 nm TSVs. The thickness of the horizontal oxide insulator layer 416 is chosen as 1 μπι. The vertical isolation thickness, i.e. the thickness RannuiarOuter ~ Rannuiarinner °f the vertical annular insulating structure 330 filled with Si0 ₂ is 3.25 μηι, at the vertical annular diameter 2R _annularInner of 6.5 μπι for 5/50/100 TSVs. And the vertical isolation thickness of the vertical annular insulating structure 330 filled with Si0 ₂ is 12 μηι at the vertical annular diameter of 14 μπι for 12/100/1000 TSVs. Table 1(a) TSV-to-GND and TSV-to-TSV capacitance reduction using the semiconductor device 400 of Fig. 4 with horizontal buried oxide layer and vertical

Si0 ₂ insulating structure in 2.5D IC

[0099] From the results of Table 1 (a), the TSV-to-GND capacitance of the TSV 320 in the semiconductor device 400 is estimated to be 15.7 fF (-90% reduction) and 24.1 fF (-88% reduction) for 5/50/100 and 12/100/1000 TSVs, respectively, compared with the conventional TSV structure e.g. the TSV 220 of Fig. 2 without the horizontal and vertical structures which has TSV-to-GND capacitance of 150 fF and 200 fF for 5/50/100 and 12/100/1000 TSVs, respectively. On the other hand, TSV-to-TSV capacitance of the TSV 320 in the semiconductor device 400 is estimated as 7.1fF and 9.8 fF for 5/50/100 and 12/100/1000 TSVs. This also achieves great reduction compared with the conventional TSV structure, e.g. the TSV 220 of Fig. 2 without the horizontal and vertical isolation structures, which has TSV-to-TSV capacitance of 75 fF and 100 fF for 5/50/100 and 12/100/1000 TSVs.

Table 1(b) TSV-to-GND and TSV-to-TSV capacitance reduction using the semiconductor device 400 of Fig. 4 with horizontal buried oxide layer and vertical air duct insulating structure in 2.5D IC

[00100] For the TSV structure of Fig. 4 with air filled ducts 330, the TSV-to-GND capacitance reduction achieved is even larger at 5.7 fF (-96% reduction) achieved for 5/50/100 TSVs and 10.6 fF (-94% reduction) achieved for 12/100/1000 TSVs, as shown in Table 1(b).

[001011 The reduced TSV-to-GND and TSV-to-TSV capacitances as achieved by the semiconductor device of various embodiments above are instrumental in achieving better interconnections through TSV and C4 bumps. [00102] Fig. 9A depicts the eye diagram simulations at 56 GHz for conventional 12/100/1000 TSVs without horizontal and vertical isolations. Fig. 9B depicts the eye diagram simulations at 56 GHz for 12/100/1000 TSVs with horizontal (Ιμπι) and vertical isolations (with inner radius of 14 μιη and outer radius of 38μπι) according to various embodiments above. The air-duct isolations for vertical annular isolations are considered along with 1500 Signal TSVs and 6000 P/G TSVs. It is evident from Fig. 9A and 9B that TSVs with horizontal and vertical annular isolations according to various embodiments provide much better communication with Eye Height = 98%, Eye Width = 100% and RMS Jitter = 0.06 pS. This achieves a considerable improvement compared to the conventional TSVs without horizontal and vertical annular isolations which provide Eye Height = 39%, Eye Width = 70% and RMS Jitter = 1.1 pS. With the ultralow TSV-to- GND and TSV-to-TSV crosstalk capacitance achieved by the TSV of various embodiments, better eye opening at 56GHz and lower power (<20%) dissipation are achieved. Further, there is no loss of real estate in the second semiconductor layer which can be used to place transistors next to TSVs.

[00103] Fig. 10 illustrates crosstalk reduction achieved using the horizontal and vertical isolations around 12/100/1000 TSVs according to various embodiments.

[00104] As shown in Fig. 10, the TSVs provided with horizontal (1 μιη) isolation 416 and vertical annular air duct isolations 330 (with inner radius = 14 μιη and outer radius =

38 μηι), for example, according to the embodiments of Fig. 4 above, result in 8% victim voltage/crosstalk reduction on a p-Si substrate with 0.01 Ω -cm resistivity, compared with

2.5D conventional TSVs without horizontal and vertical isolations.

[00105] Fig. 11A depicts the eye diagram simulations at 56 GHz for conventional

5/50/100 TSVs without horizontal and vertical isolations. Fig. 11B depicts the eye diagram simulations at 56 GHz for 5/50/100 TSVs with horizontal and vertical isolations (with inner radius of 6.5 μη and outer radius of 13μηι) according to various embodiments above. The air-duct isolations for vertical annular isolations are considered along with 1500 Signal TSVs and 6000 P/G TSVs. It is evident from Fig. 11A and 11B that TSVs with horizontal and vertical annular isolations according to various embodiments provide much better communication with Eye Height = 100%, Eye Width = 100% and RMS Jitter = 0.0 pS. This achieves huge improvement compared to the conventional TSVs without horizontal and vertical annular isolations which provide Eye Height = 61%, Eye Width = 85% and RMS Jitter = 1.6 pS. With the ultralow TSV-to-GND and TSV-to-TSV crosstalk capacitance achieved by the TSV of various embodiments, better eye opening at 56GHz and lower power (<20%) dissipation are achieved. Further, there is no loss of real estate in the second semiconductor layer which can be used to place transistors next to TSVs.

[00106] Various embodiments further provide a method of forming a semiconductor device.

[00107] Fig. 12 shows a flowchart 1200 illustrating a method of forming a semiconductor device, for example, the semiconductor device 300, 400, 500, 700 above, according to various embodiments. Various embodiments described in relation to the semiconductor device are analogously valid for the method, and vice versa.

[00108] At 1202, a semiconductor substrate is provided including a first semiconductor layer and a second semiconductor layer arranged on the first semiconductor layer. The second semiconductor layer includes one of a doped semiconductor layer or a buried insulator layer.

[00109] At 1204, a via extending through the semiconductor substrate is formed, wherein the via has a first portion extending through the first semiconductor layer and a second portion extending through the second semiconductor layer. [00110] At 1206, an insulating structure extending through the first semiconductor layer and arranged under the second semiconductor layer is formed, wherein the insulating structure at least partially surrounds the first portion of the via and is separated from the first portion of the via by a portion of the first semiconductor layer.

[00111] According to various embodiments, the insulating structure may be formed by forming an opening at least partially surrounding the first portion of the via at a predetermined distance away from the first portion of the via, and filling the opening with an insulating material. The opening extends through the first semiconductor layer and stops under the second semiconductor layer.

[00112] According to various embodiments, the insulating structure may be formed by forming an opening at least partially surrounding the first portion of the via at a predetermined distance away from the first portion of the via, and sealing the opening with air filled in the opening. The opening extends through the first semiconductor layer and stops under the second semiconductor layer.

[00113] According to various embodiments, the method may further include forming one or more transistors in the second semiconductor layer.

[00114] Fig. 13 shows a flowchart 1300 illustrating a fabrication process for forming a semiconductor device, for example, the semiconductor device 400 of Fig. 4, according to various embodiments. Various embodiments described in relation to the semiconductor device and the method above are analogously valid for the process of Fig. 13, and vice versa.

[00115] According to various embodiments, the process development of the proposed TSVs with horizontal and vertical isolation layers can be easily achieved on SOI substrates with thicker Buried Oxide (BOX) Layers, which can act as an etch stop for the vertical annular isolation to be etched from the back-side of the wafer as described in the fabrication flow shown in Fig. 13.

[00116] At 1302, a FEOL processing on SOI wafers is carried out. At 1304, TSV is manufactured in via middle or via first region. TSV via middle or via first fabrication flows could be leveraged followed up with the front-side Cu-damascene processing at 1306.

[00117] After the front-side damascene at 1306, Guest dies could be attached on interposes at 1308, for example, using the Chip-to-wafer (C2W) fashion. At 1310, the wafer is then bonded to the temporary carrier, e.g., a silicon carrier wafer, to enable the back-side processing below.

[00118] At 1312, a back-side annular etch with SOI BOX (buried oxide) layer acting as an etch stop is realized on the silicon wafer attached to the temporary carrier.

[00119] At 1314, vertical annular air/insulator ducts are filled and sealed, e.g., using polymer or deposited Si0 ₂ .

[00120] At 1316, TSVs are opened for C4 bump attachment on the TSVs to follow up with further processing.

[00121] Fig. 14 shows a flowchart 1400 illustrating a fabrication process for forming a semiconductor device, for example, the semiconductor device 700 of Fig. 7, according to various embodiments. Various embodiments described in relation to the semiconductor device and the method above are analogously valid for the process of Fig. 14, and vice versa.

[00122] At 1402, n-well and p-well are constructed, for example in a silicon substrate. FEOL transistors, e.g. nMOS and pMOS, are then formed at 1404.

[00123] At 1406, TSV is manufactured in via middle or via first region, followed up with the front-side Cu-damascene processing at 1408. [00124] After the front-side damascene at 1408, Guest dies are attached on interposes at 1410, for example, using the Chip-to-wafer (C2W) fashion. At 1412, the wafer is then bonded to the temporary carrier, e.g., a silicon carrier wafer, to enable the back-side processing below.

[00125] At 1414, a back-side annular etch is carried out on the silicon wafer attached to the temporary carrier, to form annular air/insulator ducts with etch stop at the n-well depth.

[00126] At 1416, the annular air/insulator ducts are filled and sealed, e.g., using polymer or deposited Si0 ₂ .

[00127] At 1418, TSVs are opened for C4 bump attachment on the TSVs.

[00128] According to various embodiments above, TSV architectures resulting in ultralow TSV capacitance as well as crosstalk immune TSVs are provided. The resulting capacitive contact is instrumental in reducing the TSV-to-GND capacitance compared to the existing TSV and micro-bump pad capacitance in 2.5D ICs. The resulting reduction in TSV capacitance values would enable better signal integrity (SI). The structure can be easily manufactured on Si or SOI wafers with back side etching for annular insulation formation.

[00129] While the invention has been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.