Title:
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREOF
Document Type and Number:
WIPO Patent Application WO/2001/099168
Kind Code:
A1
Abstract:
A semiconductor device has the multilayer wiring structure that includes at least one insulating layer having a set of conducting parts of an area of 500 µm?2¿ or greater and a width of 1.0 µm or narrower. A method of manufacturing such a semiconductor device comprises a chemical and mechanical polishing step for smoothing the surface of the insulating layer (501), a washing step for washing the smoothed surface of the insulating layer with chemical solution (502), and a rinsing step for removing the chemical solution (503). The rinsing step uses water containing dissolved oxygen less than 6 ppm by weight.
Inventors:
HORIUCHI HIROSHI (JP)
YAMAMOTO TAMOTSU (JP)
TAKIGAWA YUKIO (JP)
SUZUKI SHIGERU (JP)
SANTO NOBUAKI (JP)
MIYAJIMA MOTOSHU (JP)
YAMAMOTO TAMOTSU (JP)
TAKIGAWA YUKIO (JP)
SUZUKI SHIGERU (JP)
SANTO NOBUAKI (JP)
MIYAJIMA MOTOSHU (JP)
Application Number:
PCT/JP2000/004164
Publication Date:
December 27, 2001
Filing Date:
June 23, 2000
Export Citation:
Assignee:
FUJITSU LTD (JP)
HORIUCHI HIROSHI (JP)
YAMAMOTO TAMOTSU (JP)
TAKIGAWA YUKIO (JP)
SUZUKI SHIGERU (JP)
SANTO NOBUAKI (JP)
MIYAJIMA MOTOSHU (JP)
HORIUCHI HIROSHI (JP)
YAMAMOTO TAMOTSU (JP)
TAKIGAWA YUKIO (JP)
SUZUKI SHIGERU (JP)
SANTO NOBUAKI (JP)
MIYAJIMA MOTOSHU (JP)
International Classes:
H01L21/02; H01L21/321; H01L21/768; H01L23/532; (IPC1-7): H01L21/304; H01L21/3205
Foreign References:
JP2000091277A | 2000-03-31 | |||
JP2000040679A | 2000-02-08 | |||
JPH1064870A | 1998-03-06 | |||
JPH06177102A | 1994-06-24 |
Other References:
See also references of EP 1310988A4
Attorney, Agent or Firm:
Yoshida, Minoru (Tamatsukuri-motomachi Tennoji-ku Osaka-shi, Osaka, JP)
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